CN106301305B - A kind of switching matrix drive circuit and method - Google Patents
A kind of switching matrix drive circuit and method Download PDFInfo
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- CN106301305B CN106301305B CN201610696740.2A CN201610696740A CN106301305B CN 106301305 B CN106301305 B CN 106301305B CN 201610696740 A CN201610696740 A CN 201610696740A CN 106301305 B CN106301305 B CN 106301305B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
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- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Relay Circuits (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a kind of switching matrix drive circuit and method, CPLD chip for receiving the instruction of bus interface transmission, and is decoded received instruction；Relay driving chip decodes selection output significance bit for receiving the instruction after CPLD chip decodes, and by address date SEL with CPLD chip by connection to control the corresponding actuating of relay；Wherein, the relay driving chip is M group, and any group includes N number of driving chip, selects CS with the shared piece of driving chip is organized, n-th of chip of difference group shares a switch level signal LVL, and all driving chips share an address date SEL, wherein n≤N.The beneficial effects of the present invention are: being grouped shared control signals by rationally designing driving circuit, effectively solve the problems, such as that control signal shares bring maloperation；The integrated design degree for improving switch matrix meets automatic test equipment Miniaturization Design demand.
Description
Technical field
The present invention relates to switch matrix control field, especially a kind of switching matrix drive circuit and method.
Background technique
Currently, existing switch matrix control method is not as shown in Figure 1, driving chip has data selection function, how many
The SEL signal of position, can only just drive the relay of identical digit, driving circuit is difficult to effectively simplify.The control of driving chip is believed
It number corresponds, cannot share with driving chip, it is every to increase a piece of driving chip, then it needs to increase corresponding piece choosing and switch level
Deng control signal, main control chip needs many pins of overabsorption to control these driving chips.
Traditional large-scale switches matrix, due to relay and the various complexity of control circuit, it is difficult to realization device it is small-sized
Change, occupies many space resources, be unfavorable for building for Auto-Test System.
Traditional switch matrix device, control line is attached directly to relay array after driver is pressurized and expands stream, to reach
All control signals of the accurate control of switching channels, driving circuit require individual control signal wire to control, and occupy
Very more plate grade resource, so that the expansible space of switch matrix is very small, it is difficult to adapt to the testing requirement of high speed development.
Traditional switch matrix control method, can not reasonable common drive chip control signal, control signal shares meeting
The maloperation for generating a large amount of relays, cannot achieve signal transmission and routing be precisely controlled, not can guarantee in test macro and believe
Number switching and routing that output and input.
In traditional switch matrix control method, when needing to keep a relay control signal state, it is necessary to keep it
The control signal condition of corresponding driving chip, when longtime running, caused by power consumption penalty it is very big, and be unfavorable for device
Heat dissipation.
Summary of the invention
The purpose of the present invention is to overcome above-mentioned the deficiencies in the prior art, provide a kind of switching matrix drive circuit and side
Method.
To achieve the above object, the present invention adopts the following technical solutions:
A kind of switching matrix drive circuit, comprising:
CPLD chip for receiving the instruction of bus interface transmission, and decodes received instruction；
Relay driving chip, with CPLD chip by connection, for receiving the instruction after CPLD chip decodes,
And selection output significance bit is decoded to control the corresponding actuating of relay by address date SEL；
Wherein, the relay driving chip is M group, and any group includes N number of driving chip, shares one with driving chip is organized
A piece selects CS, and n-th of chip of difference group shares a switch level signal LVL, and all driving chips share a number of addresses
According to SEL, wherein n≤N.
Preferably, the switch level signal LVL and address date SEL default conditions are low level, by driving
The high level pulse of switch level and address date pin sending time span the covering chip selection signal effectual time of chip, is realized
Switch level signal LVL and address date SEL by low level to high level jump, and after piece selects CS invalid, switch level letter
Number LVL and address date SEL is low level by high level jump.Above-mentioned design advantageously reduces entire switching matrix drive circuit
Power consumption, reduce the generation of heat.
Preferably, all driving chips share global reset signal RESET, when global reset signal RESET is effective, own
The output of driving chip is shielded.By the way that global reset signal is arranged, so that entire driving circuit is without increasing bus marco letter
Number pin, can judge the state of chip selection signal CS in bus control signal in CPLD chip, when chip selection signal CS is entirely effective,
Global reset signal RESTET signal is effective, and all driving chips share a RESET signal, to realize the function of Global reset
Energy.
Based on the driving method of above-mentioned switching matrix drive circuit, when the X of n-th of driving chip in control M group
When a output bit, the corresponding chip selection signal of M group driving chip is placed in effective status, while all driving chips in M group
X position output bit is in by mode of operation, and the present invention solves non-targeted output bit by improvement control method and is misused
The problem of；
Specific step is as follows:
Step 1 judges the grouping where the corresponding driving chip A of controlled relay, obtains point where driving chip A
Group # M；
Step 2, the driving chip for including in addition to driving chip A in the M driving chip group in query steps one；
Step 3 inquires the X output bit of driving chips all in addition to the driving chip A driving chip group Nei；
If the X position output bit state of n-th of driving chip is high in the driving chip group, in the control routine sent
The corresponding code of switch level signal LVL (n) is set to 1；
If the X position output bit state of n-th of driving chip is low in the driving chip group, in the control routine sent
The corresponding code of switch level signal LVL (n) is set to 0.
The beneficial effects of the present invention are:
1. being grouped shared control signals by rationally designing driving circuit, the service efficiency for controlling pin is maximized, and
And by state recording and inquiry, control routine is flexibly sent, effectively solves the problems, such as that control signal shares bring maloperation；
2. the present invention significantly improves the integrated design degree of switch matrix, reduce the resource and sky of control circuit occupancy
Between, meet the Miniaturization Design demand of automatic test equipment；
3. the present invention has Universal and scalability can be according to switch suitable for the switch matrix of any interface form
Matrix size flexible expansion, convenient for flexibly building for Auto-Test System.
Detailed description of the invention
Fig. 1 is existing switch matrix control method schematic diagram；
Fig. 2 is the structural schematic diagram of switching matrix drive circuit provided by the invention；
Fig. 3 is the flow chart of switch matrix driving method provided by the invention.
Specific embodiment
Present invention will be further explained below with reference to the attached drawings and examples.
In the prior art, each driving chip be all made of individual piece choosing, switch level, address date come realize operation,
However along with the expansion of switch matrix scale, the control signal for needing enormous amount controls switch matrix, so,
Control circuit resource is utilized to be minimal, the present invention provides a kind of switching matrix drive circuit and method, it can be achieved that control
The effective use of circuit resource processed.
As shown in Fig. 2, a kind of switching matrix drive circuit, comprising:
CPLD chip for receiving the instruction of bus interface transmission, and decodes received instruction；
Relay driving chip, with CPLD chip by connection, for receiving the instruction after CPLD chip decodes,
And selection output significance bit is decoded to control the corresponding actuating of relay by address date SEL；All output bits are mutually indepedent, mutually
It does not influence；
Wherein, the relay driving chip is M group, and any group includes N number of driving chip, shares one with driving chip is organized
A piece selects CS, and n-th of chip of difference group shares a switch level signal LVL, and all driving chips share a number of addresses
According to SEL, wherein n≤N.
Switch level signal LVL is used to operate the level state of output bit, and switch level signal LVL is defaulted as low electricity
Flat, piece selects when rising edge such as control switch is opened, then sends high level pulse, and control switch disconnects, then keeps low level；B
Address date SEL selection signal is defaulted as low level, and high level pulse signal, driving chip are sent when address date SEL is effective
When piece selects effective, effective output bit operated by SEL signal framing is read, reads LVL signal to determine effective output bit
Output level.
The switch level signal LVL and address date SEL default conditions are low level, pass through opening to driving chip
The high level pulse of powered-down gentle address date pin sending time span covering chip selection signal effectual time, realizes switch level
Signal LVL and address date SEL by low level to high level jump, and after piece selects CS invalid, switch level signal LVL and
Address date SEL is low level by high level jump.Above-mentioned design advantageously reduces the power consumption of entire switching matrix drive circuit,
Reduce the generation of heat.
Preferably, all driving chips share global reset signal RESET, when global reset signal RESET is effective, own
The output of driving chip is shielded.By the way that global reset signal is arranged, so that entire driving circuit is without increasing bus marco letter
Number pin, can judge the state of chip selection signal CS in bus control signal in CPLD chip, when chip selection signal CS is entirely effective,
Global reset signal RESTET signal is effective, and all driving chips share a RESET signal, to realize the function of Global reset
Energy.
Based on the driving method of above-mentioned switching matrix drive circuit, when the X of n-th of driving chip in control M group
When a output bit, the corresponding chip selection signal of M group driving chip is placed in effective status, while all driving chips in M group
X position output bit is in by mode of operation, and the present invention solves non-targeted output bit by improvement control method and is misused
The problem of；
Specific step is as follows:
All driving chips all share an address date SEL, when the X for n-th of driving chip for needing to control M group
When a output bit, this group of chip chip selection signal can be placed in effective status, and since the address date of all chips all shares, will
The X position of all driving chips in the driving chip group is caused to export all in by mode of operation, it is therefore desirable to look by state
Ask determine LVL signal in control routine each data value, set LVL as it is high when output significance bit be also it is high, judge
Process is as shown in Figure 3.Other driving chips in same group are first found out, inquire the state of the X position output bit of these chips, such as
The X position of n-th of driving chip is height in group, wherein switch level signal is expressed as LVL (n), then is sending control routine
When, the correspondence code of LVL (n) is 1, as X position be it is low, then when sending control routine, the correspondence code of LVL (n) is 0, with
This changes standing state to prevent the corresponding identical output bit of identical SEL signal with the chip of a piece of choosing to be misused.
Further, operational relay driving chip output bit is the specific steps of effective status are as follows:
When driving chip chip selection signal is effective, driving chip latch switch level signal and address date state pass through
Address data signal decoding determines which output pin of operation, and how switch level signal deciding operates and (draw high or drag down) should
Pin.
If the address date SEL of each driving chip is B, each driving chip controls A relay, driving chip
Effective output bit is determined that the numerical value of the quantity A of output pin is 2B by SEL signal interpretation, then spool is controlled needed for switch matrix
Foot quantity is that piece selects the sum of quantity, switch level number of signals and address date digit, i.e. M+N+B, simultaneously as each drive
Dynamic A relay of chip controls, driving chip sum are the divisor of total number of relays and A, i.e. driving chip sum=relay
Sum/A.Therefore, compared to Figure 1 the present invention, improves the integrated design degree of switch matrix, reduces driving circuit occupancy
Resource and space meet the miniature requirement of automatic test equipment.
The present invention by by driving chip carry out it is reasonable must be grouped, convert large-scale switches matrix majorization to that " N × M drives
The control of dynamic chip matrix ", each column share a chip selection signal, and every row shares a switch level signal, passes through chip selection signal
The grouping of " driving chip matrix " can be positioned, i.e., one group correspondence one arranges, and each driving chip is opened by different in any group
Level signal LVL is closed to be controlled.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art are not
Need to make the creative labor the various modifications or changes that can be made still within protection scope of the present invention.
Claims (5)
1. a kind of switching matrix drive circuit, characterized in that include:
CPLD chip for receiving the instruction of bus interface transmission, and decodes received instruction；
Relay driving chip for receiving the instruction after CPLD chip decodes, and leads to CPLD chip by connection
Address date SEL decoding selection output significance bit is crossed to control the corresponding actuating of relay；
Wherein, the relay driving chip is M group, and any group includes N number of driving chip, shares a piece with driving chip is organized
CS is selected, n-th of chip of difference group shares a switch level signal LVL, and all driving chips share an address date
SEL, wherein n≤N.
2. switching matrix drive circuit as described in claim 1, characterized in that the switch level signal and number of addresses it is believed that
Number default conditions are low level, pass through the switch level and address date pin sending time span emulsion sheet to driving chip
Select the high level pulse of signal effectual time realize switch level signal and address date by the jump of low level to high level, and
After piece choosing is invalid, switch level signal and address date are jumped by high level as low level.
3. switching matrix drive circuit as described in claim 1, characterized in that all driving chips share Global reset letter
Number, when global reset signal is effective, the output of all driving chips is shielded, when chip selection signal is entirely effective, Global reset letter
Number effectively.
4. the driving method based on any switching matrix drive circuit of claims 1 to 3, characterized in that when controlling M
When the X output bit of n-th of driving chip in group, the corresponding chip selection signal of M group driving chip is placed in effective status, together
When M group in the X position output bits of all driving chips be in by mode of operation；
Specific step is as follows:
Step 1 judges the grouping where the corresponding driving chip A of controlled relay, obtains the packet numbering M where it；
Step 2, the driving chip for including in addition to driving chip A in the M driving chip group in query steps one；
Step 3 inquires the X output bit of driving chips all in addition to the driving chip A driving chip group Nei；
If the X position output bit state of n-th of driving chip is height in addition to driving chip A in the driving chip group, send
The corresponding code of switch level signal LVL (n) is set to 1 in control routine；
If in the driving chip group in addition to driving chip A n-th of driving chip X position output bit state be it is low, send
The corresponding code of switch level signal LVL (n) is set to 0 in control routine.
5. the driving method of switching matrix drive circuit as claimed in claim 4, characterized in that operational relay driving chip
Output bit is the specific steps of effective status are as follows:
When driving chip chip selection signal is effective, driving chip latch switch level signal and address date state pass through address
Data-signal decoding determines the output pin of operation, and switch level signal deciding operates the mode of pin.
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| CN201610696740.2A CN106301305B (en) | 2016-08-17 | 2016-08-17 | A kind of switching matrix drive circuit and method |
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| CN201610696740.2A CN106301305B (en) | 2016-08-17 | 2016-08-17 | A kind of switching matrix drive circuit and method |
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| CN106301305B true CN106301305B (en) | 2019-01-04 |
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| CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
| CN114706799B (en) * | 2022-03-30 | 2024-06-04 | 江苏肯立科技股份有限公司 | Low-delay monitoring device and method for 256×256 switching matrix |
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| CN102545853A (en) * | 2010-12-23 | 2012-07-04 | 阿尔斯通运输股份有限公司 | Electrical switching device, in particular for switching strong electrical currents |
| CN103746686A (en) * | 2014-01-26 | 2014-04-23 | 中国电子科技集团公司第五十八研究所 | Two-dimensional extendable cascade structure for multiplexer |
| CN105510811A (en) * | 2014-10-19 | 2016-04-20 | 曾庆东 | Switch matrix test system based on bus transfer |
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2016
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Patent Citations (4)
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|---|---|---|---|---|
| US6798244B1 (en) * | 2002-05-16 | 2004-09-28 | Lattice Semiconductor Corporation | Output buffer with overvoltage protection |
| CN102545853A (en) * | 2010-12-23 | 2012-07-04 | 阿尔斯通运输股份有限公司 | Electrical switching device, in particular for switching strong electrical currents |
| CN103746686A (en) * | 2014-01-26 | 2014-04-23 | 中国电子科技集团公司第五十八研究所 | Two-dimensional extendable cascade structure for multiplexer |
| CN105510811A (en) * | 2014-10-19 | 2016-04-20 | 曾庆东 | Switch matrix test system based on bus transfer |
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