CN208766645U

CN208766645U - A kind of multi-channel serial port managing device based on FPGA

Info

Publication number: CN208766645U
Application number: CN201821248134.5U
Authority: CN
Inventors: 高计丰; 曾清祺; 陈传前
Original assignee: Fujian Star-Net Wisdom Technology Co Ltd
Current assignee: Fujian Xingwang Intelligent Technology Co., Ltd
Priority date: 2018-08-03
Filing date: 2018-08-03
Publication date: 2019-04-19
Anticipated expiration: 2028-08-03

Abstract

The utility model provides a kind of multi-channel serial port managing device based on FPGA, including a FPGA, an Exterior selector, one first serial line interface, a Transistor-Transistor Logic level conversion chip and a CPU group；The Exterior selector and CPU group are connect with the FPGA；Transistor-Transistor Logic level conversion chip one end is connect with first serial line interface, and the other end is connect with the FPGA.Utility model has the advantages that reducing the external quantity of serial ports, serial ports failure can be reported in time, reduces the maintenance cost of equipment.

Description

A kind of multi-channel serial port managing device based on FPGA

Technical field

The utility model relates to a kind of serial interface management devices, refer in particular to a kind of multi-channel serial port managing device based on FPGA.

Background technique

Carrying out debugging by serial ports is common debud mode in equipment daily maintenance, for the large size with multiple serial ports Equipment often has multiple subsystems in the inside of equipment, respectively corresponds the serial ports respectively for debugging.In the prior art, right In the equipment with multiple subsystems, multiple serial ports are equipped with usually on mainboard, however generally speaking for equipment, due to structure Or the limitation of appearance, it can not be external simultaneously by multiple serial ports.

Can not by multiple serial ports simultaneously it is external in the case where, when individual subsystem needs to be serviced, exist just like Lower two methods: it one is being accessed using telnet mode, the second is opening cabinet, connects corresponding serial ports and is tieed up Shield.But there are following defects for both methods: in method one, if subsystem network interface can not communicate or telnet service default It does not open, then can not access in external sub-system；In method two, opens cabinet and increase the cost of maintenance, and work as When the serial ports of subsystem inside equipment breaks down, cannot reporting which specific serial ports in time, there are failures.

Through retrieving, applying date 2016.01.28, application No. is 201610058904.9 Chinese invention patents to disclose A kind of multiple serial communication system and method based on FPGA, FPGA's per serial ports and a latch one all the way in the invention One is correspondingly connected with；Each read-write storage chip connects at least one latch；Receive the first ground at times using latch Location signal and the first business datum are transmitted between that is, one-to-one latch and serial ports using identical signal wire at times First address signal and the first business datum, can reduce the usage quantity of signal wire.There are following problems for the invention: per all the way Serial ports corresponds to a latch, and structure is complicated；Data are transmitted at times using identical signal wire, it need to be external but reduce Serial ports quantity.

Summary of the invention

The technical problems to be solved in the utility model is to provide a kind of multi-channel serial port managing device based on FPGA, lead to The device is crossed to reduce the external quantity of serial ports, reports serial ports failure in time, reduces maintenance cost.

The utility model is realized in this way: a kind of multi-channel serial port managing device based on FPGA, including a FPGA, outside one Portion's selector, one first serial line interface, a Transistor-Transistor Logic level conversion chip and a CPU group；The Exterior selector and CPU group It is connect with the FPGA；One end of the Transistor-Transistor Logic level conversion chip is connect with first serial line interface, the other end with it is described FPGA connection.

Further, the FPGA connects including one second serial line interface, a third serial line interface group, dial-up value reading Mouth, a decoder and an I2C interface；One end of second serial line interface is connect with the Transistor-Transistor Logic level conversion chip, separately One end is connect with the decoder；One end of the third serial line interface group is connect with the decoder, the other end and the CPU Group connection；The input terminal that the dial-up value reads interface is connect with the Exterior selector, and output end and the CPU group connect； The I2C interface and the CPU group connect.

Further, the decoder is equipped with one first register, one second register and a third register.

Further, the Exterior selector is toggle switch, band switch or microswitch.

Further, first serial line interface is RS232 interface.

Further, the Transistor-Transistor Logic level conversion chip is TTL232 chip.

Further, the CPU group includes a host CPU and a plurality of auxiliary CPU；The host CPU and auxiliary CPU are and institute State FPGA connection.

Utility model has the advantages that

1, the gating that rs 232 serial interface signal is carried out by the Exterior selector, reduces the external quantity of serial ports, so that equipment can To be made more compact portable.

2, by the backstage poll of FPGA, would know that the serial ports of which subsystem, there are failures, and report serial ports in time therefore Barrier.

3, the gating of rs 232 serial interface signal is carried out by the Exterior selector, equipment can be directly connected to accordingly go here and there when generating failure Mouthful carrying out debugging maintenance, subsystem network interface can not communicate or telnet service also adjustable when not opening, it does not need to open cabinet, Reduce maintenance cost.

4, centralized detecting, channel switching are carried out, transmitting information is concentrated and issues configuration by FPGA, avoid serial ports quantity Poll occupies the CPU excessive time one by one when more, effectively reduces cpu resource loss, improves efficiency, and FPGA belongs to hardware language Speech, rate are fast.

5, Exterior selector signal is connected to CPU group by FPGA again, avoids the influence charged and stirred to CPU group.

6, FPGA is inquired by the state to third serial line interface group, is realized in backstage poll subsystem serial ports shape State does not need the intervention of host CPU, has saved resource.

Detailed description of the invention

The utility model is further described in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is a kind of schematic block circuit diagram of the multi-channel serial port managing device based on FPGA of the utility model.

100- serial interface management device, the first serial line interface of 1-FPGA, 2-, 3-TTL electrical level transferring chip, the selection of the outside 4- Device, 5-CPU group, the second serial line interface of 11-, 12- third serial line interface, 13- dial-up value read interface, 14- decoder, 141- the One register, the second register of 142-, 143- third register, 15-I2C interface, 51- host CPU, the auxiliary CPU of 52-.

Specific embodiment

It please refers to shown in Fig. 1, a kind of preferable implementation of the multi-channel serial port managing device 100 based on FPGA of the utility model Example, including a FPGA1, an Exterior selector 4, one first serial line interface 2, a Transistor-Transistor Logic level conversion chip 3 and a CPU group 5； The Exterior selector 4 and CPU group 5 are connect with the FPGA1；One end of the Transistor-Transistor Logic level conversion chip 3 and described the One serial interface 2 connects, and the other end is connect with the FPGA1；The gating of rs 232 serial interface signal is carried out by the Exterior selector 4, Reduce the external quantity of serial ports, equipment is allowed to be made more compact portable, it, can be by the outside when the device space is limited Selector 4 is integrated with the first serial line interface 2；Centralized detecting is carried out by the FPGA1, channel switching, concentrates transmitting Information and issue configuration, avoid serial ports quantity it is more when one by one poll occupy the CPU excessive time, effectively reduce cpu resource and be lost, Efficiency is improved, and the FPGA1 belongs to hardware language, rate is fast.

The FPGA1 include one second serial line interface 11, a third serial line interface group 12, a dial-up value read interface 13, One decoder 14 and an I2C interface 15；One end of second serial line interface 11 is connect with the Transistor-Transistor Logic level conversion chip 3, The other end is connect with the decoder 14；One end of the third serial line interface group 12 is connect with the decoder 14, the other end It is connect with the CPU group 5, the decoder 14 is for gating logic unit；The dial-up value reads the defeated of interface 13 Enter end to connect with the Exterior selector 4, output end is connect with the CPU group 5；The dial-up value reads interface 13 for reading The dial-up value of the Exterior selector 4；The I2C interface 15 is connect with the CPU group 5, is specially connected with the host CPU 51 It connects, control instruction is assigned to FPGA1 for the reception of the host CPU 51 FPGA1 serial ports fault message reported and host CPU 51.

The decoder 14 is equipped with one first register 141, one second register 142 and a third register 143； First register 141 is for storing current serial ports serial number, and second register 142 is for storing background query serial ports sequence Number, the third register 143 is used for storage flag information.

The Exterior selector 4 is toggle switch, band switch or microswitch；4 signal of Exterior selector is logical It crosses FPGA14 and is connected to CPU group 5 again, avoid the influence charged and stirred to the CPU group 5；There is design in toggle switch output end TVS pipe is protected, and prevents spike interference or surge when switching toggle from having an impact to the interface of the FPGA1, so even if Toggle switch is constantly stirred under electrifying condition, can also protect rear class the FPGA1 and and CPU group 5 be not damaged；It is described outer Portion's selector 4 only needs n section that can access 2ⁿA internal serial ports (n is positive integer) is every to increase an internal serial ports routing Demand, marginal cost are low.

First serial line interface 2 is RS232 interface.

The Transistor-Transistor Logic level conversion chip 3 is TTL232 chip, and the signal for transmitting RS232 interface is converted to Transistor-Transistor Logic level signal.

The CPU group 5 includes a host CPU 51 and a plurality of auxiliary CPU52；The host CPU 51 and auxiliary CPU52 are and institute FPGA1 connection is stated, the host CPU 51 uses the MT7621A of MediaTek.

Utility model works principle:

Serial equipment connects first serial line interface 2；Serial ports by toggle switch setting gating is to connect the master The serial ports of CPU51, the dial-up value reads interface 13 and carries out Key dithering to the signal of toggle switch, and dial-up value signal is transmitted To the decoder 14, decoder 14 gates the serial ports of host CPU 51；

The level signal that first serial line interface 2 inputs is converted to TTL level signal by the Transistor-Transistor Logic level conversion chip 3 Afterwards, the FPGA14 is inputted from second serial line interface 11, Transistor-Transistor Logic level signal is serial by the decoder 14 and third Interface group 12 is communicated with the host CPU 51.

In conclusion utility model has the advantages that

Although those familiar with the art answers the foregoing describe specific embodiment of the present utility model Working as understanding, we are merely exemplary described specific embodiment, rather than for the limit to the scope of the utility model Fixed, those skilled in the art modification and variation equivalent made by the spirit according to the utility model all should Cover in the scope of the claimed protection of the utility model.

Claims

1. a kind of multi-channel serial port managing device based on FPGA, it is characterised in that: including a FPGA, an Exterior selector, one One serial interface, a Transistor-Transistor Logic level conversion chip and a CPU group；The Exterior selector and CPU group connect with the FPGA It connects；One end of the Transistor-Transistor Logic level conversion chip is connect with first serial line interface, and the other end is connect with the FPGA.

2. a kind of multi-channel serial port managing device based on FPGA as described in claim 1, it is characterised in that: the FPGA includes One second serial line interface, a third serial line interface group, a dial-up value read interface, a decoder and an I2C interface；Described One end of two serial line interfaces is connect with the Transistor-Transistor Logic level conversion chip, and the other end is connect with the decoder；The third is serial One end of interface group is connect with the decoder, and the other end and the CPU group connect；The dial-up value reads the input terminal of interface It is connect with the Exterior selector, output end and the CPU group connect；The I2C interface and the CPU group connect.

3. a kind of multi-channel serial port managing device based on FPGA as claimed in claim 2, it is characterised in that: on the decoder Equipped with one first register, one second register and a third register.

4. a kind of multi-channel serial port managing device based on FPGA as described in claim 1, it is characterised in that: the external selection Device is toggle switch, band switch or microswitch.

5. a kind of multi-channel serial port managing device based on FPGA as described in claim 1, it is characterised in that: described first is serial Interface is RS232 interface.

6. a kind of multi-channel serial port managing device based on FPGA as described in claim 1, it is characterised in that: the Transistor-Transistor Logic level Conversion chip is TTL232 chip.

7. a kind of multi-channel serial port managing device based on FPGA as described in claim 1, it is characterised in that: the CPU group packet Include a host CPU and a plurality of auxiliary CPU；The host CPU and auxiliary CPU are connect with the FPGA.