CN114706799B - Low-delay monitoring device and method for 256×256 switching matrix - Google Patents
Low-delay monitoring device and method for 256×256 switching matrix Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
- H04B7/18517—Transmission equipment in earth stations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/02—Constructional details
- H04Q1/028—Subscriber network interface devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/20—Testing circuits or apparatus; Circuits or apparatus for detecting, indicating, or signalling faults or troubles
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/18—Electrical details
- H04Q1/28—Current-supply circuits or arrangements for selection equipment at exchanges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0004—Parallel ports, e.g. centronics
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Abstract
The invention discloses a low-delay monitoring device of 256×256 switching matrix, comprising: the device comprises a monitoring end CPU, an input level conversion circuit, a chip selection enabling judging circuit and an output level conversion circuit, wherein the output end of the input level conversion circuit is connected with the monitoring input end of the monitoring end CPU; the chip selection enabling judging circuit is respectively connected with the input level converting circuit and the output level converting circuit, and the output end of the output level converting circuit is connected with the control input end on the CPU of the monitored end. The low-delay monitoring device greatly reduces the monitoring delay of the switching matrix.
Description
Technical Field
The invention relates to the technical field of electronic information, in particular to a low-delay monitoring device and method for 256×256 switching matrices.
Background
In satellite communications, a switching matrix is a critical device for processing signal distribution and forwarding during terrestrial transmission. The system can route different signals from different cables to one or more devices for processing or testing and other operations, so that automation of signal routing is improved, and efficiency in a signal transmission process is improved.
Typically, satellite signals are transmitted from space to earth between satellites and ground station antennas at different frequencies and polarizations. The satellite signals are received by the antenna, separated, and fed to a low noise down converter, which typically changes to the L-band or extends the L-band. The converted signal is then transmitted to an integrated receiver decoder, which decodes the signal to baseband, and the transmission process can be usually carried out by using a coaxial cable, and the transmission process is usually carried out by combining with an amplifier to compensate transmission loss or carrying out radio frequency optical fiber conversion and then carrying out optical fiber transmission.
In order to distribute, decode, multiplex, transmit and exchange RF signals over optical fibers between different devices, different approaches may be employed. The classical approach is "hard-wired", i.e. the incoming RF signal is fed directly through a cable to the opto-electric converter on the splitter. Because the splitting reduces signal power, integrated amplifiers are often incorporated; yet another way is to use a "switching matrix", which is obviously more flexible, switching the input source to any number of outputs and vice versa. In the switching matrix, the more input and output interfaces are, the more complicated the monitoring link is, and the monitoring response speed often determines the switching time delay of the switching matrix, and the lower the time delay is, the higher the real-time performance is. In the conventional exchange matrix, the monitoring mode is usually serial communication such as RS232, RS485, I, C or SPI, and the like, and the communication mode is widely used in a small-scale control system due to simple interfaces, but the defects are also obvious. The serial communication needs to transmit the receiving and transmitting instruction bit by bit at the agreed speed of both sides, the communication time delay is influenced by the instruction length, the IC running speed and the CPU processing speed, when facing to a large-scale exchange matrix, the time delay is amplified, the working efficiency of the system is lowered, and the use experience is reduced.
As shown in fig. 1, the monitoring link in the conventional switching matrix is generally composed of a "monitoring terminal cpu+a monitoring terminal communication IC" and a "monitored terminal cpu+a monitored terminal communication IC", the signal transmission is accompanied by the processing of the command by the CPU and the switching of the transceiving modes of the communication IC, when the switching scale of the switching matrix is small, the effect caused by the delay is small, the real-time performance is high, for example, a 4×8 switching matrix is shared by 32 port switching combinations, the full-load round-robin switching time is "32× (CPU command processing delay+cpu command transmission baud rate×byte+communication IC enabling time+communication IC command transmission delay)", the signal transmission speed in the metal carrier is approximately equal to the speed of light, the delay is ignored, the CPU takes a 128MHz high-speed clock, the transmission baud rate is according to the conventional value 115200, the byte number is 8, the communication IC enabling time is approximately 7 μs, the communication IC command transmission delay is approximately 0.5 μs, and the full-load round-robin switching time of 4×8 switching matrix is approximately 18ms; the 256×256 switching matrices have 65536 port switching combinations, and the full-load round-robin switching time is about 36.9s after conversion according to the switching time of the 4×8 switching matrices, which seriously affects the working efficiency and the use experience of the system.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a low-delay monitoring device and a low-delay monitoring method for 256×256 switching matrices, which greatly reduce the monitoring delay of the switching matrices, improve the working efficiency of the system and optimize the monitoring instantaneity of the switching matrices.
In order to achieve the technical purpose, the invention adopts the following technical scheme: a low-latency monitoring device for a 256 x 256 switching matrix, the 256 x 256 switching matrix low-latency monitoring device comprising: the device comprises a monitoring end CPU, an input level conversion circuit, a chip selection enabling judgment circuit and an output level conversion circuit, wherein the output end of the input level conversion circuit is connected with the monitoring input end of the monitoring end CPU; the chip selection enabling judging circuit is respectively connected with the input level converting circuit and the output level converting circuit.
Further, the 256×256 switch matrix low-delay monitoring device is connected with a 256×256 switch matrix, and the 256×256 switch matrix low-delay monitoring device are connected with a programmable power supply.
Further, the 256×256 switching matrix is provided with a monitored terminal CPU, and the monitored terminal CPU is provided with a monitoring output terminal, a chip selection input terminal and a control input terminal.
Further, the monitoring output end on the monitored end CPU is connected with the input end of the input level conversion circuit, and the input level conversion circuit coordinates the level of the monitoring output end on the monitored end CPU and the circuit of the monitoring input end of the monitored end CPU into the same level through the gate combination circuit.
Further, the input end and the output end of the input level conversion circuit, the monitoring output end on the monitored end CPU and the monitoring input end of the monitoring end CPU are all 16-bit IO parallel ports.
Further, the chip selection input end on the monitored end CPU is connected with the output end of the chip selection enabling judging circuit, and the chip selection enabling judging circuit converts the level of the chip selection output end of the monitored end CPU into the level of the same level as the level of the chip selection input end on the monitored end CPU.
Further, the input end and the output end of the chip selection enabling judging circuit, the chip selection input end on the monitored end CPU and the chip selection output end of the monitored end CPU are all 10-bit IO parallel ports.
Further, the control input end of the monitored end CPU is connected with the output end of the output level conversion circuit, and the output level conversion circuit coordinates the level of the control output end of the monitored end CPU and the level of the control input end of the monitored end CPU into the same level through the AND gate combination circuit.
Further, the output end and the input end of the output level conversion circuit, the control input end on the monitored end CPU and the control output end of the monitored end CPU are all 16-bit IO parallel ports.
The invention also provides a monitoring method of the low-delay monitoring device of the 256×256 switching matrix, which comprises the following steps:
(1) A chip selection output end of the CPU of the monitoring end sends out a chip selection signal;
(2) The chip selection input end of the CPU at the monitored end receives the chip selection signal and judges whether the chip selection signal is valid or not through an exclusive OR gate and AND gate combined circuit, and when the signal is valid, a high-level chip selection enabling passing signal is output to a chip selection enabling judging circuit to indicate the chip selection enabling judgment;
(3) After the chip selection enabling judgment is passed, the input level conversion circuit and the output level conversion circuit both start level data monitoring;
(4) When the level data monitoring is completed, the chip selection output end of the monitoring end CPU outputs a low level monitoring completion indication signal, and the enabling signal of the chip selection enabling judging circuit is turned off.
Compared with the prior art, the invention has the following beneficial effects: the invention omits serial communication IC and peripheral circuit, replaces the 256X 256 exchange matrix low-delay monitoring device by self-developed and concurrent 256X 256 exchange matrix low-delay monitoring device, changes the monitoring terminal CPU+monitoring terminal communication IC and monitored terminal CPU+monitored terminal communication IC in the traditional monitoring flow into monitoring terminal CPU+monitored terminal CPU, and the actions of level conversion, chip selection, control, monitoring and the like between the two terminals are completed by the IO parallel port; in the low-delay monitoring device of the 256×256 switching matrix, the monitoring input end of the monitoring end CPU adopts 16-path concurrent monitoring, so that the full-load round-robin switching time is shortened from 36.9s to 528ms, the monitoring delay is greatly reduced, the working efficiency of the 256×256 switching matrix system is improved, and the monitoring instantaneity of the switching matrix is optimized.
Drawings
FIG. 1 is a schematic diagram of a monitoring method of a conventional switching matrix;
FIG. 2 is a schematic diagram of a low latency monitoring device of a 256×256 switching matrix according to the present invention;
Fig. 3 is a schematic diagram of a low latency monitoring device of 256×256 switching matrix according to the present invention.
Detailed Description
The technical scheme of the invention is further explained below with reference to the accompanying drawings.
Fig. 2 is a schematic diagram of a low-delay monitoring device of a 256×256 switch matrix according to the present invention, wherein the 256×256 switch matrix low-delay monitoring device is connected with the 256×256 switch matrix, the 256×256 switch matrix adopts the same monitoring interface as the 256×256 switch matrix low-delay monitoring device, and all channel/board monitoring circuits adopt a parallel Pin-to-Pin mode; the 256×256 switch matrix and the 256×256 switch matrix low-delay monitoring device are connected with a programmable power supply, and the programmable power supply is used for supplying power to the 256×256 switch matrix low-delay monitoring device and the 256×256 switch matrix. The low-delay monitoring device of the 256×256 switching matrix shortens the full-load round-robin switching time from 36.9s to 528ms, greatly reduces the monitoring delay, improves the working efficiency of the 256×256 switching matrix system, and optimizes the monitoring instantaneity of the switching matrix.
The 256×256 switching matrix low-delay monitoring device of the invention is designed to integrate monitoring and control, and the external interface is a 2.54mm×50 flat cable socket. The 256×256 switching matrix low-delay monitoring device includes: the core circuit of the monitoring terminal CPU is a DSP high-speed signal processing circuit and is responsible for sending chip selection signals, outputting control levels and inputting monitoring state values, so that the state of the switch matrix is updated in time; the concurrency monitoring circuit is composed of a monitoring input end of a monitoring end CPU, a chip selection output end and a control output end, wherein the chip selection output end is used for distinguishing switching channel/board card address information of a 256×256 switching matrix by chip selection signals, the control output end is used for time-sharing multiplexing to realize concurrency control of all channel/board card states, and the monitoring input end is used for time-sharing multiplexing to realize concurrency monitoring of all channel/board card states. The output end of the input level conversion circuit is connected with the monitoring input end of the monitoring end CPU, the input end of the chip selection enabling judging circuit is connected with the chip selection output end of the monitoring end CPU, and the input end of the output level conversion circuit is connected with the control output end of the monitoring end CPU; the chip selection enabling judging circuit is respectively connected with the input level converting circuit and the output level converting circuit.
In the invention, the 256×256 switching matrix adopts the same monitoring interface as the 256×256 switching matrix low-delay monitoring device, and all the channel/board card monitoring circuits adopt a parallel Pin-to-Pin mode, so that the 256×256 switching matrix is provided with a monitored terminal CPU, and the monitored terminal CPU is provided with a monitoring output terminal, a chip selection input terminal and a control input terminal.
In the invention, the input end of the input level conversion circuit is connected with the monitoring output end on the monitored end CPU, and the input level conversion circuit coordinates the level of the monitoring output end on the monitored end CPU and the circuit of the monitoring input end of the monitored end CPU into the same level through the gate combination circuit; the input end and the output end of the input level conversion circuit, the monitoring output end on the monitored end CPU and the monitoring input end of the monitoring end CPU are all 16-bit IO parallel ports, so that 16 port states can be read at the same time at a time and expansion is supported. Because the monitored end CPU has different performance and power consumption from the monitored end CPU, the driving capability of the chip IO is different from the control level, so that an input level conversion circuit is required to coordinate the level of the monitored output end and the level of the monitored input end into the same level through an AND gate combination circuit, thereby protecting the bilateral IO and increasing the IO driving capability of the output end; it should be noted that the functional on of the input level shifter circuit has a precondition, i.e., a chip select enable determination pass.
The output end of the output level conversion circuit is connected with the control input end on the CPU of the monitored end, and the output level conversion circuit coordinates the level of the control output end of the CPU of the monitored end and the level of the control input end on the CPU of the monitored end into the same level through the AND gate combination circuit; the output end and the input end of the output level conversion circuit, the control input end on the monitored end CPU and the control output end of the monitoring end CPU are all 16-bit IO parallel ports, and 16 ports can be controlled simultaneously at a time and expansion is supported. Because the monitored end CPU and the monitored end CPU have different performances and power consumption, the driving capability of the chip IO is different from the control level, so that the output level conversion circuit is required to coordinate the control output level and the control input level into the same level through the AND gate combination circuit, the bilateral IO is protected, the IO driving capability of the output end IO is increased, and the fact that the function of the output level conversion circuit is started and has a precondition, namely the chip selection enabling judgment is passed.
The output end of the chip selection enabling judging circuit is connected with the chip selection input end on the CPU of the monitored end, and the chip selection enabling judging circuit converts the level of the chip selection output end of the CPU of the monitored end into the level of the same level as the level of the chip selection input end on the CPU of the monitored end, so that the driving capability of the chip selection output end is improved while the bilateral IO is protected. The chip selection enabling judging circuit has 10 bit IO parallel port in the input end and the output end, the chip selection input end on the CPU of the monitored end and the chip selection output end of the CPU of the monitored end, and the 256X 256 exchange matrix consists of 16X 16 boards, so that 2-8 input addresses are completed in total through the IO parallel port, and the other 2 bits are the chip selection enabling through bit of the monitored end and the monitoring end data monitoring completion indicating bit. When the chip selection output end gives a chip selection signal, the chip selection input end judges whether the chip selection signal is valid or not through an exclusive OR gate and AND gate combined circuit, and when the signal is valid, the chip selection output end outputs a high level to indicate that the chip selection is successful, and at the moment, the chip selection enabling judgment passes, so that the input level conversion circuit and the output level conversion circuit start working.
The monitoring method of the low-delay monitoring device of the 256×256 switching matrix comprises the following steps:
(1) A chip selection output end of the CPU of the monitoring end sends out a chip selection signal;
(2) The chip selection input end of the CPU at the monitored end receives the chip selection signal and judges whether the chip selection signal is valid or not through an exclusive OR gate and AND gate combined circuit, and when the signal is valid, a high-level chip selection enabling passing signal is output to a chip selection enabling judging circuit to indicate the chip selection enabling judgment;
(3) After the chip selection enabling judgment is passed, the input level conversion circuit and the output level conversion circuit both start level data monitoring;
(4) When the level data monitoring is completed, the chip selection output end of the monitoring end CPU outputs a low level monitoring completion indication signal, and the enabling signal of the chip selection enabling judging circuit is turned off.
As shown in fig. 3, the monitoring flow of the low-delay monitoring device of the 256×256 switching matrix of the present invention is "monitoring terminal cpu+monitored terminal CPU", the actions of level conversion, chip selection, control and monitoring between two terminals are completed by the IO parallel port, and the adjustment for increasing or decreasing the IO parallel port and the circuit scale is made according to the difference of the switching scales of the switching matrix, which has good different scale easy adjustment and adaptability in the product types of the switching matrix. The monitoring input end of the CPU at the monitoring end in the low-delay monitoring device of the 256×256 switching matrix shortens the full-load round-robin switching time from 36.9s to 528ms, greatly reduces the monitoring delay, improves the working efficiency of the 256×256 switching matrix system, and optimizes the monitoring instantaneity of the switching matrix.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.
Claims (6)
1. A 256 x 256 switch matrix low latency monitoring device, the 256 x 256 switch matrix low latency monitoring device comprising: the device comprises a monitoring end CPU, an input level conversion circuit, a chip selection enabling judgment circuit and an output level conversion circuit, wherein the output end of the input level conversion circuit is connected with the monitoring input end of the monitoring end CPU; the chip selection enabling judging circuit is respectively connected with the input level converting circuit and the output level converting circuit;
The 256×256 switching matrix is provided with a monitored terminal CPU, and the monitored terminal CPU is provided with a monitoring output terminal, a chip selection input terminal and a control input terminal;
The monitoring output end on the monitored end CPU is connected with the input end of the input level conversion circuit, and the input level conversion circuit coordinates the level of the monitoring output end on the monitored end CPU and the circuit of the monitoring input end of the monitored end CPU into the same level through the gate combination circuit;
the chip selection input end of the monitored end CPU is connected with the output end of the chip selection enabling judging circuit, and the chip selection enabling judging circuit converts the level of the chip selection output end of the monitored end CPU into the level of the same level as the level of the chip selection input end of the monitored end CPU;
The control input end of the monitored end CPU is connected with the output end of the output level conversion circuit, and the output level conversion circuit coordinates the level of the control output end of the monitored end CPU and the level of the control input end of the monitored end CPU into the same level through the AND gate combination circuit.
2. The low-latency monitoring device for 256×256 switch matrix according to claim 1, wherein the 256×256 switch matrix low-latency monitoring device is connected to a 256×256 switch matrix, and the 256×256 switch matrix low-latency monitoring device are connected to a programmable power supply.
3. The low-delay monitoring device of 256×256 switch matrix according to claim 1, wherein the input end and the output end of the input level conversion circuit, the monitoring output end on the monitored end CPU, and the monitoring input end of the monitoring end CPU are all 16-bit IO parallel ports.
4. The low-latency monitoring device of 256×256 switch matrix according to claim 1, wherein the chip select enable judging circuit has an input end and an output end, and the chip select input end on the monitored CPU and the chip select output end of the monitored CPU are all 10 bit IO parallel ports.
5. The low-delay monitoring device of 256×256 switch matrix according to claim 4, wherein the output end and the input end of the output level conversion circuit, the control input end on the monitored end CPU, and the control output end of the monitoring end CPU are all 16-bit IO parallel ports.
6. A method of monitoring a low latency monitoring device of a 256 x 256 switching matrix according to any of claims 1-5, comprising the steps of:
(1) A chip selection output end of the CPU of the monitoring end sends out a chip selection signal;
(2) The chip selection input end of the CPU at the monitored end receives the chip selection signal and judges whether the chip selection signal is valid or not through an exclusive OR gate and AND gate combined circuit, and when the signal is valid, a high-level chip selection enabling passing signal is output to a chip selection enabling judging circuit to indicate the chip selection enabling judgment;
(3) After the chip selection enabling judgment is passed, the input level conversion circuit and the output level conversion circuit both start level data monitoring;
(4) When the level data monitoring is completed, the chip selection output end of the monitoring end CPU outputs a low level monitoring completion indication signal, and the enabling signal of the chip selection enabling judging circuit is turned off.
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