CN202332303U - Structure of multichannel real-time direct-reading memory - Google Patents
Structure of multichannel real-time direct-reading memory Download PDFInfo
- Publication number
- CN202332303U CN202332303U CN2011204953889U CN201120495388U CN202332303U CN 202332303 U CN202332303 U CN 202332303U CN 2011204953889 U CN2011204953889 U CN 2011204953889U CN 201120495388 U CN201120495388 U CN 201120495388U CN 202332303 U CN202332303 U CN 202332303U
- Authority
- CN
- China
- Prior art keywords
- passage
- channel
- data
- state machine
- storer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
- 230000003139 buffering effect Effects 0.000 claims abstract description 3
- 238000010276 construction Methods 0.000 claims description 11
- 241001522296 Erithacus rubecula Species 0.000 abstract 1
- 239000002699 waste material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Images
Landscapes
- Time-Division Multiplex Systems (AREA)
- Multi Processors (AREA)
Abstract
The utility model discloses a structure of a multichannel real-time direct-reading memory, comprising a memory, a time division multiplex controller, and a plurality of channel controllers, wherein the memory consists of a first channel memory and a difference register group; the time division multiplex controller is connected with the memory and comprises a state machine and a group of buffer data registers; each channel controller comprises a first channel and is connected with the time division multiplex controller; the state machine controls the channels for round robin; the buffer data registers are used for buffering data of the channels; a first memory is sued for storing complete storage data of a first channel; and the difference register group is used for storing the storage data of the other channels of the channels, except the first channel, which is different from the storage data of the first channel. With the adoption of the technical scheme of the multichannel real-time direct-reading memory provided by the utility model, the resource waste of a storage space, caused by repeatedly storing the same data by the memory, is prevented. The efficiency of an integrated circuit is improved by memory access of the channels in the different time slices.
Description
Technical field
The utility model belongs to technical field of integrated circuits, particularly a kind of Multi-channel Real-time direct-reading memory construction.
Background technology
The HDMI technology is high with its transmission quality, characteristics such as control is convenient, copyright protection, the revolution that has brought video transmission technologies.The HDMI interface develops into the switching of the multiport of today also by single link.In multi-source HDMI switch data, after source end equipment inserts, obtain EDID information through the DDC passage, system for each DDC channel arrangement a storer be used to preset the EDID data.For one of each DDC channel arrangement has preset the storer of EDID information, solved effectively obtaining of EDID data between the multi-source HDMI interface.
Usually have HDMI multi-source input at one, a terminal shows in the system of output, the storage of EDID data and obtain common employing such as the design of Fig. 1, Fig. 2.
Among Fig. 1, system has been each HDMI channel arrangement EDID ROM.When having N passage in the system, need N EDID ROM of corresponding configuration, be used to store EDID information.This scheme has solved Multi-channel Real-time and has obtained the EDID data, but the existence of a plurality of EDID ROM resolution elements, has increased the Master Cost of business men.
Among Fig. 2, chip is integrated EDID storer adopts multiplexer (MUX control hyperchannel visit EDID storer, obtains EDID information.There are a plurality of selector switchs in the multiplexer (MUX, when having N passage, corresponding have a N selector switch.Selector switch is used to select the EDID data.This solution integration the EDID storer, solved a large amount of resolution elements and existed the material that brings to increase, but multiplexer channel visit EDID storer, the selector switch of employing has taken a large amount of resource of chip, has reduced integrated circuit efficient.
The utility model content
The purpose of the utility model provides a kind of Multi-channel Real-time direct-reading memory construction, and is comparatively complicated with Multi-channel Real-time direct-reading memory construction in the solution prior art, takies the problem of excess resource.
The technical scheme of the utility model is, a kind of Multi-channel Real-time direct-reading memory construction, and this structure comprises:
Storer, this storer is made up of first passage storer and difference registers group;
The time-sharing multiplex controller that is connected with storer, this time-sharing multiplex controller comprises a state machine and pool of buffer data register;
The a plurality of channel controllers that comprise first passage that are connected with the time-sharing multiplex controller; Wherein, Said each passage of state machine control is with round-robin; Said buffered data register is used for the data buffering to each passage, and said first memory is used to store the complete storage data of first passage, and said difference registers group is used for storing other passage of a plurality of passages of eliminating first passage and the storage data of first passage difference.
Preferably, described channel controller comprises and changes string module and data exchange control signal maker.
Preferably, the state number M of said state machine satisfies the M=N+1 relation by passage number N decision,
The state of state machine be defined as respectively successively first passage state, second channel state ..., N channel status and one finishes waiting status,
When state machine detected any one channel access storer, state machine began to get into the first passage state, along with the wheel commentaries on classics of timeslice; Finish waiting status up to getting into last; State machine will stop at this state this moment, and whether after this state machine will detect always has the channel access storer, if having; State machine gets into the first passage state, with this running repeatedly.
Further; Described passage is the DDC passage of HDMI interface standard, and storer is used to store the EDID data of each passage, and N group EDID data are stored in same storer and the difference registers group; The difference registers group is the individual byte capacities of 3 (N-1); Be used to store DDC passage and the storage area of first passage variance data except that first passage, here, N is the non-zero integer.
The technical scheme of the Multi-channel Real-time DASD of the utility model; Implementation method is when several groups of data same sections account for one group of partial data significant proportion; Employing is stored one group of partial data respectively and is organized data data of difference with it with other, and each passage is through time-sharing multiplex reference-to storage resource.Adopt the Multi-channel Real-time DASD technical scheme of above-mentioned proposition, avoided storer repeated storage identical data to cause the wasting of resources of storage space; Adopt the method for time-sharing multiplex, each passage reference-to storage in different time slices, shared resource has improved the efficient of integrated circuit, has reduced power consumption.
Description of drawings
A kind of Multi-channel Real-time direct-reading memory construction figure in Fig. 1 prior art
Another kind of Multi-channel Real-time direct-reading memory construction figure in Fig. 2 prior art
The system chart of Multi-channel Real-time direct-reading storer among Fig. 3 the utility model embodiment
Channel controller structural drawing among Fig. 4 the utility model embodiment
Time-sharing multiplex state machine controller structural drawing among Fig. 5 the utility model embodiment
The process flow diagram of Multi-channel Real-time direct-reading memory approaches among Fig. 6 the utility model embodiment
Embodiment
Further specify the embodiment of the utility model below in conjunction with accompanying drawing, embodiment adopts 4 passages.
Like Fig. 3, the system chart of Multi-channel Real-time DASD comprises: storer, 4 interface channel controllers and time-sharing multiplex state machine controller.
Storer: be used to store the data of each passage, comprise passage 1 storer and difference registers group.Passage 1 storer is the storage area that is used for memory channel 1 partial data; The difference registers group is the storage area that is used to store other passage and passage 1 variance data.
4 interface channel controllers: they adopt identical structure, are used to connect Peripheral Interface and storer, share with the identical round-robin of size and use storer.Parallel 8 bit data are during from memory transfer to passage, and data will be by serialization, with the transmission speed of coupling external unit.
Time-sharing multiplex state machine controller: comprise a group state machine and one group of 4 buffered data register that are used for 4 passages of buffer memory that each channel time sheet wheel of control changes.The passage number is 4, so the state number of state machine is 5, is defined as passage 1 successively, passage 2, and passage 3, passage 4 finishes waiting status.
4 above-mentioned interface channel controllers adopt identical structure, and like Fig. 4, its channel controller comprises and changes string module and data exchange control signal maker.The data exchange control signal maker produces control signal, and control channel is obtained valid data, controls simultaneously and changes the string module, realizes that data are from parallel-to-serial conversion.
Above-mentioned time-sharing multiplex state machine controller, constitutional diagram such as Fig. 5, state machine reset signal generative circuit produces the commencing signal machine that gets the hang of among the figure, and state machine system is given tacit consent at passage 1 state.When the commencing signal arrival, system implements passage 4 states from the commentaries on classics of passage 1 status wheel, arrives at last and finishes waiting status.State machine will rest on the end waiting status always, begin the arrival of reset signal to wait for next time.
During the hyperchannel reference-to storage, two kinds of situation are arranged: have only a passage to read storer at the same time; Have at the same time greater than 2 passages and read storer.State machine is provided with buffer register and writes enable signal in any channel status, in the channel status implementation, judge that successively buffer register writes enable signal; If effectively; Then begin compare address, from storer, obtain valid data, upgrade buffer register then; If invalid, buffer register will not be updated.
Design cycle such as Fig. 6 of above-mentioned Multi-channel Real-time DASD, among the figure behind the system power-on reset:
The first step: the state machine controller of time-sharing multiplex begins detection and has or not the channel access storer, if having, generates state machine reset signal admission passage 1 state; If do not have, then the time-sharing multiplex storage operation finishes.
Second step: when state machine generation reset signal admission passage 1 state, system's sense channel 1 state buffer register is write enable signal EN1, if effectively, match address obtains active data from storer, thereby upgrades the data in the buffer register 1; If invalid, then do not upgrade buffer register 1.Jump to passage 2 states, carry out passage 1 state identical operations successively; Up to implementing passage 4 states, get at last and finish waiting status.
The 3rd step: in the process of carrying out, system will detect each channel access memory signals always, if having; System will be through state machine reset signal maker; Produce the state machine reset signal, system's machine controller passage 1 state that gets the hang of is carried out the operation of second step successively.
For the HDMI interface, following embodiment can be arranged.Embodiment adopts 4 HDMI interfaces, promptly has 4 DDC access paths.The system of HDMI Multi-channel Real-time direct-reading storer comprises: storer, 4 DDC channel controllers and time-sharing multiplex state machine controller.
Storer: be used to store the EDID data of each passage, comprise passage 1 storer and difference registers group.Passage 1 storer is the storage area that is used for memory channel 1 complete EDID data; The difference registers group is the storage area that is used to store other DDC passage and passage 1 variance data, and relatively there are the variance data of 3 bytes in each DDC passage and passage 1, promptly has the difference registers group of 9 bytes.
4 DDC channel controllers: they adopt identical structure, are used to connect Peripheral Interface and storer, share with the identical round-robin of size and use storer.Parallel 8 bit data are during from memory transfer to the DDC passage, and data will be by serialization, with the transmission speed of coupling external unit.
Time-sharing multiplex state machine controller: comprise a group state machine and one group of 4 buffered data register that are used for 4 DDC passages of buffer memory that each DDC channel time sheet wheel of control changes.DDC passage number is 4, so the state number of state machine is 5, is defined as passage 1 successively, passage 2, and passage 3, passage 4 finishes waiting status.
4 above-mentioned DDC channel controllers adopt identical structure, and like Fig. 4, its channel controller comprises and changes string module and data exchange control signal maker.The data exchange control signal maker produces control signal, and control channel is obtained valid data, controls simultaneously and changes the string module, realizes that data are from parallel-to-serial conversion.
Directly visit the EDID storer in real time for the multichannel DDC passage that makes HDMI, improve integrated circuit efficient, adopt time-sharing multiplex state machine control multichannel DDC channel access EDID storer.In the design of HDMI multi-source interface chip, there is the difference of 3 bytes in each passage EDID data, and the EDID data storage can adopt and store one group of partial data and all the other group data method of variance data with it respectively in the design, reduces chip area.N group EDID data are stored in the individual difference registers group of same storer and 3 (N-1).
Claims (4)
1. Multi-channel Real-time direct-reading memory construction is characterized in that this structure comprises:
Storer, this storer is made up of first passage storer and difference registers group;
The time-sharing multiplex controller that is connected with storer, this time-sharing multiplex controller comprises a state machine and pool of buffer data register;
The a plurality of channel controllers that comprise first passage that are connected with the time-sharing multiplex controller; Wherein, Said each passage of state machine control is with round-robin; Said buffered data register is used for the data buffering to each passage, and said first memory is used to store the complete storage data of first passage, and said difference registers group is used to store passage and the storage data of first passage difference except that first passage.
2. Multi-channel Real-time direct-reading memory construction as claimed in claim 1 is characterized in that, described channel controller comprises and changes string module and data exchange control signal maker.
3. Multi-channel Real-time direct-reading memory construction as claimed in claim 1 is characterized in that, the state number M of said state machine satisfies the M=N+1 relation by passage number N decision,
The state of state machine be defined as respectively successively first passage state, second channel state ..., N channel status and one finishes waiting status,
When state machine detected any one channel access storer, state machine began to get into the first passage state, along with the wheel commentaries on classics of timeslice; Finish waiting status up to getting into last; State machine will stop at this state this moment, and whether after this state machine will detect always has the channel access storer, if having; State machine gets into the first passage state, with this running repeatedly.
4. Multi-channel Real-time direct-reading memory construction as claimed in claim 1 is characterized in that, described passage is the DDC passage of HDMI interface standard; Storer is used to store the EDID data of each passage; N group EDID data are stored in same storer and the difference registers group, and the difference registers group is the individual byte capacities of 3 (N-1), are used to store DDC passage and the storage area of first passage variance data except that first passage; Here, N is the non-zero integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204953889U CN202332303U (en) | 2011-12-02 | 2011-12-02 | Structure of multichannel real-time direct-reading memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204953889U CN202332303U (en) | 2011-12-02 | 2011-12-02 | Structure of multichannel real-time direct-reading memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202332303U true CN202332303U (en) | 2012-07-11 |
Family
ID=46444275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204953889U Withdrawn - After Issue CN202332303U (en) | 2011-12-02 | 2011-12-02 | Structure of multichannel real-time direct-reading memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202332303U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521180A (en) * | 2011-12-02 | 2012-06-27 | 百利通科技（扬州）有限公司 | Multi-channel real-time direct reading memory structure |
| CN111343106A (en) * | 2020-02-25 | 2020-06-26 | 母国标 | Multi-channel intermediate frequency digital signal processing device and method |
-
2011
- 2011-12-02 CN CN2011204953889U patent/CN202332303U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521180A (en) * | 2011-12-02 | 2012-06-27 | 百利通科技（扬州）有限公司 | Multi-channel real-time direct reading memory structure |
| CN102521180B (en) * | 2011-12-02 | 2014-10-22 | 百利通科技（扬州）有限公司 | Multi-channel real-time direct reading memory structure |
| CN111343106A (en) * | 2020-02-25 | 2020-06-26 | 母国标 | Multi-channel intermediate frequency digital signal processing device and method |
| CN111343106B (en) * | 2020-02-25 | 2023-03-24 | 母国标 | Multi-channel intermediate frequency digital signal processing device and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109271335B (en) | FPGA implementation method for DDR cache of multi-channel data source | |
| KR101611516B1 (en) | Method and system for improving serial port memory communication latency and reliability | |
| CN100498806C (en) | Device and method for outputting signal of emulation infrared detector | |
| CN103297055A (en) | Device for achieving multipath serial ADC synchronization by adopting FPGA | |
| CN104915303B (en) | High speed digital I based on PXIe buses/O systems | |
| CN104317770B (en) | Data store organisation for many-core processing system and data access method | |
| CN103593306A (en) | Design method for Cache control unit of protocol processor | |
| CN109656851B (en) | System with time determination and comprising multiple high-speed bus channels and shared interface | |
| CN104915213B (en) | A kind of Partial Reconstruction controller of reconfigurable system | |
| CN104298628A (en) | Data storage device arbitration circuit and method for concurrent access | |
| CN101625635A (en) | Method, system and equipment for processing circular task | |
| CN107391422A (en) | multi-path asynchronous serial communication data access system and method | |
| CN104765701A (en) | Data access method and device | |
| CN102521180B (en) | Multi-channel real-time direct reading memory structure | |
| CN202332303U (en) | Structure of multichannel real-time direct-reading memory | |
| CN106372029A (en) | Point-to-point on-chip communication module based on interruption | |
| CN103455367B (en) | Management unit and method for implementing multi-task scheduling in reconfigurable systems | |
| CN102404183B (en) | Arbitration method and arbitration device | |
| CN104636151A (en) | FPGA chip configuration structure and configuration method based on application memorizers | |
| CN106569968A (en) | Inter-array data transmission structure and scheduling method used for reconfigurable processor | |
| CN111831209B (en) | Data access device and system | |
| CN105630400A (en) | High-speed massive data storage system | |
| CN115328832A (en) | Data scheduling system and method based on PCIE DMA | |
| CN102890664A (en) | Capacity expansion data acquisition board and data storage method | |
| CN202871257U (en) | A DMA-based GPIO module capable of flashing LED displays |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120711 Effective date of abandoning: 20141022 |
|
| RGAV | Abandon patent right to avoid regrant |