CN102541133A - Voltage reference source capable of compensation in full temperature range - Google Patents

Abstract

The invention discloses a voltage reference source for full temperature range compensation, which specifically includes a start-up circuit, a first-order temperature compensation circuit, a proportional superposition output circuit and a current bias circuit, and is characterized in that it also includes a low-temperature high-order compensation circuit, a high-temperature high- order compensation circuit and negative feedback loop. The voltage reference source provided by the present invention adopts exponential curvature compensation at low temperature and piecewise linear curvature compensation at high temperature, has very good temperature stability and very low temperature coefficient, and can be applied to analog integrated circuits, high-precision digital Analog conversion circuits and pure digital integrated circuits.

Description

A full temperature range compensated voltage reference

technical field

The invention belongs to the technical field of power supplies, and in particular relates to the design of a voltage reference source.

Background technique

In analog, digital-analog hybrid, and even pure digital circuits, high-precision voltage reference sources are required, such as A/D converters, DRAMS, power converters, flash memory control circuits, etc. The stability of the voltage reference directly determines the quality of the circuit performance. The indicators describing the stability of the voltage reference source mainly include: power supply rejection ratio, temperature coefficient, etc. In order to meet the requirements of the circuit to work normally under harsh external temperature environment, the voltage reference must have a very small temperature coefficient, that is, very high temperature stability.

The function of the voltage reference source is to provide reference voltages to other functional modules in the circuit. It is a very important functional module in analog integrated circuits. It often provides reference voltages for ADCs, DACs, sensors, VCOs and other circuits. The traditional bandgap reference adopts first-order temperature compensation, which is mainly realized by V _BE with negative temperature coefficient and V _T with positive temperature coefficient. Neglecting the V _BE nonlinearity, the first-order temperature coefficient is usually limited to 20-100ppm/°C. To overcome this limitation, many high-order compensation techniques have been developed, such as second-order temperature compensation, exponential compensation, piecewise linear compensation, and temperature-dependent resistivity using high-value polycrystalline resistors and diffusion resistors. The temperature stability of bandgap references is indeed improved by these techniques, but they add some other requirements, such as current mirror matching, pre-regulation of supply voltage or the need for high-resistivity resistors.

Contents of the invention

The purpose of the present invention is to solve the problems existing in the existing voltage reference source during high-order compensation, and propose a voltage reference source with full temperature range compensation.

The technical solution of the present invention is: a voltage reference source with full temperature range compensation, including a start-up circuit, a first-order temperature compensation circuit, a proportional superposition output circuit and a current bias circuit, and is characterized in that it also includes a low-temperature high-order compensation circuit, High-temperature high-order compensation circuit and negative feedback loop, wherein, the start-up circuit provides start-up bias voltage for the voltage reference source, and the current bias circuit provides bias current for the first-order temperature compensation circuit and negative feedback loop. The negative feedback loop and the first-order temperature The compensation circuit is connected with the output circuit, and the first-order temperature compensation circuit, the low-temperature high-order compensation circuit and the high-temperature high-order compensation circuit output the high-order compensated voltage reference source in the full temperature range through the proportional superposition output circuit.

The current bias circuit includes PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP10, NMOS transistor MN1, resistor R1, NPN transistor Q3 and PNP transistor Q6, wherein the gate and drain of PMOS transistor MP2 Connect the gates of PMOS transistors MP3, MP4, MP5, MP6 and MP7 and the collector of NPN transistor Q3 at the same time, the source of PMOS transistor MP4 is connected to the drain of MP3, the source of PMOS transistor MP3 is connected to an external power supply, and the source of PMOS transistor MP3 is connected to the external power supply. The source of MP7 is connected to the drain of MP6, the source of PMOS transistor MP6 is connected to an external power supply, the drain of PMOS transistor MP7 is connected to the emitter of PNP transistor Q7 and used as node F, and the drain of PMOS transistor MP4 is connected to that of PNP transistor Q6 The emitter, the base of PNP transistor Q6 is connected to the drain of PMOS transistor MP11 as node B, the collector of PNP transistor Q6 is grounded, the gate of PMOS transistor MP10 is connected to the base of NPN transistor Q3 as node E, PMOS The drain of the tube MP10 is connected to the gate and the drain of the NMOS tube MN1, the source of the PMOS tube MP10 is connected to the node G, the source of the NMOS tube MN1 is grounded, and the emitter of the NPN transistor Q3 is grounded through the resistor R1;

The first-order temperature compensation circuit includes PMOS transistors MP11 and MP12, resistors R2 and R3, and NPN transistors Q4 and Q5, wherein the gate of the PMOS transistor MP11 is connected to the drain and simultaneously connected to the gate of the PMOS transistor MP12 and the NPN transistor Q4 The drain of the PMOS transistor MP12 is connected to the collector of the NPN transistor Q5 as node A, the bases of the NPN transistors Q4 and Q5 are respectively connected to the node E, and the NPN transistor Q4 and the NPN transistor Q5 are connected through the resistor R2 The emitters of the PMOS tubes are connected and used as node C, the node C is grounded through the resistor R3, and the sources of the PMOS transistors MP11 and MP12 are connected and used as the node G;

The negative feedback loop includes capacitor C1, PNP transistor Q7 and NPN transistor Q9, wherein the base of NPN transistor Q7 and one end of capacitor C1 are respectively connected to node A, the other end of capacitor C1 is grounded, and the collector of PNP transistor Q7 Grounded, the emitter of the NPN transistor Q9 as the output node is VREF, the emitter of the NPN transistor Q7 is connected to the base of the NPN transistor Q9 as node F;

The low-temperature high-order compensation circuit includes resistors R2, R3, R5, and R6, and NPN transistors Q4 and Q5, wherein one end of the resistor R6 is used as the output end of the voltage reference source, and the other end is connected in series with a resistor R5, and the other end of the resistor R5 is connected to The bases of NPN transistors Q4 and Q5 are connected;

The high-temperature high-order compensation circuit includes resistors R2, R3, R4, R5, R6, NPN transistors Q4, Q5, Q10, one end of the resistor R6 is used as the output node VREF, the other end is connected in series with a resistor R5, and the other end of the resistor R5 is connected to the NPN transistor The bases of Q4 and Q5 are connected, the junction of resistors R6 and R5 is node D and connected to the collector of NPN transistor Q10, the base of NPN transistor Q10 is connected to node C, and the emitter of NPN transistor Q10 is grounded through resistor R4;

The proportional superposition output circuit includes an NPN transistor Q9 and resistors R5 and R6, wherein the base of the NPN transistor Q9 is connected to the node F, the collector of the NPN transistor Q9 is connected to an external power supply, and the emitter of the NPN transistor is connected to the resistor R6 , at the same time as the output node VREF, the resistor R6 and R5 are connected in series to node D, and the other end of the resistor R5 is connected to node E.

Beneficial effects of the present invention: the present invention provides a voltage reference source with full temperature range compensation, which adopts exponential curvature compensation at low temperature and segmental linear curvature compensation at high temperature, and has very good temperature stability and very low temperature Coefficients can be applied in analog integrated circuits, high-precision digital-to-analog conversion circuits and pure digital integrated circuits.

Description of drawings

FIG. 1 is a schematic structural diagram of a voltage reference source for full temperature range compensation in the present invention.

FIG. 2 is a schematic diagram of a voltage reference source circuit for full temperature range compensation in the present invention.

FIG. 3 is a temperature characteristic diagram of the output voltage of the voltage reference source with full temperature range compensation according to the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The full temperature range compensation voltage reference source circuit block diagram of the present invention is shown in Figure 1, including a start-up circuit, a first-order temperature compensation circuit, a low-temperature high-order compensation circuit, a high-temperature high-order compensation circuit, a negative feedback loop, a proportional superposition output circuit and current bias circuit. The start-up circuit provides start-up bias voltage for the full temperature range compensation core circuit. When the whole circuit works stably, the start-up circuit stops working and is isolated from the whole circuit. The current bias circuit is mainly for the first-order temperature compensation circuit and negative feedback loop. bias current for proper operation. The negative feedback loop is mainly to improve the performance of the bandgap reference and improve the stability of the reference output voltage. The first-order temperature compensation circuit, the low-temperature high-order compensation circuit and the high-temperature high-order compensation circuit output the high-order compensated VREF in the full temperature range through the proportional superposition output circuit.

The schematic diagram of the voltage reference source circuit for full temperature range compensation is shown in Fig. 2 .

PTAT电压为：

式中，V_BE5为NPN三极管Q5的BE结电压，V_T为热电压。Among them, the first-order temperature compensation circuit includes PMOS transistors MP11 and MP12, resistors R2 and R3, and NPN transistors Q4 and Q5. Among them, the gate of the PMOS transistor MP11 is connected to the drain and is connected to the gate of the PMOS transistor MP12 and the collector of the NPN transistor Q4, the drain of the PMOS transistor MP12 is connected to the collector of the NPN transistor Q5 at node A, and the node of the NPN transistor Q4 It is connected to the base of Q5, and its node is E, and the emitter of NPN transistor Q4 and NPN transistor Q5 is connected through resistor R2, and its node is C, and node C is grounded through resistor R3. The bias current IBIAS1 is connected to the sources of the PMOS transistors MP11 and MP12. The first-order reference voltage is:

The PTAT voltage is:

In the formula, V _BE5 is the BE junction voltage of NPN transistor Q5, and V _T is the thermal voltage.

其中

式中V_T为热电压，ΔE_G为与发射极掺杂浓度成正比的射极带隙窄变因子，k为玻尔兹曼常数，β_∞是三极管共发射极电流增益的最大值，且β_∞是与温度无关的。Low-temperature high-order compensation circuit, including resistors R2, R3, R5, R6, NPN transistors Q4, Q5. Wherein, one end of the resistor R6 is connected to the output node VREF and the other end is connected to the resistor R5 in series, and the other end of the resistor R5 is connected to the bases of the NPN transistors Q4 and Q5 at the node E. Among them, the NPN transistors Q4 and Q5, and the resistors R6 and R5 themselves belong to the first-order temperature compensation circuit and are connected in the same way. At low temperatures, the exponential compensation voltage is:

in

where V _T is the thermal voltage, ΔE _G is the emitter bandgap narrowing factor proportional to the emitter doping concentration, k is the Boltzmann constant, β _∞ is the maximum value of the triode common emitter current gain, and β _∞ is independent of temperature.

High-temperature high-order compensation circuit, including resistors R2, R3, R4, R5, R6, NPN transistors Q4, Q5, Q10. Wherein, one end of the resistor R6 is connected to the output node VREF and the other end is connected to the resistor R5 in series, and the other end of the resistor R5 is connected to the bases of the NPN transistors Q4 and Q5, and the node is E. The junction of resistors R6 and R5 is node D and connected to the collector of NPN transistor Q10, the base of NPN transistor Q10 is connected to node C, and the emitter of NPN transistor Q10 is grounded through resistor R4. Among them, the NPN transistors Q4 and Q5, and the resistors R6 and R5 themselves belong to the first-order temperature compensation circuit and are connected in the same way. When the NPN transistor Q10 is turned on at high temperature, the segmented linear compensation voltage is: R ₆ /R ₄ (R ₃ /R ₂ V _T lnN-V _BE10 ), where V _BE10 (T ₁ )=(R ₃ /R ₂ ) V _T1 lnN, where T1 is the temperature when the NPN transistor Q10 is turned on, and V _BE10 is the BE junction voltage of the NPN transistor Q10.

环路的传输函数为：

其中，g_m4和g_m5分别为NPN三极管Q4和Q5的跨导，β₅为NPN三极管共发射极电流增益，r_o5为NPN三极管Q5的CE结电阻，r_o12为PMOS管MP12的漏源电阻，为用作尾电流偏置的PMOS管MP5的漏源电阻。The negative feedback loop includes capacitor C1, PNP transistor Q7 and NPN transistor Q9. Among them, the base of the NPN transistor Q7 is connected to the node A of the capacitor C1, the collector of the PNP transistor Q7 is grounded, the emitter of the NPN transistor Q9 is used as the output node VREF, and the emitter of the NPN transistor Q7 is connected to the base of the NPN transistor Q9. Node is F. NPN transistor Q7 improves the output impedance of node A, and capacitor C1 generates a dominant pole at node A as:

The transfer function of the loop is:

Among them, g _m4 and g _m5 are the transconductance of NPN transistor Q4 and Q5 respectively, β ₅ is the common emitter current gain of NPN transistor, r _o5 is the CE junction resistance of NPN transistor Q5, r _o12 is the drain-source resistance of PMOS transistor MP12 , It is the drain-source resistance of the PMOS transistor MP5 used as the tail current bias.

The role of the startup circuit is to ensure that the circuit works in the expected normal state when it is powered on. When the circuit is first powered on, the bases of Q1, Q2, and Q8 are at high potential, and node C is at low potential, so Q2 and Q8 are turned on, so there is current flowing through nodes C, F, and G, which will drive the circuit into Balanced state. When the circuit enters a balanced state and the potential of node C rises to a certain level, NPN transistors Q2 and Q8 are cut off.

The first-order temperature compensation circuit first generates a first-order bandgap voltage. The function of the PNP transistor Q6 is to compensate the base current of the PNP transistor Q7, so that the drain potentials of the PMOS transistors MP11 and MP12 are equal, so that the current flowing through the PMOS transistors MP11 and MP12 currents are equal.

其次产生C点处的PTAT电压，

C点处的电压可以控制NPN三极管Q10的通断，并以此来产生高阶温度补偿电压。It can be obtained from Figure 2:

Second, the PTAT voltage at point C is generated,

The voltage at point C can control the on-off of the NPN transistor Q10 to generate a high-order temperature compensation voltage.

The low-temperature high-order compensation circuit mainly generates exponential compensation voltage. Low temperature Q10 is turned off, it can be obtained from Figure 2: where β(T) is an exponential function with respect to temperature, which can be expressed as

其中高阶曲率补偿项

可在T_r处进行泰勒级数展开：The final output voltage at low temperature is:

Among them, the high-order curvature compensation term

A Taylor series expansion can be performed at T _r :

$\mathrm{<span\; class="notranslate">\; 2</span>}\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; \&infin;</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; exp</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; a</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; a</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; \&times;</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; a</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&times;</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; a</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; \&times;</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 4</span>}}$

和

可以消除V_BE自身的高阶项所引起的曲率，使得带隙基准电压得到优化。Among them, a ₀ , a ₁ , a ₂ , and a ₃ are temperature-independent constants. By setting the resistor ratio reasonably

and

The curvature caused by the higher-order terms of V _BE itself can be eliminated, so that the bandgap reference voltage is optimized.

The high-temperature high-order compensation circuit mainly generates exponential curvature compensation voltage and piecewise linear compensation voltage. In the high temperature range, the voltage of node C increases, while the voltage of V _RE10 with a negative temperature coefficient decreases, making the NPN transistor Q10 turn on, and the piecewise linear curvature compensation is realized through R4, R6 and Q10.

It can be obtained from Figure 2:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; REF</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 2</span>}\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{<span\; class="notranslate">\; \&infin;</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; exp</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 6</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; )</span>$

Among them, the additional linear voltage generated by resistor R6, NPN transistor Q10 and resistor R4 further compensates the reference source, making the reference source more accurate, and even reaching zero temperature coefficient at certain temperatures.

So far, the reference voltage output in the full temperature range is obtained:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BEF</span>}}<span\; class="notranslate">\; =</span>\left\{\begin{array}{c}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; exp</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\\ {\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; exp</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; E.</span>}}_{\mathrm{<span\; class="notranslate">\; G</span>}}}{\mathrm{<span\; class="notranslate">\; kT</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 4</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; \&Greater\; Equal;</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\end{array}\right.$

in, $K_1=\frac{R_3}{R_2}\ln N,K_2=2\frac{(R_5+R_6)\ln N}{R_2{\mathrm{\&beta;}}_{\&infin;}},{\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="HDA0000060374820000012.png"\; state="\{\{state\}\}">K</figure-callout>}}_3=\frac{R_6}{R_4},K_4=\frac{R_3}{R_2}.$

Figure 3 is the temperature characteristic diagram of the output voltage of the voltage reference source. Based on the 0.6μm BCD process, the proposed voltage reference circuit is verified, and the following experimental results are obtained: under the power supply voltage of 3.6V, the temperature is between -20°C and 120°C When changing, the temperature coefficient is 2.9ppm/℃; when the power supply voltage changes between 2.2V and 5V, the temperature coefficient is up to 5.3ppm/℃.

The voltage reference source of the present invention adopts exponential curvature compensation at low temperature and piecewise linear curvature compensation at high temperature, has very good temperature stability and very low temperature coefficient, and can be applied to analog integrated circuits, high-precision digital-analog Conversion circuits and pure digital integrated circuits.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (2)

1. A voltage reference source compensated in a full temperature range, comprising a start-up circuit, a first-order temperature compensation circuit, a proportional superposition output circuit and a current bias circuit, characterized in that it also includes a low-temperature high-order compensation circuit and a high-temperature high-order compensation circuit and a negative feedback loop, wherein the start-up circuit provides a start-up bias voltage for the voltage reference source, the current bias circuit provides a bias current for the first-order temperature compensation circuit and the negative feedback loop, and the negative feedback loop is superimposed with the first-order temperature compensation circuit and the ratio The output circuits are connected, and the first-order temperature compensation circuit, the low-temperature high-order compensation circuit and the high-temperature high-order compensation circuit output the high-order compensated voltage reference source in the full temperature range through the proportional superposition output circuit. 2. The voltage reference source of full temperature range compensation according to claim 1, characterized in that, The current bias circuit includes PMOS transistors MP2, MP3, MP4, MP5, MP6, MP7, MP10, NMOS transistor MN1, resistor R1, NPN transistor Q3 and PNP transistor Q6, wherein the gate and drain of PMOS transistor MP2 Connect the gates of PMOS transistors MP3, MP4, MP5, MP6 and MP7 and the collector of NPN transistor Q3 at the same time, the source of PMOS transistor MP4 is connected to the drain of MP3, the source of PMOS transistor MP3 is connected to an external power supply, and the source of PMOS transistor MP3 is connected to the external power supply. The source of MP7 is connected to the drain of MP6, the source of PMOS transistor MP6 is connected to an external power supply, the drain of PMOS transistor MP7 is connected to the emitter of PNP transistor Q7 and used as node F, and the drain of PMOS transistor MP4 is connected to that of PNP transistor Q6 The emitter, the base of PNP transistor Q6 is connected to the drain of PMOS transistor MP11 as node B, the collector of PNP transistor Q6 is grounded, the gate of PMOS transistor MP10 is connected to the base of NPN transistor Q3 as node E, PMOS The drain of the tube MP10 is connected to the gate and the drain of the NMOS tube MN1, the source of the PMOS tube MP10 is connected to the node G, the source of the NMOS tube MN1 is grounded, and the emitter of the NPN transistor Q3 is grounded through the resistor R1; The first-order temperature compensation circuit includes PMOS transistors MP11 and MP12, resistors R2 and R3, and NPN transistors Q4 and Q5, wherein the gate of the PMOS transistor MP11 is connected to the drain and simultaneously connected to the gate of the PMOS transistor MP12 and the NPN transistor Q4 The drain of the PMOS transistor MP12 is connected to the collector of the NPN transistor Q5 as node A, the bases of the NPN transistors Q4 and Q5 are respectively connected to the node E, and the NPN transistor Q4 and the NPN transistor Q5 are connected through the resistor R2 The emitters of the PMOS tubes are connected and used as node C, the node C is grounded through the resistor R3, and the sources of the PMOS transistors MP11 and MP12 are connected and used as the node G; The negative feedback loop includes capacitor C1, PNP transistor Q7 and NPN transistor Q9, wherein the base of NPN transistor Q7 and one end of capacitor C1 are respectively connected to node A, the other end of capacitor C1 is grounded, and the collector of PNP transistor Q7 Grounded, the emitter of the NPN transistor Q9 as the output node is VREF, the emitter of the NPN transistor Q7 is connected to the base of the NPN transistor Q9 as node F; The low-temperature high-order compensation circuit includes resistors R2, R3, R5, and R6, and NPN transistors Q4 and Q5, wherein one end of the resistor R6 is used as the output end of the voltage reference source, and the other end is connected in series with a resistor R5, and the other end of the resistor R5 is connected to The bases of NPN transistors Q4 and Q5 are connected; The high-temperature high-order compensation circuit includes resistors R2, R3, R4, R5, R6, NPN transistors Q4, Q5, Q10, one end of the resistor R6 is used as the output node VREF, the other end is connected in series with a resistor R5, and the other end of the resistor R5 is connected to the NPN transistor The bases of Q4 and Q5 are connected, the junction of resistors R6 and R5 is node D and connected to the collector of NPN transistor Q10, the base of NPN transistor Q10 is connected to node C, and the emitter of NPN transistor Q10 is grounded through resistor R4; The proportional superposition output circuit includes an NPN transistor Q9 and resistors R5 and R6, wherein the base of the NPN transistor Q9 is connected to the node F, the collector of the NPN transistor Q9 is connected to an external power supply, and the emitter of the NPN transistor is connected to the resistor R6 , at the same time as the output node VREF, the resistor R6 and R5 are connected in series to node D, and the other end of the resistor R5 is connected to node E.

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