CN103197716A - Band-gap reference voltage circuit for reducing offset voltage influence - Google Patents

Abstract

A band-gap reference voltage circuit for reducing offset voltage influence is based on a traditional band-gap reference voltage circuit structure and provided with plug-and-play (PNP) triodes Q1, Q2 and Q3, an operational amplifier OP, resistors R1 and R2, and P-channel metal oxide semiconductor tubes M1, M2 and M3. The band-gap reference voltage circuit is characterized in that a resistor R3 and a resistor R5 are respectively added between an emitter and a base of the PNP triodes Q1 and Q2, and a resistor R4 and a resistor R6 are respectively added between the bases of the PNP triodes Q1 and Q2 and the ground. By leading in a divider resistance network, the offset voltage VOS coefficients are structurally reduced, the influence of the offset voltage to the reference voltage is reduced accordingly, and the standard voltage with high accuracy and better stability can be obtained.

Description

A Bandgap Reference Voltage Circuit with Reduced Effect of Offset Voltage

technical field

The invention relates to a bandgap reference circuit, in particular to a bandgap reference voltage circuit that reduces the influence of offset voltage, and belongs to the technical field of bipolar transistor (BJT) and metal oxide semiconductor (MOS) transistor integrated circuits.

Background technique

In the prior art, there is a traditional bandgap reference voltage circuit as shown in Figure 1, which is provided with PNP transistors Q1, Q2 and Q3, operational amplifier OP, resistors R1 and R2, PMOS transistors M1, M2 and M3; PNP transistor Q1 The bases and collectors of Q2 and Q3 are grounded, the emitter of PNP transistor Q1 is connected to the non-inverting input terminal of amplifier OP and the drain of PMOS transistor M1 (node A) through resistor R1, and the emitter of PNP transistor Q2 is connected to amplifier OP The inverting input terminal of the operational amplifier OP is connected to the drain of the PMOS transistor M2 (node B), the output terminal of the operational amplifier OP is connected to the gates of the PMOS transistors M1, M2, and M3, and the sources and substrates of the PMOS transistors M1, M2, and M3 are connected Connected to the power supply VDD, the emitter of the PNP transistor Q3 is connected to the drain of the PMOS transistor M3 (node C) through the resistor R2 and outputs the reference voltage V _ref as an output terminal.

The working principle in Figure 1 is as follows: PMOS transistors M1, M2 and M3 with the same aspect ratio constitute an equal-proportion current mirror, so that the branch currents flowing through the transistors Q1, Q2 and Q3 are equal, that is, I _Q1 =I _Q2 =I _Q3 . The base-emitter voltage of transistor Q2 is:

$V_{\mathrm{BE}2}=V_T\ln \left(\frac{I_{Q2}}{I_{S0}}\right)$ (Formula 1)

三极管Q1的基极-发射极电压为：Wherein, V _T is the thermal voltage, which is about 26mv at normal temperature, and I _S0 is the saturation current of the triode Q2 and its value is proportional to the emitter area of the triode. The base-emitter voltage V _BE of the triode is the CTAT (negative temperature coefficient) voltage. At room temperature, when V _BE ≈ 750mV,

The base-emitter voltage of transistor Q1 is:

$V_{\mathrm{BE}1}=V_T\ln \left(\frac{I_{Q1}}{{\mathrm{NI}}_{S0}}\right)$ (Formula 2)

Wherein, N is the ratio of the emitter area of the triode Q1 and Q2, and the value of N is usually taken as 8 in order to make the matching of the triode Q1 and Q2 better. The operational amplifier OP works in deep negative feedback, so that the voltages of the nodes A and B of the same input terminal and the reverse input terminal are equal, and the voltage drop on the resistor R1 is:

${\mathrm{\ΔV}}_{\mathrm{BE}}=V_{\mathrm{BE}2}-V_{\mathrm{BE}1}=V_T\ln \left(\frac{I_{Q2}}{I_{S0}}\right)-V_T\ln \left(\frac{I_{Q1}}{{\mathrm{NI}}_{S0}}\right)=V_T\ln N=I_{Q1}{R}_1$ (Formula 3)

And V _T =kT/q, k is Boltzmann's constant, q is the charge carried by an electron, and the temperature coefficient of V _T is:

   （公式4）

(Formula 4)

Among them, T ₀ =300K. It can be seen from the above formula that the thermal voltage V _T has a positive temperature coefficient, so the temperature coefficient of ΔV _BE is also positive, and ΔV _BE obtains a PTAT (positive temperature coefficient) current I _Q1 ( Voltage to current), since I _Q1 = I _Q3 , obviously I _Q3 is also PTAT current, I _Q3 flows through resistor R2 to generate a PTAT voltage (current to voltage), this voltage is added to CTAT voltage V _BE3 (voltage summation) constitutes the output reference voltage V _ref :

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}{V}_T\ln N$ (Formula 5)

即可到一个近似与温度无关的基准电压，此时V_ref≈1.2V。When V _BE3 ≈750mV, N=8, adjust resistors R1 and R2 so that

That is, a reference voltage that is approximately temperature-independent can be obtained, and V _ref ≈1.2V at this time.

Due to the asymmetry of the branch where the non-inverting terminal and the inverting terminal of the operational amplifier are located and the limited gain, it will be affected by the input offset. When there is an offset voltage V _os in the operational amplifier, if V _b =V _a -V _os , then the output reference voltage V _ref,os after considering the offset is:

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (Formula 6)

The offset voltage is amplified by R2/R1 times, which introduces errors in the reference voltage and reduces the accuracy of the reference voltage. In addition, the offset voltage V _os itself will vary with temperature, thus increasing the temperature drift of the reference voltage. It can be seen from the above formula that the coefficient of the offset voltage V _os is the same as that of ΔV _BE , and this coefficient is determined in order to satisfy the offset of positive and negative temperature coefficients. For example, in formula 5, when V _BE3 ≈750mV, take N=8, then An offset voltage V _os =±5mV will cause a reference deviation ΔV _ref ≈±41.5mV. It can be seen that the offset voltage is amplified by 8.3 times, which has a great influence on the reference accuracy.

In practical applications, the problem of offset voltage will be more prominent. Because not only the circuit structure will introduce offset, but also there are many factors that cause offset in the process, such as the mismatch between resistors, the mismatch of transistors, the mismatch of threshold voltage of transistors in the input stage of op amps, and so on.

In order to solve this problem, most of the existing technologies reduce the value of the offset voltage V _os by various methods from the perspective of designing an operational amplifier to reduce the influence of the offset voltage on the reference voltage. However, as mentioned above, V _OS is difficult to completely eliminate.

Contents of the invention

Aiming at the above-mentioned problem that the offset voltage has an influence on the reference voltage, the present invention provides a bandgap reference voltage circuit that reduces the influence of the offset voltage. proportion.

For realizing the object of the present invention, the technical scheme that takes is as follows: a kind of bandgap reference voltage circuit that reduces offset voltage influence, based on traditional bandgap reference voltage circuit structure, is provided with PNP triode Q1, Q2 and Q3, operational amplifier OP, resistor R1 and R2, PMOS transistors M1, M2 and M3; the bases and collectors of PNP transistors Q1, Q2 and Q3 are grounded, and the emitter of PNP transistor Q1 is connected to the non-inverting input terminal of the amplifier OP and the drain of PMOS transistor M1 through resistor R1 The emitter of the PNP transistor Q2 is connected to the inverting input of the amplifier OP and the drain of the PMOS transistor M2, the output of the operational amplifier OP is connected to the gates of the PMOS transistors M1, M2, M3, and the PMOS transistors M1, M2, M3 Both the source and the substrate of the PNP transistor Q3 are connected to the power supply VDD, and the emitter of the PNP transistor Q3 is connected to the drain of the PMOS transistor M3 through the resistor R2 and used as the output terminal to output the reference voltage V _ref ; Resistors R3 and R5 are respectively added between the ground and the base, and resistors R4 and R6 are respectively added between the bases of the PNP transistors Q1 and Q2 and the ground.

The resistance R3=R5, R4=R6, R3<R4.

Compared with prior art, the beneficial effect of the present invention is:

The bandgap reference voltage circuit structure provided by the present invention does not reduce the offset voltage from the perspective of designing an operational amplifier, but starts with a more essential bandgap reference structure, and realizes the base-emitter voltage of the triode by introducing a resistor divider network Doubling, reducing the coefficient of V _os structurally, thereby reducing the influence of the offset voltage of the operational amplifier on the reference voltage, has a more general significance.

Description of drawings

Fig. 1 is a kind of bandgap reference voltage circuit in the prior art;

Fig. 2 is the bandgap reference voltage circuit of the present invention that reduces the influence of offset voltage;

Fig. 3 is another embodiment of Fig. 2 .

Detailed ways

The principles and features of the present invention will be described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

Referring to Fig. 2, the bandgap reference voltage circuit of the present invention that reduces the influence of the offset voltage includes PNP transistors Q1, Q2 and Q3, PMOS transistors M1, M2 and M3, operational amplifier OP, resistors _R1 , _R2 , _R3 , _R4 , R ₅ , R ₆ ; Resistor R4 is connected across the base of PNP transistor Q1 and ground, resistor R3 is connected between the base and emitter of PNP transistor Q1, and resistor R6 is connected across the base of PNP transistor Q2 Between the ground and the ground, the resistor R5 is connected between the base and the emitter of the PNP transistor Q2, the collectors of the PNP transistors Q1 and Q2 are grounded, the base and collector of the PNP transistor Q3 are grounded, and the emitter of the PNP transistor Q1 passes through Resistor _R1 is connected to the non-inverting input terminal of the operational amplifier OP and the drain of the PMOS transistor M1 and is marked as node A, and the emitter of the PNP transistor Q2 is connected to the inverting input terminal of the operational amplifier OP and the drain of the PMOS transistor M2 And marked as node B, the output terminal of the operational amplifier OP is connected to the gates of PMOS transistors M1, M2 and M3, the emitter of PNP transistor Q3 is connected to the drain of PMOS transistor M3 through resistor _R2 and marked as node C, The sources and substrates of the PMOS transistors M1, M2 and M3 are connected to the power supply voltage VDD, and the node C outputs the reference voltage V _ref .

Compared with the conventional structure in Fig. 1, the circuit of the present invention adds resistors R4 and R3 respectively between the base and the ground of the PNP transistor Q1 and between the base and the emitter; between the base and the ground of the PNP transistor Q2 and Resistors R6 and R5 are respectively added between the base and the emitter, R3=R5, R4=R6, R3<R4.

The operating principle of the circuit of the present invention is:

为传统带隙基准电路中的

倍，Q2的发射极电压为

为传统带隙基准电路中的

倍。运算放大器OP工作在深度负反馈使得节点A和节点B的电压相等，即Assuming that the emitter areas of PNP transistors Q1, Q2 and Q3 in circuit diagram 2 of the present invention are equal to the emitter areas of PNP transistors Q1, Q2 and Q3 in traditional structure Fig. 1 respectively; Circuit diagram 2 of the present invention flows through the current I _Q1 of each PNP transistors , I _Q2 , I _Q3 are also equal to the current I _Q1 , I _Q2 , I _Q3 of each PNP transistor in the traditional structure Fig. 1, then the base-emitter voltage V _BE1 of each PNP transistor in the circuit Fig. 2 of the present invention is also equal respectively . Then by the principle of resistance voltage division, the emitter voltage of Q1 in the circuit diagram 2 of the present invention is

for traditional bandgap reference circuits

times, the emitter voltage of Q2 is

for traditional bandgap reference circuits

times. The operational amplifier OP works in deep negative feedback so that the voltages of nodes A and B are equal, that is

V _A =V _B (Equation 7)

则运算放大器OP同相端和反相端所在的支路电流为：Since the current mirror tubes M2 and M1 have the same width-to-length ratio and are connected by a current mirror, so I ₁ =I ₂ , in order to ensure that I _Q1 =I _Q2 , the currents flowing through the two resistor networks are required to be equal, which is taken here

Then the branch current of the non-inverting terminal and the inverting terminal of the operational amplifier OP is:

$I_1=I_2=\frac{\frac{R_5+R_6}{R_5}{V}_{\mathrm{BE}2}-\frac{R_3+R_4}{R_3}{V}_{\mathrm{BE}1}}{R_1}=\frac{R_3+R_4}{R_3}\frac{{\mathrm{\&Delta;V}}_{\mathrm{BE}}}{R_1}=\frac{R_3+R_4}{R_3}\frac{V_T\ln N}{R_1}$ (Formula 8)

在电阻R1上完成电压-电流转换。I₁正比于热电压V_T，即I₁是与绝对温度成正比的电流（PTAT电流）。由于电流镜管M3和M1、M2具有相同的宽长比，且为电流镜连接，因此V _BE1 and V _BE2 are the base-emitter voltages of PNP transistors Q1 and Q2, N is the ratio of the emitter areas of PNP transistors Q1 and Q2,

The voltage-to-current conversion is done across resistor R1. I ₁ is proportional to the thermal voltage V _T , i.e. I ₁ is a current proportional to absolute temperature (PTAT current). Since the current mirror tube M3 has the same width-to-length ratio as M1 and M2, and is connected by a current mirror, therefore

I ₃ =I ₁ =I ₂ (Equation 9)

I ₃ flows through the resistor R ₂ to complete the current-voltage conversion, and obtain a voltage proportional to the absolute temperature (PTAT voltage):

$R_2{I}_3=\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (Formula 10)

Adding this PTAT voltage R ₂ I ₃ to the CTAT voltage V _BE3 gives the output reference voltage as:

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (Formula 11)

时即可到一个近似与温度无关的基准电压，此时V_ref≈1.2V。When V _BE3 ≈750mV, take N=8, let

A reference voltage that is approximately temperature-independent can be obtained when V _ref ≈ 1.2V.

When considering the offset voltage V _os of the operational amplifier, the output reference voltage V _ref,os is:

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (Formula 12)

运放失调电压V_os=±5mV时将引起基准偏差ΔV_ref≈±2.075mV。即在本发明中，失调电压不但没有被放大，反而被衰减了，因此本发明可以显著地降低失调电压对对基准电压的影响。在精确度要求较高的场合，将

的值设为几十甚至上百倍可以使失调电压的影响降至极低。It is worth noting that, compared with formula 6 in the traditional bandgap circuit, the coefficient of the offset voltage V _os in this structure is only related to the partial coefficient of ΔV _BE , and the ratio of the resistors R1 and R2 can be adjusted to reduce the coefficient of the offset voltage Influence, when R2/R1<1, the offset voltage is attenuated instead of being amplified like in the traditional structure. When V _BE3 ≈750mV, N=8, R ₄ =19R ₃ , then

The reference deviation ΔV _ref ≈±2.075mV will be caused when the operational amplifier offset voltage V _os =±5mV. That is, in the present invention, the offset voltage is not amplified but attenuated, so the present invention can significantly reduce the impact of the offset voltage on the reference voltage. Where higher accuracy is required, the

The value of is set to tens or even hundreds of times to make the influence of the offset voltage extremely low.

Fig. 3 is another embodiment of the circuit of the present invention. Replace the PNP transistor in Figure 2 with an NPN transistor.

The analysis is the same as in Figure 2, and the output reference voltage is obtained as:

$V_{\mathrm{ref}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N$ (Formula 13)

When considering the offset voltage V _os of the operational amplifier, the output reference voltage V _ref,os is

$V_{\mathrm{ref},\mathrm{os}}=V_{\mathrm{BE}3}+\frac{R_2}{R_1}\frac{R_3+R_4}{R_3}{V}_T\ln N-\frac{R_2}{R_1}{V}_{\mathrm{os}}$ (Formula 14)

Compared with FIG. 2 , it can be found that the NPN transistor used in this embodiment can also achieve the effect of reducing the influence of the offset voltage on the reference voltage.

The above descriptions are only preferred examples of the present invention, and are not limited to the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (2)

1. A bandgap reference voltage circuit that reduces the influence of offset voltage, based on the traditional bandgap reference voltage circuit structure, is provided with PNP transistors Q1, Q2 and Q3, operational amplifier OP, resistors R1 and R2, PMOS transistors M1, M2 and M3; the bases and collectors of PNP transistors Q1, Q2 and Q3 are grounded, the emitter of PNP transistor Q1 is connected to the non-inverting input terminal of amplifier OP and the drain of PMOS transistor M1 through resistor R1, and the emitter of PNP transistor Q2 is connected to the amplifier The inverting input terminal of OP is connected to the drain of PMOS transistor M2, the output terminal of operational amplifier OP is connected to the gates of PMOS transistors M1, M2, and M3, and the sources and substrates of PMOS transistors M1, M2, and M3 are connected to the power supply VDD , the emitter of the PNP transistor Q3 is connected to the drain of the PMOS transistor M3 through a resistor R2 and used as an output terminal to output a reference voltage V _ref ; it is characterized in that: resistors R3 and R5, resistors R4 and R6 are respectively added between the bases of the PNP transistors Q1 and Q2 and the ground. 2. The bandgap reference voltage circuit for reducing the influence of offset voltage according to claim 1, characterized in that: resistors R3=R5, R4=R6, R3>R4.

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