WO2023124636A1 - Low-mismatch operational amplifier, bandgap reference circuit, and chip - Google Patents

Abstract

The embodiments of the present invention provide a low-mismatch operational amplifier, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first resistor and a second resistor. According to the low-mismatch operational amplifier of the present invention, a transistor of an operational amplifier in the related art is replaced by the first resistor and the second resistor, and devices and bias circuits that are connected to the first resistor and the second resistor are adjusted. The circuit effectively reduces the mismatch of the operational amplifier by taking advantage of the better resistance matching characteristics of the first resistor and the second resistor than those of the transistors and the flexibility in the bias circuit. The embodiments of the present invention further provide a bandgap reference circuit and a chip that use the low-mismatch operational amplifier. By using the technical solution of the present invention, the mismatch of the operational amplifier is low.

Description

Low Mismatch Operational Amplifiers, Bandgap Reference Circuits, and Chips technical field

The utility model relates to the technical field of operational amplifier circuits, in particular to a low-mismatch operational amplifier, a bandgap reference circuit and a chip.

Background technique

At present, with the rapid development of semiconductor technology, the use of integrated circuits has spread across various fields, among which operational amplifiers are often used for the calculation of various analog signals, and are important components in analog circuit design. The mismatch of the op amp will often affect the accuracy of the final required specification of the op amp.

The operational amplifier shown in FIG. 1 is a commonly used operational amplifier in the related art. The operational amplifier of the related art includes a twenty-first transistor P21, a twelfth transistor P12, a thirteenth transistor P13, a fourteenth transistor P14, a fifteenth transistor P15, a sixteenth transistor P16, a seventeenth transistor P17, a The eighteenth transistor N18, the nineteenth transistor N19, the twentieth transistor N20, and the twenty-second transistor N22. The input offset voltage Vos,in of the operational amplifier of the related art satisfies the following formula (1):

Wherein, it can be obtained from the formula that the input offset voltage Vos,in is related to relevant parameters of the twelfth transistor P12 , the fourteenth transistor P14 and the twentieth transistor N20 .

However, the input offset voltage of the operational amplifier in the related art is limited by the process and transistor parameters of the twentieth transistor N20 , how to reduce the operational amplifier is a technical problem that needs to be solved.

Therefore, it is necessary to provide a new operational amplifier and related circuits and chips to solve the above problems.

Utility model content

Aiming at the above deficiencies in the prior art, the utility model proposes a low-mismatch operational amplifier, a bandgap reference circuit and a chip with low mismatch of the operational amplifier.

In order to solve the above technical problems, in the first aspect, embodiments of the present invention provide a low-mismatch operational amplifier, the low-mismatch operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first resistor, and a second resistor;

The gate of the first transistor is connected to a first bias voltage, the source of the first transistor is connected to a power supply voltage, and the drain of the first transistor is respectively connected to the source of the second transistor and the the source of the third transistor;

The gate of the second transistor is used as the negative input terminal of the low mismatch operational amplifier, and the drain of the second transistor is respectively connected to the source of the eleventh transistor and the first resistor of the second resistor. end;

The gate of the third transistor is used as the positive input terminal of the low mismatch operational amplifier, and the drain of the third transistor is respectively connected to the source of the tenth transistor and the first end of the first resistor ;

The source of the fourth transistor is connected to the power supply voltage, the drain of the fourth transistor is connected to the source of the sixth transistor, and the gate of the fourth transistor is respectively connected to the gate of the fifth transistor. Pole, the drain of the sixth transistor and the drain of the eighth transistor;

The source of the fifth transistor is connected to a power supply voltage, and the drain of the fifth transistor is connected to the source of the seventh transistor;

The gate of the sixth transistor is respectively connected to the gate of the seventh transistor and a second bias voltage;

The drain of the seventh transistor is used as the output terminal of the low-mismatch operational amplifier, and the drain of the seventh transistor is connected to the drain of the ninth transistor;

The gate of the eighth transistor is respectively connected to the gate of the ninth transistor and a third bias voltage, and the source of the eighth transistor is connected to the source of the tenth transistor;

The source of the ninth transistor is connected to the source of the eleventh transistor;

The gate of the tenth transistor is respectively connected to the gate of the eleventh transistor and a fourth bias voltage;

Both the second end of the first resistor and the second end of the second resistor are connected to ground.

Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are all PMOS transistors, and the first The eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all NMOS transistors.

Preferably, both the first resistor and the second resistor are parameter-adjustable resistors.

In the second aspect, the embodiment of the present invention further provides a bandgap reference circuit, the bandgap reference circuit includes the above-mentioned low-mismatch operational amplifier provided by the embodiment of the present invention.

Preferably, the bandgap reference circuit further includes a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a third resistor, a fourth resistor, a first bipolar transistor, a second bipolar transistor and a third bipolar transistor;

The source of the twenty-third transistor is connected to a power supply voltage, and the gate of the twenty-third transistor is respectively connected to the gate of the twenty-fourth transistor, the gate of the twenty-fifth transistor, and the gate of the twenty-fifth transistor. The output terminal of the low mismatch operational amplifier, the drain of the twenty-third transistor is respectively connected to the collector of the first bipolar transistor and the negative input terminal of the low mismatch operational amplifier;

The source of the twenty-fourth transistor is connected to a power supply voltage, and the drain of the twenty-fourth transistor is respectively connected to the first end of the third resistor and the positive input end of the low mismatch operational amplifier;

The source of the twenty-fifth transistor is connected to the power supply voltage; the drain of the twenty-fifth transistor is used as the output end of the bandgap reference circuit, and the drain of the twenty-fifth transistor is connected to the The first end of the fourth resistor;

The second end of the third resistor is connected to the collector of the second bipolar transistor;

The second end of the fourth resistor is connected to the collector of the third bipolar transistor;

the base of the first bipolar transistor, the emitter of the first bipolar transistor, the base of the second bipolar transistor, the emitter of the second bipolar transistor, the Both the base of the third bipolar transistor and the emitter of the third bipolar transistor are connected to ground.

Preferably, the twenty-third transistor, the twenty-fourth transistor and the twenty-fifth transistor are all PMOS transistors.

In a third aspect, the embodiment of the present invention further provides a chip, and the chip includes the above-mentioned low-mismatch operational amplifier provided by the embodiment of the present invention.

Compared with the related art, the low-mismatch operational amplifier of the embodiment of the utility model sets the first resistor and the second resistor, and replaces the transistor of the operational amplifier of the related art through the first resistor and the second resistor, and respectively compares with the first resistor and the second resistor. The first resistor and the second resistor are connected to the device and the bias circuit for adjustment. The circuit effectively reduces the mismatch of the operational amplifier because the matching characteristic of the resistance is better than that of the transistor and the flexibility in the bias circuit. Therefore, the low mismatch operational amplifier, the bandgap reference circuit and the chip operational amplifier of the embodiment of the present invention have low mismatch.

Description of drawings

Below in conjunction with accompanying drawing, describe the utility model in detail. Through the detailed description in conjunction with the following drawings, the content of the above or other aspects of the present invention will become clearer and easier to understand. In the attached picture,

Fig. 1 is the application circuit schematic diagram of the operational amplifier of related art;

Fig. 2 is the circuit structure diagram of the low-mismatch operational amplifier of the first embodiment of the utility model;

FIG. 3 is a circuit structure diagram of the bandgap reference circuit of the second embodiment of the present invention.

Detailed ways

The specific embodiment of the utility model will be described in detail below in conjunction with the accompanying drawings.

The specific implementations/embodiments described here are specific specific implementations of the present utility model, and are used to illustrate the concept of the present utility model. Limitations on the scope of utility models. In addition to the embodiments described here, those skilled in the art can also adopt other obvious technical solutions based on the claims of the application and the contents disclosed in the description, and these technical solutions include adopting any obvious changes made to the embodiments described here. The replacement and modified technical solutions are all within the protection scope of the present utility model.

(first embodiment)

The utility model provides a low-mismatch operational amplifier 100 .

Please refer to FIG. 2 . FIG. 2 is a circuit structure diagram of a low mismatch operational amplifier 100 according to an embodiment of the present invention.

The low mismatch operational amplifier 100 includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor N8, a Nine transistors N9, tenth transistors N10, eleventh transistors N11, first resistor R1 and second resistor R2.

Wherein, the first transistor P1, the second transistor P2, the third transistor P3, the fourth transistor P4, the fifth transistor P5, the sixth transistor P6, and the seventh transistor P7 , the eighth transistor N8 , the ninth transistor N9 , the tenth transistor N10 and the eleventh transistor N11 are field effect transistors. Specifically, the first transistor P1, the second transistor P2, the third transistor P3, the fourth transistor P4, the fifth transistor P5, the sixth transistor P6 and the seventh transistor P7 are all is a PMOS transistor, and the eighth transistor N8, the ninth transistor N9, the tenth transistor N10 and the eleventh transistor N11 are all NMOS transistors.

The circuit connection relationship of the low mismatch operational amplifier 100 is:

The gate of the first transistor P1 is connected to the first bias voltage Vb1, the source of the first transistor P1 is connected to the power supply voltage VDD, and the drains of the first transistor P1 are respectively connected to the second transistors the source of P2 and the source of the third transistor P3.

The gate of the second transistor P2 is used as the negative input terminal Vinn of the low-mismatch operational amplifier 100, and the drain of the second transistor P2 is respectively connected to the source of the eleventh transistor N11 and the first The first end of the second resistor R2.

The gate of the third transistor P3 is used as the positive input terminal Vinp of the low mismatch operational amplifier 100, and the drain of the third transistor P3 is respectively connected to the source of the tenth transistor N10 and the first The first terminal of resistor R1.

The source of the fourth transistor P4 is connected to the power supply voltage VDD, the drain of the fourth transistor P4 is connected to the source of the sixth transistor P6, and the gates of the fourth transistor P4 are respectively connected to the The gate of the fifth transistor P5, the drain of the sixth transistor P6 and the drain of the eighth transistor N8.

The source of the fifth transistor P5 is connected to the power supply voltage VDD, and the drain of the fifth transistor P5 is connected to the source of the seventh transistor P7.

The gate of the sixth transistor P6 is respectively connected to the gate of the seventh transistor P7 and the second bias voltage Vb2.

The drain of the seventh transistor P7 serves as the output terminal OPOUT of the low mismatch operational amplifier 100 , and the drain of the seventh transistor P7 is connected to the drain of the ninth transistor N9 .

The gate of the eighth transistor N8 is respectively connected to the gate of the ninth transistor N9 and the third bias voltage Vb3 , and the source of the eighth transistor N8 is connected to the source of the tenth transistor N10 .

The source of the ninth transistor N9 is connected to the source of the eleventh transistor N11.

The gate of the tenth transistor N10 is respectively connected to the gate of the eleventh transistor N11 and the fourth bias voltage Vb4.

Both the second end of the first resistor R1 and the second end of the second resistor R2 are connected to the ground GND.

The input offset voltage Vos,in of the low mismatch operational amplifier 100 satisfies the following formula (2):

Among them, V _GS is the gate and source voltage difference of the transistor, V _TH is the turn-on voltage of the transistor, P2 is the second transistor, P4 is the fourth transistor, W is the gate width of the transistor, L is W is the transistor Gate length, Δ(W/L) is the error value of the ratio of the gate width to the gate length of the transistor, ΔV _TH is the error value of the turn-on voltage of the transistor, g _m is the transconductance of the transistor, k is the circuit parameter, T is the working temperature, and R is the resistance value of the first resistor R1.

The formula (2) of the input offset voltage of the low-mismatch operational amplifier 100 is compared with the formula (1) of the input offset voltage of the operational amplifier of the related art, the difference is that: the formula) is the relevant parameter of the twentieth transistor N20, The formula (2) is the resistance R of the first resistor R1. Right now

of formula (1)

不同。 with formula (2)

different.

Among them, because

That is, the resistance matching characteristics of the low-mismatch operational amplifier 100 are much better than the transistor matching characteristics of the operational amplifier of the related art, so that a smaller input offset voltage is obtained, thereby improving the operational amplifier offset characteristics. The flexibility of the first resistor R1 and the second resistor R2 of the low-mismatch operational amplifier 100 in the bias circuit also effectively reduces the mismatch of the operational amplifier.

The fourth transistor P4, the fifth transistor P5, the sixth transistor P6, the seventh transistor P7, the eighth transistor N8, the ninth transistor N9, the tenth transistor N10, the The eleventh transistor N11, the first resistor R1 and the second resistor R2 together form a bias circuit connected to the output terminal OPOUT. The flexibility of the first resistor R1 and the second resistor R2 in the bias circuit is beneficial to adjust the input offset voltage of the low-mismatch operational amplifier 100.

In this implementation manner, both the first resistor R1 and the second resistor R2 are parameter-adjustable resistors. The first resistor R1 and the second resistor R2 with adjustable parameters can dynamically adjust the input offset voltage of the low mismatch operational amplifier 100 , so that the circuit performance of the low mismatch operational amplifier 100 is good.

It should be pointed out that the relevant transistors and resistors used in the present invention are commonly used components in the field, and the specific indicators and parameters corresponding to the components can be adjusted according to actual applications, and will not be described in detail here.

(second embodiment)

The embodiment of the present invention also provides a bandgap reference circuit 200 . The bandgap reference circuit 200 includes the low mismatch operational amplifier 100 .

Please refer to FIG. 3 , which is a circuit structure diagram of a bandgap reference circuit 200 according to a second embodiment of the present invention.

The bandgap reference circuit 200 also includes a twenty-third transistor P23, a twenty-fourth transistor P24, a twenty-fifth transistor P25, a third resistor R3, a fourth resistor R4, a first bipolar transistor Q1, a second bipolar transistor Q2 and a third bipolar transistor Q3.

Wherein, the twenty-third transistor P23 , the twenty-fourth transistor P24 and the twenty-fifth transistor P25 are all PMOS transistors.

The circuit connection relationship of the bandgap reference circuit 200 is:

The source of the twenty-third transistor P23 is connected to the power supply voltage VDD, the gate of the twenty-third transistor P23 is respectively connected to the gate of the twenty-fourth transistor P24, the gate of the twenty-fifth transistor The gate of P25 and the output terminal OPOUT of the low mismatch operational amplifier 100, the drain of the twenty-third transistor P23 are respectively connected to the collector of the first bipolar transistor Q1 and the low mismatch The negative input terminal Vinn of the operational amplifier 100 .

The source of the twenty-fourth transistor P24 is connected to the power supply voltage VDD, and the drain of the twenty-fourth transistor P24 is respectively connected to the first end of the third resistor R3 and the low mismatch operational amplifier 100 The positive input terminal Vinp.

The source of the twenty-fifth transistor P25 is connected to the power supply voltage VDD. The drain of the twenty-fifth transistor P25 serves as the output terminal Vref of the bandgap reference circuit 200 , and the drain of the twenty-fifth transistor P25 is connected to the first end of the fourth resistor R4 .

A second end of the third resistor R3 is connected to the collector of the second bipolar transistor Q2.

A second end of the fourth resistor R4 is connected to the collector of the third bipolar transistor Q3.

The base of the first bipolar transistor Q1, the emitter of the first bipolar transistor Q1, the base of the second bipolar transistor Q2, the emitter of the second bipolar transistor Q2 The pole, the base of the third bipolar transistor Q3 and the emitter of the third bipolar transistor Q3 are all connected to the ground GND.

The bandgap reference circuit 200 uses the low-mismatch operational amplifier 100 , therefore, the bandgap reference circuit 200 has low mismatch of the operational amplifier.

It should be pointed out that the relevant transistors and resistors used in the present invention are commonly used components in the field, and the specific indicators and parameters corresponding to the components can be adjusted according to actual applications, and will not be described in detail here.

The embodiment of the utility model also provides a chip. The chip includes the low mismatch operational amplifier 100 .

Compared with the related art, the low-mismatch operational amplifier of the embodiment of the utility model sets the first resistor and the second resistor, and replaces the transistor of the operational amplifier of the related art through the first resistor and the second resistor, and respectively compares with the first resistor and the second resistor. The first resistor and the second resistor are connected to the device and the bias circuit for adjustment. The circuit effectively reduces the mismatch of the operational amplifier because the matching characteristic of the resistance is better than that of the transistor and the flexibility in the bias circuit. Therefore, the low mismatch operational amplifier, the bandgap reference circuit and the chip operational amplifier of the embodiment of the present invention have low mismatch.

It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the utility model rather than limit the scope of the utility model, those of ordinary skill in the art should understand that without departing from the spirit and scope of the utility model Any modifications or equivalent replacements made to the present utility model under the premise of the present utility model shall be covered within the scope of the present utility model. Furthermore, words appearing in the singular include the plural and vice versa unless the context otherwise requires. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.

Claims (7)

A low mismatch operational amplifier, characterized in that, the low mismatch operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor a transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first resistor, and a second resistor; The gate of the first transistor is connected to a first bias voltage, the source of the first transistor is connected to a power supply voltage, and the drain of the first transistor is respectively connected to the source of the second transistor and the the source of the third transistor; The gate of the second transistor is used as the negative input terminal of the low mismatch operational amplifier, and the drain of the second transistor is respectively connected to the source of the eleventh transistor and the first resistor of the second resistor. end; The gate of the third transistor is used as the positive input terminal of the low mismatch operational amplifier, and the drain of the third transistor is respectively connected to the source of the tenth transistor and the first end of the first resistor ; The source of the fourth transistor is connected to the power supply voltage, the drain of the fourth transistor is connected to the source of the sixth transistor, and the gate of the fourth transistor is respectively connected to the gate of the fifth transistor. Pole, the drain of the sixth transistor and the drain of the eighth transistor; The source of the fifth transistor is connected to a power supply voltage, and the drain of the fifth transistor is connected to the source of the seventh transistor; The gate of the sixth transistor is respectively connected to the gate of the seventh transistor and a second bias voltage; The drain of the seventh transistor is used as the output terminal of the low-mismatch operational amplifier, and the drain of the seventh transistor is connected to the drain of the ninth transistor; The gate of the eighth transistor is respectively connected to the gate of the ninth transistor and a third bias voltage, and the source of the eighth transistor is connected to the source of the tenth transistor; The source of the ninth transistor is connected to the source of the eleventh transistor; The gate of the tenth transistor is respectively connected to the gate of the eleventh transistor and a fourth bias voltage; Both the second end of the first resistor and the second end of the second resistor are connected to ground. The low mismatch operational amplifier according to claim 1, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor And the seventh transistor is a PMOS transistor, and the eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are all NMOS transistors. The low-mismatch operational amplifier according to claim 1, wherein the first resistor and the second resistor are parameter-adjustable resistors. A bandgap reference circuit, characterized in that the bandgap reference circuit comprises the low-mismatch operational amplifier according to any one of claims 1-3. The bandgap reference circuit according to claim 4, wherein the bandgap reference circuit further comprises a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor, a third resistor, a fourth resistor, a first bipolar transistor, a second bipolar transistor, and a third bipolar transistor; The source of the twenty-third transistor is connected to a power supply voltage, and the gate of the twenty-third transistor is respectively connected to the gate of the twenty-fourth transistor, the gate of the twenty-fifth transistor, and the gate of the twenty-fifth transistor. The output terminal of the low mismatch operational amplifier, the drain of the twenty-third transistor is respectively connected to the collector of the first bipolar transistor and the negative input terminal of the low mismatch operational amplifier; The source of the twenty-fourth transistor is connected to a power supply voltage, and the drain of the twenty-fourth transistor is respectively connected to the first end of the third resistor and the positive input end of the low mismatch operational amplifier; The source of the twenty-fifth transistor is connected to the power supply voltage; the drain of the twenty-fifth transistor is used as the output end of the bandgap reference circuit, and the drain of the twenty-fifth transistor is connected to the The first end of the fourth resistor; The second end of the third resistor is connected to the collector of the second bipolar transistor; The second end of the fourth resistor is connected to the collector of the third bipolar transistor; the base of the first bipolar transistor, the emitter of the first bipolar transistor, the base of the second bipolar transistor, the emitter of the second bipolar transistor, the Both the base of the third bipolar transistor and the emitter of the third bipolar transistor are connected to ground. The bandgap reference circuit according to claim 5, wherein the twenty-third transistor, the twenty-fourth transistor and the twenty-fifth transistor are all PMOS transistors. A chip, characterized in that the chip comprises the low-mismatch operational amplifier according to any one of claims 1-3.

Images