CN108233926A - A kind of hyperfrequency buffer input signal device - Google Patents

Abstract

A kind of hyperfrequency buffer input signal device, belongs to analogue layout field.The input signal of high quality is driven and provided the present invention provides powerful input signal, including host buffer circuit, secondary buffer circuit, operation amplifier circuit, capacitance coupling circuit and impedance matching circuit, secondary buffer circuit is that host buffer circuit replicates diminution generation, preferably minimum scale in proportion.Input signal is coupled to the drain terminal of source follower, avoids the channel modulation effect of short channel device, improved linearity of output signal by the present invention using source follower and capacitance；Main buffer uses open loop source follower, has the characteristics that unit gain and output impedance are low, reaches high bandwidth purpose；The output common mode of source follower changes with the variation of process corner and temperature, and the mode of Replica common-mode feedbacks is used to provide common mode for main buffer, realizes the stabilization of buffer output common mode.Present invention can apply to the buffer input signal devices of the time-interleaved ADC of ultrahigh speed.

Description

A UHF Input Signal Buffer

technical field

The invention relates to the field of analog integrated circuit design, specifically designs an ultra-high-frequency input signal buffer, which can be applied to an ultra-high-speed ADC input buffer.

Background technique

For low-speed ADCs, buffers may not be used, or closed-loop operational amplifiers may be used. For ultra-high-speed ADCs, if no buffer is used, the parasitic inductance of the package will deteriorate the quality of the input signal; and for open-loop operational amplifiers for high-speed and high-bandwidth applications, stability is difficult to guarantee. Directly inputting high-frequency input signals into the ADC chip will cause severe signal distortion and insufficient drive capability of the input signal. It is necessary to improve the drive capability of the input signal while ensuring better linearity. The input signal buffer is one of the most important modules. one. The buffer output is used for sample and hold (S/H) circuits and comparator circuits. Due to process angle and temperature changes, the output common mode of the source follower of the open-loop structure will drift, which will cause the input common mode of the comparator to drift. not working properly.

As the buffer of the analog-to-digital converter, the source follower has the characteristics of unity gain, and its output impedance is low. Combined with the sampling capacitor of the analog-to-digital converter, it can achieve the purpose of high bandwidth, drive large capacitive loads at the same time, and provide high-quality input signal.

Contents of the invention

In view of the problems mentioned above, the present invention proposes an ultra-high frequency input signal buffer for buffering input signals, increasing the drive capability of the input signal without damaging the signal, and is especially suitable for ultra-high-speed ADCs.

Technical scheme of the present invention is:

A UHF input signal buffer, comprising a main buffer circuit, a secondary buffer circuit, an operational amplifier circuit, a capacitive coupling circuit and an impedance matching circuit,

The secondary buffer circuit is generated by copying the main buffer circuit, and the overall size of the secondary buffer circuit is proportionally reduced to the overall size of the main buffer circuit;

The input end of the main buffer circuit is connected to the input signal after passing through the capacitive coupling circuit, and its output end is used as the output end of the UHF input signal buffer;

The positive input terminal of the operational amplifier circuit is connected to the reference voltage VREF, the negative input terminal is connected to the output terminal of the secondary buffer circuit, and the output terminal is connected to the input terminal of the secondary buffer circuit and passed through the impedance matching circuit. connected to the input of the main buffer circuit.

Specifically, the overall size of the secondary buffer circuit is the minimum ratio of the overall size of the main buffer circuit.

Specifically, the input signal is a differential signal, the main buffer circuit and the secondary buffer circuit are double-ended input and double-ended output, the operational amplifier circuit includes a first operational amplifier Amp1 and a second operational amplifier Amp2, and the capacitor The coupling circuit includes a first capacitor C1 and a second capacitor C2, and the impedance matching circuit includes a first resistor R1 and a second resistor R2,

The differential signal is respectively connected to the positive input terminal and the negative input terminal of the main buffer circuit through the first capacitor C1 and the second capacitor C2;

The first resistor R1 and the second resistor R2 are connected in series and in parallel between the positive input terminal and the negative input terminal of the main buffer circuit, and their series point is connected to the positive input terminal and the negative input terminal of the secondary buffer circuit And the output terminals of the first operational amplifier Amp1 and the second operational amplifier Amp2;

The positive input terminals of the first operational amplifier Amp1 and the second operational amplifier are connected to the reference voltage VREF, and their negative input terminals are respectively connected to the positive output terminal and the negative output terminal of the auxiliary buffer circuit.

Specifically, the main buffer circuit includes a first NMOS transistor NM1A, a second NMOS transistor NM1B, a third NMOS transistor NM2A, a fourth NMOS transistor NM2B, a third capacitor C1A, a fourth capacitor C1B, a third resistor R1A, a fourth resistor R1B, first current source I1A and second current source I1B,

The gate of the first NMOS transistor NM1A is used as the positive input terminal of the main buffer circuit and is connected to the gate of the third NMOS transistor NM2A after passing through the third capacitor C1A, and its drain is connected to the source of the third NMOS transistor NM2A, which The source is used as the positive output terminal of the main buffer circuit and grounded after passing through the first current source I1A; the drain of the third NMOS transistor NM2A is connected to the power supply voltage VDD, and its gate is connected to the drain after passing through the third resistor R1A;

The gate of the second NMOS transistor NM1B serves as the negative input terminal of the main buffer circuit and is connected to the gate of the fourth NMOS transistor NM2B after passing through the fourth capacitor C1B, and its drain is connected to the source of the fourth NMOS transistor NM2B, which The source serves as the negative output terminal of the main buffer circuit and is grounded after passing through the second current source I1B; the drain of the fourth NMOS transistor NM2B is connected to the power supply voltage VDD, and its gate is connected to the drain after passing through the fourth resistor R1B;

The first NMOS transistor NM1A, the second NMOS transistor NM1B, the third NMOS transistor NM2A and the fourth NMOS transistor NM2B are all deep N-well devices.

The beneficial effects of the present invention are:

1. The main buffer circuit adopts an open-loop source follower structure, the output impedance of the source follower is very small, and the bandwidth can be made large.

2. The common-mode level VCM at the input end of the main buffer circuit is generated by the common-mode feedback control of the replica buffer circuit. The replica buffer circuit is generated by replicating the main buffer circuit in proportion. The minimum ratio is preferred. The static operating point of the replica buffer circuit The same as the main buffer circuit and works in the DC state, the stability of the feedback loop can be guaranteed, and the buffer output common mode level VCM is stable.

3. In the main buffer circuit, the input signal is coupled to the drain of the source follower through the source follower and the capacitor, which avoids the channel modulation effect of the short channel device and improves the linearity of the output signal.

4. The NMOS transistors used in the main buffer circuit and the auxiliary buffer circuit all use deep N-well devices, and the substrate source is shorted to eliminate the influence of the substrate bias effect.

Description of drawings

FIG. 1 is a schematic structural diagram of a UHF input signal buffer proposed by the present invention.

FIG. 2 is a structural block diagram of an embodiment in which the input signal is a differential signal and applied to an ultra-high-speed ADC.

Fig. 3 is a schematic structural diagram of the main buffer circuit, the secondary buffer circuit and the impedance matching circuit in the embodiment.

Fig. 4 is a simulation diagram of -3dB bandwidth of a UHF input signal buffer proposed by the present invention.

FIG. 5 is a simulation result of the spurious-free dynamic range SFDR of a UHF input signal buffer proposed by the present invention changing with the frequency Fin of the input signal.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

An ultra-high frequency input signal buffer proposed by the invention provides powerful input signal drive, can drive large capacitive loads and provides high-quality input signals. The invention uses a source follower and a capacitor to couple the input signal to the drain of the source follower, avoiding the channel modulation effect of the short-channel device and improving the linearity of the output signal; the main buffer adopts an open-loop source follower, which has The characteristics of unity gain and low output impedance achieve the purpose of high bandwidth; the output common mode of the source follower changes with the change of process angle and temperature, and the common mode of the main buffer is provided by the way of Replica common mode feedback to realize the buffer output common-mode stability. The invention can be applied to an input signal buffer of an ultra-high-speed time-interleaved ADC.

As shown in Figure 1, it is a schematic structural diagram of a UHF input signal buffer proposed by the present invention, including a main buffer (Buffer) circuit, a secondary buffer (Replica Buffer) circuit, an operational amplifier circuit, a capacitive coupling circuit and an impedance matching circuit , the sub-buffer circuit is generated by duplicating the main buffer circuit, and the overall size of the sub-buffer circuit is reduced in proportion to the overall size of the main buffer circuit; the input terminal of the main buffer circuit is connected to the input signal after passing through the capacitive coupling circuit, and its output terminal is used as a UHF The output terminal of the input signal buffer; the positive input terminal of the operational amplifier circuit is connected to the reference voltage VREF, its negative input terminal is connected to the output terminal of the secondary buffer circuit, and its output terminal is connected to the input terminal of the secondary buffer circuit and passed through the impedance matching circuit. Connected to the input end of the main buffer circuit, the secondary buffer circuit provides the common mode level VCM to the main buffer circuit.

In the embodiment, the overall size of the secondary buffer circuit is the smallest ratio of the overall size of the main buffer circuit, and the number of tubes is reduced, so that the power consumption and chip area are reduced, achieving the optimal effect.

The present invention can also be applicable to the situation that the input signal is a differential signal, as shown in Figure 2, the main buffer circuit and the secondary buffer circuit are double-ended input and double-ended output, and the operational amplifier circuit includes the first operational amplifier Amp1 and the second operational amplifier Amp2, the capacitive coupling circuit includes the first capacitor C1 and the second capacitor C2, the impedance matching circuit includes the first resistor R1 and the second resistor R2, and the differential signal is respectively connected to the positive side of the main buffer circuit through the first capacitor C1 and the second capacitor C2 Input terminal (ie VP node) and negative input terminal (ie VN node); the first resistor R1 and the second resistor R2 are connected in series between the positive input terminal and the negative input terminal of the main buffer circuit, the series connection point Connect the positive input terminal and the negative input terminal of the secondary buffer circuit and the output terminals of the first operational amplifier Amp1 and the second operational amplifier Amp2; the positive input terminals of the first operational amplifier Amp1 and the second operational amplifier are connected to the reference voltage VREF, Their negative input terminals are respectively connected to the positive output terminal and the negative output terminal of the secondary buffer circuit.

Figure 3 is a schematic structural diagram of the main buffer circuit, the secondary buffer circuit and the impedance matching circuit in some embodiments, the main buffer circuit includes a first NMOS transistor NM1A, a second NMOS transistor NM1B, a third NMOS transistor NM2A, and a fourth NMOS transistor NM2B , the third capacitor C1A, the fourth capacitor C1B, the third resistor R1A, the fourth resistor R1B, the first current source I1A and the second current source I1B, the gate of the first NMOS transistor NM1A is used as the positive direction of the main buffer circuit The input terminal is connected to the gate of the third NMOS transistor NM2A after passing through the third capacitor C1A, and its drain is connected to the source of the third NMOS transistor NM2A, and its source is used as the positive output terminal of the main buffer circuit and passed through the first The current source I1A is then grounded; the drain of the third NMOS transistor NM2A is connected to the power supply voltage VDD, and its gate is connected to the drain after passing through the third resistor R1A; the second NMOS transistor NM1B, the fourth NMOS transistor NM2B, the fourth capacitor C1B, The fourth resistor R1B and the second current source I1B are formed by mirroring the first NMOS transistor NM1A, the third NMOS transistor NM2A, the third capacitor C1A, the third resistor R1A, and the first current source I1A, and the gate of the second NMOS transistor NM1B Serve as the negative input terminal of the main buffer circuit and connect to the gate of the fourth NMOS transistor NM2B after passing through the fourth capacitor C1B, its drain is connected to the source of the fourth NMOS transistor NM2B, and its source serves as the main buffer circuit The negative output end of the NMOS transistor NM2B is grounded after passing through the second current source I1B; the drain of the fourth NMOS transistor NM2B is connected to the power supply voltage VDD, and the gate thereof is connected to the drain after passing through the fourth resistor R1B.

The secondary buffer circuit includes fifth NMOS transistor NM3A, sixth NMOS transistor NM3B, seventh NMOS transistor NM4A, eighth NMOS transistor NM4B, fifth capacitor C2A, sixth capacitor C2B, fifth resistor R2A, sixth resistor R2B, third The current source I2A and the fourth current source I2B, the gate of the fifth NMOS transistor NM3A is used as the positive input terminal of the secondary buffer circuit and is connected to the gate of the seventh NMOS transistor NM4A after passing through the fifth capacitor C2A, and its drain is connected to the seventh NMOS transistor NM4A. The source of the NMOS transistor NM4A is used as the positive output terminal of the secondary buffer circuit and grounded after passing through the third current source I2A; the drain of the seventh NMOS transistor NM4A is connected to the power supply voltage VDD, and its gate passes through the fifth resistor R2A Then connect its drain; the gate of the sixth NMOS transistor NM3B is used as the negative input terminal of the secondary buffer circuit and is connected to the gate of the eighth NMOS transistor NM4B after passing through the sixth capacitor C2B, and its drain is connected to the gate of the eighth NMOS transistor NM4B The source, its source is used as the negative output terminal of the secondary buffer circuit and grounded after passing through the fourth current source I2B; the drain of the eighth NMOS transistor NM4B is connected to the power supply voltage VDD, and its gate is connected to its drain after passing through the sixth resistor R2B pole. The positive input end of the first operational amplifier Amp1 is connected to the reference voltage VREF, its negative input end is connected to the source electrode of the fifth NMOS transistor NM3A, and its output end is connected to the gate of the fifth NMOS transistor NM3A; the positive input end of the second operational amplifier Amp2 Connect the reference voltage VREF to the input terminal, its negative input terminal is connected to the source of the sixth NMOS transistor NM3B, its output terminal is connected to the gate of the sixth NMOS transistor NM3B, the output terminals of the first operational amplifier Amp1 and the second operational amplifier Amp2 The positive and negative input terminals of the main buffer circuit are respectively connected to the positive input terminal and the negative input terminal of the main buffer circuit through the first resistor R1 and the second resistor R2 in the impedance matching circuit to provide a common mode bias voltage for the main buffer circuit.

In the main buffer circuit, the first NMOS transistor NM1A, the second NMOS transistor NM1B, the third NMOS transistor NM2A, and the fourth NMOS transistor NM2B constitute the main input pair of the source follower, the secondary buffer circuit, the fifth NMOS transistor NM3A, the sixth The NMOS transistor NM3B, the seventh NMOS transistor NM4A and the eighth NMOS transistor NM4B constitute the main input pair of the source follower. In order to solve the non-ideal factors of the traditional source follower, the NMOS transistors in the main buffer circuit and the auxiliary buffer circuit are both For deep N-well devices, the influence of substrate bias effect is eliminated. The main buffer circuit adopts an open-loop source follower structure, the output impedance of the source follower is very small, and the bandwidth can be made very large.

In the main buffer circuit, the input signal is coupled to the node N1A (that is, the source end of the third NMOS transistor NM2A) and the node N1B (that is, the The source terminal of the fourth NMOS transistor NM2B), so that the drain-source voltage of the first NMOS transistor NM1A is constant, and the drain-source voltage of the third NMOS transistor NM1B is also constant, which reduces the influence of the channel modulation effect and improves the linearity .

In order to overcome the change of the output common mode with temperature and process, the present invention proposes the Replica Buffer common mode feedback mode, that is, the secondary buffer circuit, which provides the common mode voltage VCM to the main buffer (Buffer) circuit, and replicates the main buffer circuit in proportion to obtain the secondary buffer circuit. The buffer (Replica Buffer) circuit is used for common-mode feedback, then the static operating points of the main buffer circuit and the secondary buffer circuit are the same, and the secondary buffer circuit works in the DC state, the stability can be well satisfied, and the power consumption is also low. Through the use of common-mode feedback, the problem of output common-mode changes due to process angle and temperature changes is solved, and the comparator in the subsequent analog-to-digital converter can work normally.

In this embodiment, the ultra-high-frequency input signal buffer proposed by the present invention is applied to an ultra-high-speed ADC. As shown in FIG. 2, the first capacitor C1 and the second capacitor C2 are connected in series outside the ultra-high-speed ADC chip, and the main buffer circuit , sub-buffer circuit, impedance matching circuit and operational amplifier circuit are integrated in the ultra-high-speed ADC chip; this embodiment adopts an open-loop source follower structure to improve the buffer bandwidth; the source follower output common mode of the open-loop structure will shift , the common mode of the main buffer is provided by the way of Replica common mode feedback to realize the stability of the output common mode of the buffer; in the main buffer circuit, the stacked source follower and capacitor are used to couple the input signal to the source follower The drain terminal avoids the channel modulation effect of short channel devices. The source-follower input halls all use deep N-well devices, which eliminates the substrate bias effect. There are only MOS transistors, capacitor CAP and resistor R in this circuit, and the process is simple to realize. The invention is suitable for the input signal buffer structure of the semiconductor integrated circuit, especially when the frequency of the input signal is very high, and solves the problems of increasing the drive of the input signal, improving the linearity of the input signal, and improving the stability of the open-loop output common-mode voltage. The simulation results of this embodiment are shown in Figure 4 and Figure 5, for the input signal buffer applied to the ultra-high speed ADC, the -3dB bandwidth is 12GHz; when the load is 1.5pF, the input signal frequency is 1.5GHz, When Vpp is 800mV, the spurious-free dynamic range SFDR is 75.91dB, which is suitable for 12bit ultra-high-speed ADC design requirements.

The above example is only a preferred example of the present invention, and the use of the present invention is not limited to this example. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the present invention. within the scope of protection.

Claims (4)

1. a kind of ultra-high frequency input signal buffer is characterized in that, comprises main buffer circuit, secondary buffer circuit, operational amplifier circuit, capacitive coupling circuit and impedance matching circuit, The secondary buffer circuit is generated by copying the main buffer circuit, and the overall size of the secondary buffer circuit is proportionally reduced to the overall size of the main buffer circuit; The input end of the main buffer circuit is connected to the input signal after passing through the capacitive coupling circuit, and its output end is used as the output end of the UHF input signal buffer; The positive input terminal of the operational amplifier circuit is connected to the reference voltage (VREF), the negative input terminal is connected to the output terminal of the secondary buffer circuit, and the output terminal is connected to the input terminal of the secondary buffer circuit and passed through the impedance matching connected to the input of the main buffer circuit after the circuit. 2 . The UHF input signal buffer according to claim 1 , wherein the overall size of the secondary buffer circuit is the smallest ratio of the overall size of the main buffer circuit. 3. according to claim 1 and 2 described ultra-high frequency input signal buffers, it is characterized in that, described input signal is a differential signal, and described main buffer circuit and secondary buffer circuit are double-ended input and double-ended output, so The operational amplifier circuit includes a first operational amplifier (Amp1) and a second operational amplifier (Amp2), the capacitive coupling circuit includes a first capacitor (C1) and a second capacitor (C2), and the impedance matching circuit includes a first resistor (R1) and a second resistor (R2), The differential signal is respectively connected to the positive input terminal and the negative input terminal of the main buffer circuit through the first capacitor (C1) and the second capacitor (C2); The first resistor (R1) and the second resistor (R2) are connected in series and parallel between the positive input terminal and the negative input terminal of the main buffer circuit, and the series point is connected to the positive input terminal and the negative input terminal of the secondary buffer circuit. Negative input and outputs of the first operational amplifier (Amp1) and the second operational amplifier (Amp2); The positive input terminals of the first operational amplifier (Amp1) and the second operational amplifier are connected to the reference voltage (VREF), and their negative input terminals are respectively connected to the positive output terminal and the negative output terminal of the auxiliary buffer circuit. 4. The UHF input signal buffer according to claim 3, wherein the main buffer circuit comprises a first NMOS transistor (NM1A), a second NMOS transistor (NM1B), and a third NMOS transistor (NM2A) , the fourth NMOS transistor (NM2B), the third capacitor (C1A), the fourth capacitor (C1B), the third resistor (R1A), the fourth resistor (R1B), the first current source (I1A) and the second current source ( I1B), The gate of the first NMOS transistor (NM1A) is used as the positive input terminal of the main buffer circuit and is connected to the gate of the third NMOS transistor (NM2A) after passing through the third capacitor (C1A), and its drain is connected to the third NMOS transistor The source of (NM2A), its source is used as the positive output terminal of the main buffer circuit and grounded after passing through the first current source (I1A); the drain of the third NMOS transistor (NM2A) is connected to the power supply voltage (VDD), Its gate is connected to its drain after passing through the third resistor (R1A); The gate of the second NMOS transistor (NM1B) is used as the negative input terminal of the main buffer circuit and is connected to the gate of the fourth NMOS transistor (NM2B) after passing through the fourth capacitor (C1B), and its drain is connected to the fourth NMOS transistor The source of (NM2B), its source is used as the negative output terminal of the main buffer circuit and grounded after passing through the second current source (I1B); the drain of the fourth NMOS transistor (NM2B) is connected to the power supply voltage (VDD), Its gate is connected to its drain after passing through the fourth resistor (R1B); The first NMOS transistor (NM1A), the second NMOS transistor (NM1B), the third NMOS transistor (NM2A) and the fourth NMOS transistor (NM2B) are deep N-well devices.