CN116015217A - Broadband low-power-consumption transconductance operational amplifier with enhanced slew rate - Google Patents

Abstract

The invention discloses a broadband low-power transconductance operational amplifier with enhanced slew rate, which comprises an improved loop-folded transconductance operational amplifier and a slew rate enhanced circuit. The slew rate enhanced circuit can significantly Improve the positive and negative slew rate, and during the small-signal operation of the amplifier, its transistors work in the sub-threshold region and consume almost no current, so the unit of the amplifier can be increased while maintaining low power consumption gain bandwidth and slew rate, thereby increasing the operating speed and output current capability of the operational amplifier. The embodiment of the invention improves the working speed of the high-performance switched capacitor circuit, reduces power consumption, is easy to popularize and use, and can be widely used in the technical field of operational amplifiers.

Description

A Broadband Low Power Transconductance Operational Amplifier with Enhanced Slew Rate

technical field

The invention relates to the technical field of operational amplifiers, in particular to a wideband low-power transconductance operational amplifier with enhanced slew rate.

Background technique

Transconductance operational amplifier is one of the most important circuit units in analog circuits, and is widely used in analog circuits and mixed signal processing circuits, such as switched capacitors, analog-to-digital/digital-to-analog converters, etc. Transconductance operational amplifiers usually determine the power consumption, accuracy, speed and other indicators that high-performance switched capacitor circuits can achieve. In switched capacitor circuits, the load is usually a pure capacitive load. At this time, a single-stage operational transconductance amplifier is better than a multi-stage operational amplifier, so the traditional folded transconductance amplifier has been widely used.

The working category of the traditional folded transconductance amplifier belongs to class A, the current efficiency is low, and it has the disadvantages of slow speed and high power consumption. Design requirements for high slew rate and wide bandwidth transconductance operational amplifiers. In order to improve the current efficiency of the operational transconductance amplifier, it is necessary to improve the traditional folded cascode amplifier, so the circular folded transconductance operational amplifier is proposed, which uses the current multiplexing technology to improve the current efficiency of the operational amplifier. However, the existing loop-folded transconductance operational amplifier has a limited increase in the slew rate under the condition of limited power consumption, and the positive and negative slew rates are not equal, and its maximum output current is limited.

Contents of the invention

The purpose of the present invention is to solve one of the technical problems in the prior art at least to a certain extent.

Therefore, an object of the embodiments of the present invention is to provide a wideband low-power transconductance operational amplifier with enhanced slew rate, which can improve the unity gain bandwidth and slew rate of the amplifier while maintaining low power consumption, thereby In order to improve the operating speed and output current capability of the operational amplifier.

In order to achieve the above technical objectives, the technical solutions adopted in the embodiments of the present invention include:

An embodiment of the present invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, including an improved cycle-folded transconductance operational amplifier and a slew rate enhancement circuit, and the improved cycle-folded transconductance operational amplifier includes the first Three PMOS transistors, eighth PMOS transistors, first NMOS transistors, fourth PMOS transistors, ninth PMOS transistors, tenth PMOS transistors, eleventh PMOS transistors, twelfth PMOS transistors, fifth PMOS transistors, thirteenth PMOS transistors tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, The fourteenth NMOS transistor and the fifteenth NMOS transistor, the slew rate enhancement circuit includes a first PMOS transistor, a second PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a sixth PMOS transistor, The seventh PMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor, wherein:

Sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor Both poles are connected to the analog positive power supply, the gates of the first PMOS transistor and the second PMOS transistor are connected to the drain of the seventh NMOS transistor, and the drain of the second PMOS transistor is connected to the differential output negative Terminal, the drain of the seventeenth NMOS transistor, the drain of the eighth PMOS transistor, and the drain of the first NMOS transistor are connected, and the gate of the third PMOS transistor is connected to the common-mode feedback voltage, so The drain of the third PMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the eighth PMOS transistor is connected to the P-type first bias voltage, and the drain of the fourth PMOS transistor is connected to the source of the eighth PMOS transistor. The sources of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor are connected, and the gate of the fourth PMOS transistor is connected to a P-type second bias voltage, The gate of the fifth PMOS transistor is connected to the common-mode feedback voltage, the drain of the fifth PMOS transistor is connected to the source of the thirteenth PMOS transistor, and the sixth PMOS transistor and the seventh PMOS transistor are connected to the source of the thirteenth PMOS transistor. The gates of the PMOS transistors are all connected to the drain of the eighteenth NMOS transistor, the drain of the sixth PMOS transistor is connected to the positive terminal of the differential output, the drain of the eighth NMOS transistor, the drain of the thirteenth PMOS transistor The drain of the transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, and the drain of the ninth NMOS transistor. The drain of the PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected, and the gate of the first NMOS transistor is connected to the first NMOS transistor. Type bias voltage, the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor are connected to the positive terminal of the differential input, the drain of the tenth PMOS transistor is connected to the drain of the fifth NMOS transistor electrode, the drain of the sixth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor, and the drain of the eleventh PMOS transistor is connected to the third The drain of the NMOS transistor, the drain of the fourth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected, and the gate of the eleventh PMOS transistor is connected to the gate of the eleventh NMOS transistor. The gate of the twelfth PMOS transistor is connected to the negative terminal of the differential input, the gate of the thirteenth PMOS transistor is connected to the P-type first bias voltage, and the source of the second NMOS transistor is connected to the negative terminal of the differential input. The drain of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the sixteenth NMOS transistor, the seventeenth NMOS transistor The gate of the eighteenth NMOS transistor is connected to the gate, the gate of the second NMOS transistor is connected to the first N-type bias voltage, and the source of the third NMOS transistor is connected to the tenth NMOS transistor. The drain of an NMOS transistor is connected, the source of the fourth NMOS transistor is connected to the drain of the twelfth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the thirteenth NMOS transistor connected, the source of the sixth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor The gates of the transistors are connected to the first N-type bias voltage, the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor are connected to the second N-type bias voltage, and the seventh NMOS transistor , the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the tenth NMOS transistor The sources of the four NMOS transistors, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor and the eighteenth NMOS transistor are all connected to analog ground.

Further, in an embodiment of the present invention, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the first Six NMOS transistors, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the Substrates of the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are all compatible with The analog ground is connected, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the The seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor The substrates are all connected to the analog positive power supply.

Further, in an embodiment of the present invention, the potential of the analog ground is 0V, and the potential of the analog positive power supply is 3.3V.

Further, in an embodiment of the present invention, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor have the same transistor size, and the third PMOS transistor The NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor and the sixth NMOS transistor have the same transistor size.

Further, in an embodiment of the present invention, the ratio of transistor sizes of the ninth NMOS transistor, the eighth NMOS transistor, and the seventh NMOS transistor is 1:m:n, and the sixteenth NMOS transistor transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor have a transistor size ratio of 1:m:n, n=m+2.5, and the ninth NMOS transistor and the sixteenth NMOS transistor The transistors are the same size.

Further, in an embodiment of the present invention, transistor sizes of the first PMOS transistor, the second PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor are the same.

Further, in an embodiment of the present invention, the ratio of transistor sizes of the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor is 6:1:1, and the tenth NMOS transistor The ratio of the transistor size of the fifth NMOS transistor, the fourteenth NMOS transistor, and the thirteenth NMOS transistor is 6:1:1, and the transistor size of the twelfth NMOS transistor and the fifteenth NMOS transistor are the same .

Further, in an embodiment of the present invention, the common-mode feedback voltage is generated by a switched capacitor type common-mode feedback circuit.

Advantage of the present invention and beneficial effect will be provided in part in the following description, part will become apparent from the following description, or understand by practice of the present invention:

An embodiment of the present invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, including an improved loop-folded transconductance operational amplifier and a slew rate enhanced circuit, and the slew rate enhanced circuit is used during the large signal operation of the amplifier. It can significantly improve the positive and negative slew rate, and during the small-signal operation of the amplifier, its transistors work in the sub-threshold region and consume almost no current, so the amplifier can be improved while maintaining low power consumption. Unity gain bandwidth and slew rate, thereby improving the operating speed and output current capability of the operational amplifier; the embodiment of the invention improves the operating speed of the high-performance switched capacitor circuit, reduces power consumption, and is easy to popularize and use.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings that need to be used in the embodiments of the present invention are described below. It should be understood that the accompanying drawings in the following introductions are only for the convenience of clearly expressing the technology of the present invention For some embodiments in the solution, those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a broadband low-power transconductance operational amplifier with enhanced slew rate provided by an embodiment of the present invention.

Reference signs:

P1 to P13 represent the first to thirteenth PMOS transistors; N1 to N18 represent the first to eighteenth NMOS transistors; AVDD represents the analog positive power supply; AVSS represents the analog ground; Vbp1 represents the first P-type bias voltage; Vbp2 Indicates the P-type second bias voltage; Vbn1 indicates the N-type first bias voltage; Vbn2 indicates the N-type second bias voltage; Vo+ indicates the positive terminal of the differential output; Vo- indicates the negative terminal of the differential output; Vin+ indicates the positive terminal of the differential input ; Vin- represents the negative terminal of the differential input; Vcmfb represents the common-mode feedback voltage.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

In the description of the present invention, multiple means two or more. If the first and the second are described only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance or implying Indicate the number of indicated technical features or implicitly indicate the sequence of indicated technical features. Also, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Referring to FIG. 1 , an embodiment of the present invention provides a broadband low-power transconductance operational amplifier with enhanced slew rate, including an improved loop-folded transconductance operational amplifier (as shown in the area outside the dashed box in FIG. 1 ) and a slew rate enhancement circuit (as shown in the area within the dotted line box in Figure 1), the improved loop-folding transconductance operational amplifier includes a third PMOS transistor (P3), an eighth PMOS transistor (P8), a first NMOS transistor (N1), a Four PMOS transistors (P4), ninth PMOS transistors (P9), tenth PMOS transistors (P10), eleventh PMOS transistors (P11), twelfth PMOS transistors (P12), fifth PMOS transistors (P5), and Thirteen PMOS transistors (P13), second NMOS transistors (N2), third NMOS transistors (N3), fourth NMOS transistors (N4), fifth NMOS transistors (N5), sixth NMOS transistors (N6), tenth NMOS tube (N10), eleventh NMOS tube (N11), twelfth NMOS tube (N12), thirteenth NMOS tube (N13), fourteenth NMOS tube (N14) and fifteenth NMOS tube (N15) , The slew rate enhancement circuit includes a first PMOS transistor (P1), a second PMOS transistor (P2), a seventh NMOS transistor (N7), an eighth NMOS transistor (N8), a ninth NMOS transistor (N9), a sixth PMOS transistor tube (P6), seventh PMOS tube (P7), sixteenth NMOS tube (N16), seventeenth NMOS tube (N17) and eighteenth NMOS tube (N18), wherein:

The first PMOS transistor (P1), the second PMOS transistor (P2), the third PMOS transistor (P3), the fourth PMOS transistor (P4), the fifth PMOS transistor (P5), the sixth PMOS transistor (P6) and the seventh The sources of the PMOS transistors (P7) are connected to the analog positive power supply (AVDD), the gates of the first PMOS transistor (P1) and the second PMOS transistor (P2) are connected to the drain of the seventh NMOS transistor (N7), The drain of the second PMOS transistor (P2) and the differential output negative terminal (Vo-), the drain of the seventeenth NMOS transistor (N17), the drain of the eighth PMOS transistor (P8), and the first NMOS transistor (N1) The drain of the third PMOS transistor (P3) is connected to the common mode feedback voltage (Vcmfb), the drain of the third PMOS transistor (P3) is connected to the source of the eighth PMOS transistor (P8), and the eighth PMOS transistor (P8) The gate of the transistor (P8) is connected to the P-type first bias voltage (Vbp1), and the drain of the fourth PMOS transistor (P4) is connected to the ninth PMOS transistor (P9), the tenth PMOS transistor (P10), and the eleventh PMOS transistor. The source of the twelfth PMOS transistor (P11) and the twelfth PMOS transistor (P12) are connected, the gate of the fourth PMOS transistor (P4) is connected to the P-type second bias voltage (Vbp2), and the gate of the fifth PMOS transistor (P5) Connect the common mode feedback voltage (Vcmfb), the drain of the fifth PMOS transistor (P5) is connected to the source of the thirteenth PMOS transistor (P13), the sixth PMOS transistor (P6), and the seventh PMOS transistor (P7) The gates are all connected to the drain of the eighteenth NMOS transistor (N18), the drain of the sixth PMOS transistor (P6) is connected to the differential output positive terminal (Vo+), the drain of the eighth NMOS transistor (N8), and the drain of the thirteenth NMOS transistor (N8). The drain of the PMOS transistor (P13) is connected to the drain of the second NMOS transistor (N2), the source of the first NMOS transistor (N1) is connected to the drain of the ninth NMOS transistor (N9), the tenth NMOS transistor (N10) The drain of the ninth PMOS transistor (P9), the gates of the seventh to ninth NMOS transistors (N7, N8, N9) are connected, and the gate of the first NMOS transistor (N1) is connected to the first N-type bias Set the voltage (Vbn1), the gate of the ninth PMOS transistor (P9) and the gate of the tenth PMOS transistor (P10) are connected to the differential input positive terminal (Vin+), the drain of the tenth PMOS transistor (P10) is connected to the fifth The drain of the NMOS transistor (N5), the drain of the sixth NMOS transistor (N6), the gate of the fourteenth NMOS transistor (N14) and the gate of the fifteenth NMOS transistor (N15) are connected, and the eleventh PMOS transistor The drain of (P11) and the drain of the third NMOS transistor (N3), the drain of the fourth NMOS transistor (N4), the gate of the tenth NMOS transistor (N10) and the gate of the eleventh NMOS transistor (N11) The gates of the eleventh PMOS transistor (P11) and the gate of the twelfth PMOS transistor (P12) are connected to the differential input negative terminal (Vin-), and the gate of the thirteenth PMOS transistor (P13) is connected to P type first bias voltage (Vbp1), the source of the second NMOS transistor (N2), the drain of the fifteenth NMOS transistor (N15), the drain of the sixteenth NMOS transistor (N16), the twelfth PMOS transistor The drain of (P12) is connected to the gates of the sixteenth to eighteenth NMOS transistors (N16, N17, N18), and the gate of the second NMOS transistor (N2) is connected to the first N-type bias voltage (Vbn1), The source of the third NMOS transistor (N3) is connected to the drain of the eleventh NMOS transistor (N11), the source of the fourth NMOS transistor (N4) is connected to the drain of the twelfth NMOS transistor (N12), and the fifth The source of the NMOS transistor (N5) is connected to the drain of the thirteenth NMOS transistor (N13), the source of the sixth NMOS transistor (N6) is connected to the drain of the fourteenth NMOS transistor (N14), and the third to sixth The gates of the NMOS transistors (N3, N4, N5, N6) are connected to the first N-type bias voltage (Vbn1), and the gates of the twelfth NMOS transistor (N12) and the thirteenth NMOS transistor (N13) are connected to the second N-type bias voltage, seventh NMOS transistor (N7), eighth NMOS transistor (N8), ninth NMOS transistor (N9), tenth NMOS transistor (N10), eleventh NMOS transistor (N11), twelfth NMOS transistor NMOS tube (N12), thirteenth NMOS tube (N13), fourteenth NMOS tube (N14), fifteenth NMOS tube (N15), sixteenth NMOS tube (N16), seventeenth NMOS tube (N17) And the source of the eighteenth NMOS transistor (N18) is connected to the analog ground (AVSS).

Further as an optional implementation manner, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor NMOS tubes, tenth NMOS tubes, eleventh NMOS tubes, twelfth NMOS tubes, thirteenth NMOS tubes, fourteenth NMOS tubes, fifteenth NMOS tubes, sixteenth NMOS tubes, seventeenth NMOS tubes, and The substrates of the eighteenth NMOS transistors (N1 to N18) are all connected to the analog ground (AVSS), and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor The substrates of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor and the thirteenth PMOS transistor (P1 to P13) are all related to the analog Connect to the positive supply (AVDD).

As a further optional implementation manner, the potential of the analog ground (AVSS) is 0V, and the potential of the analog positive power supply (AVDD) is 3.3V.

Further as an optional implementation manner, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor (P9 to P12) have the same transistor size, and the third NMOS transistor, the fourth NMOS transistor, the The transistor sizes of the fifth NMOS transistor and the sixth NMOS transistor (N3 to N6) are the same.

Further as an optional implementation manner, the ratio of transistor sizes of the ninth NMOS transistor (N9), the eighth NMOS transistor (N8) and the seventh NMOS transistor (N7) is 1:m:n, and the sixteenth NMOS transistor (N16 ), the ratio of transistor size of the seventeenth NMOS transistor (N17) and the eighteenth NMOS transistor (N18) is 1:m:n, n=m+2.5, the ninth NMOS transistor (N9) and the sixteenth NMOS transistor (N16) has the same transistor size.

As a further optional implementation manner, the transistor sizes of the first PMOS transistor (P1), the second PMOS transistor (P2), the sixth PMOS transistor (P6) and the seventh PMOS transistor (P7) are the same.

Further as an optional implementation manner, the ratio of transistor sizes of the tenth NMOS transistor (N10), the eleventh NMOS transistor (N11), and the twelfth NMOS transistor (N12) is 6:1:1, and the fifteenth NMOS transistor (N15), the fourteenth NMOS transistor (N14), the thirteenth NMOS transistor (N13) have a transistor size ratio of 6:1:1, the twelfth NMOS transistor (N12) and the fifteenth NMOS transistor (N15) The transistors are the same size.

As a further optional implementation manner, the common-mode feedback voltage (Vcmfb) is generated by a switched capacitor common-mode feedback circuit.

In the embodiment of the present invention, the direct current may flow through the tenth NMOS transistor (N10), the eleventh NMOS transistor (N11), the twelfth NMOS transistor (N12), the thirteenth NMOS transistor (N13), the fourteenth NMOS transistor tube (N14) and the fifteenth NMOS tube (N15), and almost no AC current flows through the fourth NMOS tube (N4), the fifth NMOS tube (N5), the twelfth NMOS tube (N12), the thirteenth NMOS tube tube (N13) as they exhibit high impedance to AC signals. Assuming that the transconductance of the ninth PMOS transistor ( P9 ) is gm, then through the above proportional control, the final transconductance of the operational amplifier in this embodiment is Gm1=7*gm. If the input transistor of the traditional folded transconductance amplifier is twice the size of P9 as a comparison, then its transconductance is Gm2=2*gm. It shows that the transconductance of the amplifier in this embodiment is 3.5 times that of the traditional folded transconductance amplifier, which will significantly improve the bandwidth of the amplifier.

Meanwhile, the positive slew rate SR ⁺ of the op amp can be expressed as:

SR ⁺ ＝(1+n)*I _b /C _L

Wherein, I _b is half of the current passing through the fourth PMOS transistor (P4), and _CL is the magnitude of the load capacitance connected to the two output terminals of the amplifier respectively.

The negative slew rate SR- of the operational amplifier can be expressed as:

SR ^- ＝(m+3.5)*I _b /C _L

It can be seen that in this embodiment, the slew rate of the amplifier can be adjusted by changing the value of m. In order to make the positive slew rate and negative slew rate of the operational amplifier as close as possible, the embodiment of the present invention takes n=m+2.5. At this time, the total slew rate SR of the operational amplifier can be expressed as:

SR＝(2m+7)*I _b /C _L

In the present embodiment, m=5 is taken, and SPICE simulation is carried out on the CADENCE platform. The simulation results show that, when the load capacitance CL=40pF is respectively connected at both ends of the output, under a total bias current of 400 μA (including the current of the bias circuit), The unity gain bandwidth is 15.4MHz, the DC gain is 87.8dB, the positive slew rate is 15.5V·μs^(-1), the negative slew rate is 15.4V·μs^(-1), and the total slew rate is 30.9V ·μs^(-1), the phase margin is 44°.

It can be recognized that after adopting the embodiment of the present invention, by carefully designing the size of each branch transistor, compared with the traditional transconductance amplifier, the current of each branch is more fully utilized, and by designing the slew rate enhancement circuit, It can significantly increase the positive and negative slew rate during the large-signal operation of the amplifier, and its transistor works in the sub-threshold region during the small-signal operation of the amplifier, which consumes almost no current, further improving the unity-gain bandwidth and slew rate of the amplifier , thereby improving the operating speed and output current capability of the operational amplifier, high reliability, and broad application prospects.

The slew rate enhancement circuit of the embodiment of the present invention can significantly increase the positive and negative slew rates during the large-signal operation of the amplifier, and its transistors work in the sub-threshold region during the small-signal operation of the amplifier, almost no Therefore, the unity gain bandwidth and slew rate of the amplifier can be improved while maintaining low power consumption, thereby improving the operating speed and output current capability of the operational amplifier; the embodiment of the present invention improves the performance of the high-performance switched capacitor circuit. The working speed reduces power consumption and is easy to popularize and use.

In the above description of this specification, the description with reference to the terms "one embodiment/example", "another embodiment/example" or "some embodiments/example" means that the description is described in conjunction with the embodiment or example. A particular feature, structure, material, or characteristic is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. Equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (8)

1. A broadband low-power transconductance operational amplifier with enhanced slew rate is characterized in that it includes an improved loop-folded transconductance operational amplifier and a slew rate enhancement circuit, and the improved loop-folded transconductance operational amplifier includes the first Three PMOS transistors, eighth PMOS transistors, first NMOS transistors, fourth PMOS transistors, ninth PMOS transistors, tenth PMOS transistors, eleventh PMOS transistors, twelfth PMOS transistors, fifth PMOS transistors, thirteenth PMOS transistors tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube, the thirteenth NMOS tube, The fourteenth NMOS transistor and the fifteenth NMOS transistor, the slew rate enhancement circuit includes a first PMOS transistor, a second PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a sixth PMOS transistor, The seventh PMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor, wherein: Sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, and the seventh PMOS transistor Both poles are connected to the analog positive power supply, the gates of the first PMOS transistor and the second PMOS transistor are connected to the drain of the seventh NMOS transistor, and the drain of the second PMOS transistor is connected to the differential output negative Terminal, the drain of the seventeenth NMOS transistor, the drain of the eighth PMOS transistor, and the drain of the first NMOS transistor are connected, and the gate of the third PMOS transistor is connected to the common-mode feedback voltage, so The drain of the third PMOS transistor is connected to the source of the eighth PMOS transistor, the gate of the eighth PMOS transistor is connected to the P-type first bias voltage, and the drain of the fourth PMOS transistor is connected to the source of the eighth PMOS transistor. The sources of the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor are connected, and the gate of the fourth PMOS transistor is connected to a P-type second bias voltage, The gate of the fifth PMOS transistor is connected to the common-mode feedback voltage, the drain of the fifth PMOS transistor is connected to the source of the thirteenth PMOS transistor, and the sixth PMOS transistor and the seventh PMOS transistor are connected to the source of the thirteenth PMOS transistor. The gates of the PMOS transistors are all connected to the drain of the eighteenth NMOS transistor, the drain of the sixth PMOS transistor is connected to the positive terminal of the differential output, the drain of the eighth NMOS transistor, the drain of the thirteenth PMOS transistor The drain of the transistor is connected to the drain of the second NMOS transistor, the source of the first NMOS transistor is connected to the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, and the drain of the ninth NMOS transistor. The drain of the PMOS transistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected, and the gate of the first NMOS transistor is connected to the first NMOS transistor. Type bias voltage, the gate of the ninth PMOS transistor and the gate of the tenth PMOS transistor are connected to the positive terminal of the differential input, the drain of the tenth PMOS transistor is connected to the drain of the fifth NMOS transistor electrode, the drain of the sixth NMOS transistor, the gate of the fourteenth NMOS transistor, and the gate of the fifteenth NMOS transistor, and the drain of the eleventh PMOS transistor is connected to the third The drain of the NMOS transistor, the drain of the fourth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected, and the gate of the eleventh PMOS transistor is connected to the gate of the eleventh NMOS transistor. The gate of the twelfth PMOS transistor is connected to the negative terminal of the differential input, the gate of the thirteenth PMOS transistor is connected to the P-type first bias voltage, and the source of the second NMOS transistor is connected to the negative terminal of the differential input. The drain of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the sixteenth NMOS transistor, the seventeenth NMOS transistor The gate of the eighteenth NMOS transistor is connected to the gate, the gate of the second NMOS transistor is connected to the first N-type bias voltage, and the source of the third NMOS transistor is connected to the tenth NMOS transistor. The drain of an NMOS transistor is connected, the source of the fourth NMOS transistor is connected to the drain of the twelfth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the thirteenth NMOS transistor connected, the source of the sixth NMOS transistor is connected to the drain of the fourteenth NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor The gates of the transistors are connected to the first N-type bias voltage, the gates of the twelfth NMOS transistor and the thirteenth NMOS transistor are connected to the second N-type bias voltage, and the seventh NMOS transistor , the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the tenth NMOS transistor The sources of the four NMOS transistors, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor and the eighteenth NMOS transistor are all connected to analog ground. 2. A kind of slew rate enhanced broadband low-power transconductance operational amplifier according to claim 1, characterized in that: said first NMOS transistor, said second NMOS transistor, said third NMOS transistor, The fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the The eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the Substrates of the seventeenth NMOS transistor and the eighteenth NMOS transistor are connected to the analog ground, and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor , the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, and the eleventh PMOS transistor , the substrates of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected to the analog positive power supply. 3. A kind of slew rate enhanced broadband low-power transconductance operational amplifier according to claim 2, characterized in that: the potential of the analog ground is 0V, and the potential of the analog positive power supply is 3.3V. 4. The wideband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: the ninth PMOS transistor, the tenth PMOS transistor, and the eleventh PMOS transistor And the transistor size of the twelfth PMOS transistor is the same, and the transistor size of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are the same. 5. The wideband low-power transconductance operational amplifier with enhanced slew rate according to claim 1, characterized in that: the ninth NMOS transistor, the eighth NMOS transistor and the seventh NMOS transistor The ratio of transistor size is 1:m:n, the ratio of transistor size of the sixteenth NMOS transistor, the seventeenth NMOS transistor and the eighteenth NMOS transistor is 1:m:n, n=m+ 2.5. The ninth NMOS transistor and the sixteenth NMOS transistor have the same transistor size. 6. A kind of slew rate enhanced broadband low-power transconductance operational amplifier according to claim 1, characterized in that: said first PMOS transistor, said second PMOS transistor, said sixth PMOS transistor and The transistor size of the seventh PMOS transistor is the same. 7. A kind of slew rate enhanced broadband low-power transconductance operational amplifier according to claim 1, characterized in that: said tenth NMOS transistor, said eleventh NMOS transistor, said twelfth NMOS transistor The transistor size ratio of the tubes is 6:1:1, the ratio of the transistor sizes of the fifteenth NMOS transistor, the fourteenth NMOS transistor, and the thirteenth NMOS transistor is 6:1:1, and the The transistor size of the twelfth NMOS transistor is the same as that of the fifteenth NMOS transistor. 8. A kind of slew rate enhanced broadband low-power transconductance operational amplifier according to any one of claims 1 to 7, characterized in that: the common mode feedback voltage is generated by a switched capacitor type common mode feedback circuit .

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