CN102075151A - Complementary circulation folding gain bootstrapping operational amplifier circuit with preamplifier - Google Patents

Abstract

The invention discloses a complementary loop folding gain bootstrap operational amplifier circuit with a preamplifier, which belongs to the technical field of operational amplifiers. It has a pre-amplifier consisting of N-type transistors (N1, N2, N3, N4), complementary inputs via P-type transistors (P1, P2, P3, P4) and N-type transistors (N16, N17, N18, N19), and The loop folding gain bootstrap transconductance operational amplifier structure is adopted to improve the unity-gain bandwidth of the transconductance operational amplifier. This circuit has the characteristics of high unity gain bandwidth and low power consumption, which is in line with the current research and development direction of integrated circuits.

Description

Complementary Loop Folding Gain Bootstrap Operational Amplifier Circuit with Preamplifier

technical field

The invention relates to the fields of microelectronics and solid electronics, and relates to an operational amplifier, in particular to a complementary loop folding gain bootstrap operational amplifier circuit with a preamplifier.

Background technique

The operational amplifier is one of the most important modules of many analog circuits, and is widely used in analog signal processing circuits such as analog-to-digital conversion circuits and filters. It usually determines the accuracy, speed and power consumption that the high-performance switched capacitor circuit can achieve. In a switched capacitor circuit, the load is usually purely capacitive. At this time, the power consumption of a single-stage operational amplifier (OTA) is better than that of a multi-stage operational amplifier, and a single-stage operational amplifier with a gain bootstrap structure can provide very high gain. . Therefore, the traditional folded gain bootstrap OTA amplifier has been widely used. However, traditional folded-gain bootstrap OTA amplifiers have disadvantages such as slow speed and high power consumption. On the one hand, the working speed of integrated circuits is increasing day by day; on the other hand, in the field of consumer electronics, mobile portable devices powered by batteries require the power consumption of circuits to be as low as possible, so as to prolong the use time of mobile portable devices.

Contents of the invention

(1) Technical problems to be solved

In order to overcome the shortcomings of the existing folded gain bootstrap OTA, such as slow speed and large power consumption, the present invention provides a complementary loop folded gain bootstrap OTA with a pre-amplifier. The problem to be solved is to improve the gain bootstrap OTA Unity gain bandwidth GBW to increase its operating speed and reduce power consumption.

(2) Technical solutions

In order to solve the above-mentioned technical problems, the invention provides a kind of complementary loop folding gain bootstrap operational amplifier circuit with pre-amplifier, comprising: pre-amplifier circuit, P-type complementary input branch and N-type complementary input branch, wherein:

The pre-amplifier circuit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5, wherein:

The source of the fifth NMOS transistor N5 is grounded, and the gate is connected to the N-type first bias voltage Vbn1; the gate of the first NMOS transistor N1 is connected to the first full differential signal VINN; the gate of the second NMOS transistor N2 is connected to the second full differential signal Signal VINP; the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and then connected to the drain of the fifth NMOS transistor N5; the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 After the poles are connected, the N-type zero bias voltage Vbn0 is connected, and the drains of the two are connected to the power supply voltage VDD;

The P-type complementary input branch includes: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, wherein: both the first PMOS transistor P1 and the second PMOS transistor P2 The gate of the gate is connected to the first full differential signal VINN; the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the second full differential signal VINP;

The N-type complementary input branch includes: a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, and a nineteenth NMOS transistor N19, wherein: the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N19 The gates of the NMOS transistors N17 and N17 are interconnected and then connected to the first full differential signal VINN; the gates of the eighteenth NMOS transistor N18 and the nineteenth NMOS transistor N19 are connected and then connected to the second full differential signal VINP.

Wherein, the circuit further includes: a P-type bias voltage transistor part connected to the P-type complementary input branch, a P-type bias tail current transistor pair part, a P-type cascode transistor part, and the P-type A first operational amplifier partially connected to a type cascode transistor; where,

The P-type bias voltage transistor part includes a fifth PMOS transistor P5, the source of the fifth PMOS transistor P5 is connected to the power supply voltage VDD, the gate is connected to the P-type first bias voltage Vbp1, and the drain is connected to the first P-type bias voltage Vbp1 at the same time. The sources of the first to fourth four PMOS transistors P1-P4 are connected;

The P-type bias tail current transistor part includes: a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor M9, wherein: the sixth to ninth NMOS transistors are four in total The sources of N6-N9 are all grounded; the gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are interconnected and then connected to the drain of the third PMOS transistor P3; the eighth NMOS transistor N8, The gates of the ninth NMOS transistor N9 are connected to the drain of the second PMOS transistor P2; the drains of the sixth NMOS transistor N6 and the first PMOS transistor P1 are connected;

The P-type cascode transistor pair includes: the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, and the thirteenth NMOS transistor N13, wherein: the source of the tenth NMOS transistor N10 connected to the drain of the sixth NMOS transistor N6, the source of the eleventh NMOS transistor N11 is connected to the drain of the ninth NMOS transistor N9, the source of the twelfth NMOS transistor N12 is connected to the seventh transistor The drain of N7 is connected, the source of the thirteenth NMOS transistor N13 is connected to the drain of the eighth NMOS transistor N8, the drain of the twelfth NMOS transistor N12 is connected to the drain of the third PMOS transistor P3, The drain of the thirteenth NMOS transistor N13 is connected to the drain of the second PMOS transistor P2; voltage Vbn2;

The positive terminal of the power supply voltage of the first operational amplifier is connected to the drain of the sixth PMOS transistor P6, the negative terminal of the power supply voltage is connected to the drain of the ninth PMOS transistor P9, and the positive output terminal connects the first output signal POUTP to the drain of the sixth PMOS transistor P6. The gate of the fifteenth PMOS transistor P15, the negative output terminal outputs the second output signal POUTN to the gate of the fourteenth PMOS transistor P14, and the first bias voltage terminal PVCM is connected to the N-type bias voltage.

Wherein, the circuit also includes:

The N-type bias voltage transistor part connected to the N-type complementary input branch, the N-type bias tail current transistor part, the N-type cascode transistor part, and the N-type cascode transistor part connected second operational amplifier;

The N-type bias voltage transistor part includes a twentieth NMOS transistor N20, the source of the twentieth NMOS transistor N20 is grounded, and the drain is simultaneously connected to the sixteenth to nineteenth NMOS transistors N16-N16. The source of N19 is connected, and the gate of the twentieth NMOS transistor N20 is connected to the common mode control signal VCMFB;

The N-type bias tail current transistor part includes: a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, and a ninth PMOS transistor P9, wherein there are four PMOS transistors P6 to P9 in total from the sixth to the ninth The sources of P9 are connected to the power supply voltage VDD; the gates of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the drain of the eighteenth NMOS transistor N18; the eighth PMOS The gates of the transistor P8 and the ninth PMOS transistor P9 are interconnected and then connected to the drain of the seventh NMOS transistor N7; the drains of the sixth PMOS transistor P6 and the drains of the sixteenth MOS transistor N16 are connected; The drains of the ninth PMOS transistor P9 and the nineteenth NMOS transistor N19 are connected;

The N-type cascode transistor part includes: a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, and a fifteenth PMOS transistor P15, wherein the twelfth PMOS transistor P12, The gates of the thirteenth PMOS transistor P13 are connected to the second P-type bias voltage Vbp2; the source of the twelfth PMOS transistor P12 is connected to the drain of the seventh PMOS transistor P7, and the twelfth PMOS transistor P12 The drain of the transistor P12 is connected to the drain of the eighteenth NMOS transistor N18, the source of the thirteenth PMOS transistor P13 is connected to the drain of the eighth PMOS transistor P8, and the drain of the thirteenth PMOS transistor P13 is connected to the drain of the eighth PMOS transistor P8. The drain of the seventeenth NMOS transistor N17 is connected, the source of the fourteenth PMOS transistor P14 is connected to the drain of the sixth PMOS transistor P6, and the drain of the fourteenth PMOS transistor P14 is connected to the tenth NMOS transistor P14. The drain of the transistor N10 is connected to output the first differential signal VOUTP, the source of the fifteenth PMOS transistor P15 is connected to the drain of the ninth PMOS transistor P9, and the drain of the fifteenth PMOS transistor P15 is connected to the tenth PMOS transistor P15. The drains of an NMOS transistor N11 are connected to output a second differential signal VOUTN;

The negative terminal of the power supply voltage of the second operational amplifier is connected to the source of the eleventh NMOS transistor N11, the positive terminal of the power supply voltage is connected to the source of the tenth NMOS transistor N10, and the positive output terminal outputs the third output signal NOUTP to the tenth NMOS transistor N10. The gate of a PMOS transistor P11, and the negative output terminal outputs the fourth output signal NOUTN to the gate of the tenth NMOS transistor N10, and the second bias voltage terminal NVCM is connected to the P-type bias voltage.

(3) Beneficial effects

The present invention adopts the complementary input branch composed of N-type MOS transistor and P-type MOS transistor, and the cascode transistors N10, N11 and P14, P15 of the N-type complementary input branch and the P-type complementary input branch share the same Therefore, the current of each branch is more fully utilized, which effectively improves the unit gain bandwidth GBW of the operational amplifier and improves the operating speed of the operational amplifier. And because the cascode bootstrap circuit Nboost and Pboost are added, the gain of the circuit is improved. Simulation results show that the circuit improves unity-gain bandwidth and DC gain. Therefore, using the present invention can increase the speed of high-performance switched capacitors such as high-performance analog-to-digital converters and reduce power consumption.

Description of drawings

Fig. 1 is a circuit structure diagram of the present invention;

Fig. 2 is a Pboost circuit structure diagram;

Fig. 3 is the structure diagram of Nboost circuit.

Detailed ways

The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

The invention belongs to the design of ultra-large-scale integrated circuits in the field of microelectronics and solid-state electronics, and relates to a gain bootstrap OTA circuit, which can be used in the design of analog signal processing circuits such as analog-to-digital conversion circuits and filters. Design of high-speed gain bootstrap operational amplifiers in high-performance switched capacitor circuits such as high-speed analog-to-digital converters.

The circuit structure of the present invention is referring to Fig. 1, and the present invention provides a kind of complementary loop folding gain bootstrap operational amplifier circuit with preamplifier, comprises: preamplifier circuit, P-type complementary input branch and N-type complementary input branch, in:

The pre-amplifier circuit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5, wherein:

The source of the fifth NMOS transistor N5 is grounded, and the gate is connected to the N-type first bias voltage Vbn1; the gate of the first NMOS transistor N1 is connected to the first full differential signal VINN; the gate of the second NMOS transistor N2 is connected to the second full differential signal Signal VINP; the source of the first NMOS transistor N1 is connected to the source of the second NMOS transistor N2 and then connected to the drain of the fifth NMOS transistor N5; the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 After the poles are connected, the N-type zero bias voltage Vbn0 is connected, and the drains of the two are connected to the power supply voltage VDD;

The P-type complementary input branch includes: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, wherein: both the first PMOS transistor P1 and the second PMOS transistor P2 The gate of the gate is connected to the first full differential signal VINN; the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the second full differential signal VINP;

The N-type complementary input branch includes: a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, and a nineteenth NMOS transistor N19, wherein: the sixteenth NMOS transistor N16, the seventeenth NMOS transistor N19 The gates of the NMOS transistors N17 and N17 are interconnected and then connected to the first full differential signal VINN; the gates of the eighteenth NMOS transistor N18 and the nineteenth NMOS transistor N19 are connected and then connected to the second full differential signal VINP.

Wherein, the circuit further includes: a P-type bias voltage transistor part connected to the P-type complementary input branch, a P-type bias tail current transistor pair part, a P-type cascode transistor part, and the P-type A first operational amplifier partially connected to a type cascode transistor; where,

The P-type bias voltage transistor part includes a fifth PMOS transistor P5, the source of the fifth PMOS transistor P5 is connected to the power supply voltage VDD, the gate is connected to the P-type first bias voltage Vbp1, and the drain is connected to the first P-type bias voltage Vbp1 at the same time. The sources of the first to fourth four PMOS transistors P1-P4 are connected;

The P-type bias tail current transistor part includes: a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor M9, wherein: the sixth to ninth NMOS transistors are four in total The sources of N6-N9 are all grounded; the gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are interconnected and then connected to the drain of the third PMOS transistor P3; the eighth NMOS transistor N8, The gates of the ninth NMOS transistor N9 are connected to the drain of the second PMOS transistor P2; the drains of the sixth NMOS transistor N6 and the first PMOS transistor P1 are connected;

The P-type cascode transistor pair includes: the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, and the thirteenth NMOS transistor N13, wherein: the source of the tenth NMOS transistor N10 connected to the drain of the sixth NMOS transistor N6, the source of the eleventh NMOS transistor N11 is connected to the drain of the ninth NMOS transistor N9, the source of the twelfth NMOS transistor N12 is connected to the seventh transistor The drain of N7 is connected, the source of the thirteenth NMOS transistor N13 is connected to the drain of the eighth NMOS transistor N8, the drain of the twelfth NMOS transistor N12 is connected to the drain of the third PMOS transistor P3, The drain of the thirteenth NMOS transistor N13 is connected to the drain of the second PMOS transistor P2; voltage Vbn2;

The positive terminal of the power supply voltage of the first operational amplifier is connected to the drain of the sixth PMOS transistor P6, the negative terminal of the power supply voltage is connected to the drain of the ninth PMOS transistor P9, and the positive output terminal connects the first output signal POUTP to the drain of the sixth PMOS transistor P6. The gate of the fifteenth PMOS transistor P15, the negative output terminal outputs the second output signal POUTN to the gate of the fourteenth PMOS transistor P14, and the first bias voltage terminal PVCM is connected to the N-type bias voltage.

Wherein, the circuit also includes:

The N-type bias voltage transistor part connected to the N-type complementary input branch, the N-type bias tail current transistor part, the N-type cascode transistor part, and the N-type cascode transistor part connected to the N-type cascode transistor part second operational amplifier;

The N-type bias voltage transistor part includes a twentieth NMOS transistor N20, the source of the twentieth NMOS transistor N20 is grounded, and the drain is simultaneously connected to the sixteenth to nineteenth NMOS transistors N16-N16. The source of N19 is connected, and the gate of the twentieth NMOS transistor N20 is connected to the common mode control signal VCMFB;

The N-type bias tail current transistor part includes: a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, and a ninth PMOS transistor P9, wherein there are four PMOS transistors P6 to P9 in total from the sixth to the ninth The sources of P9 are connected to the power supply voltage VDD; the gates of the sixth PMOS transistor P6 and the seventh PMOS transistor P7 are connected to the drain of the eighteenth NMOS transistor N18; the eighth PMOS The gates of the transistor P8 and the ninth PMOS transistor P9 are interconnected and then connected to the drain of the seventh NMOS transistor N7; the drains of the sixth PMOS transistor P6 and the drains of the sixteenth MOS transistor N16 are connected; The drains of the ninth PMOS transistor P9 and the nineteenth NMOS transistor N19 are connected;

The N-type cascode transistor part includes: a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, and a fifteenth PMOS transistor P15, wherein the twelfth PMOS transistor P12, The gates of the thirteenth PMOS transistor P13 are connected to the second P-type bias voltage Vbp2; the source of the twelfth PMOS transistor P12 is connected to the drain of the seventh PMOS transistor P7, and the twelfth PMOS transistor P12 The drain of the transistor P12 is connected to the drain of the eighteenth NMOS transistor N18, the source of the thirteenth PMOS transistor P13 is connected to the drain of the eighth PMOS transistor P8, and the drain of the thirteenth PMOS transistor P13 is connected to the drain of the eighth PMOS transistor P8. The drain of the seventeenth NMOS transistor N17 is connected, the source of the fourteenth PMOS transistor P14 is connected to the drain of the sixth PMOS transistor P6, and the drain of the fourteenth PMOS transistor P14 is connected to the tenth NMOS transistor P14. The drain of the transistor N10 is connected to output the first differential signal VOUTP, the source of the fifteenth PMOS transistor P15 is connected to the drain of the ninth PMOS transistor P9, and the drain of the fifteenth PMOS transistor P15 is connected to the tenth PMOS transistor P15. The drains of an NMOS transistor N11 are connected to output a second differential signal VOUTN;

The negative terminal of the power supply voltage of the second operational amplifier is connected to the source of the eleventh NMOS transistor N11, the positive terminal of the power supply voltage is connected to the source of the tenth NMOS transistor N10, and the positive output terminal outputs the third output signal NOUTP to the tenth NMOS transistor N10. The gate of a PMOS transistor P11, and the negative output terminal outputs the fourth output signal NOUTN to the gate of the tenth NMOS transistor N10, and the second bias voltage terminal NVCM is connected to the P-type bias voltage.

Transistors P1, P2, P3, and P4 in FIG. 1 are P-type input devices, and N16, N17, N18, and N19 are N-type input devices. VINP and VINN are fully differential input signals. VINP is added to the gates of P3, P4 and N18 and N19, and VINN is added to the gates of P1, P2 and N16 and N17. Transistor P5 provides bias current for the P-type complementary input branch composed of P1, P2, P3, and P4, and N20 provides bias current for the N-type complementary input branch composed of N16, N17, N18, and N19. At the same time, N20 provides a path to control the common-mode components of the output VOUTP, VOUTN through the signal VCMFB generated in the common-mode feedback circuit (N-type bias voltage crystal silicon part). Transistors N6, N7, N8, and N9 are bias tail current transistors of the P-type complementary input branch, and N10, N11, N12, and N13 are cascode transistor pairs of the P-type complementary input branch. Transistors P6, P7 and P8, P9 are bias tail current transistors of the N-type complementary input branch. P14, P15 and P12, P13 are cascode transistor pairs of the N-type complementary input branch. VOUTP and VOUTN are fully differential outputs. Vbp1 is the bias voltage of the transistor P5, and Vpb2 is the bias voltage of the transistors P14, P15, P12, and P13. Vbn2 is the bias voltage of the transistors N10, N11, N12, and N13. VDD and GND have supply voltages of 1.8V and 0V, respectively.

Compared with conventional gain bootstrapping OTA, the present invention has adopted N-type MOS tube and P-type MOS tube branch complementary input; With only P-type input device Rida S.Assaad cycle folding OTA (can refer to IEEE solid-state circuit magazine 2009 Compared with the cyclic folding OTA structure reported in the article "The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier" on pages 2535-2542 of Volume 9 in September 2009), the complementary cyclic folding OTA of the present invention increases the N-type complementary The input branch, and the cascode transistors N10, N11 and P14, P15 of the N-type complementary input branch and the P-type complementary input branch share the same current. Therefore, the current of each branch is more fully utilized, effectively improving the unity gain bandwidth GBW of the operational amplifier, and improving the working speed of the operational amplifier. And because the cascode bootstrap circuit Nboost and Pboost are added, the gain of the amplifier is improved.

As shown in Figure 2, the input PINP and PINN of the auxiliary amplifier Pboost (namely the above-mentioned first operational amplifier) are connected to the nodes 24 and 27, the output POUTP and POUTN are connected to the nodes 61 and 60, PVCM, PVbp1, PVbp2, PVbn1 and PVbn1 for a fixed bias voltage.

As shown in Figure 3, the inputs NINP and NINN of the auxiliary amplifier Nboost (that is, the above-mentioned second operational amplifier) are connected to nodes 14 and 17, and the outputs NOUTP and NOUTN are connected to nodes 63 and 62, VCMFB, NVCM, PVCM, NVbp1, NVbp2 , NVbn1, NVbn1, PVbp1, PVbp2, PVbn2 and PVbn1 are fixed bias voltages.

In order to verify the performance, SPICE simulation is carried out on the CADENCE platform.

Simulation results show that the unity-gain bandwidth is 11.26GHz at a 3pF capacitive load. Therefore, a summary of the characteristics of the gain bootstrap OTA of the present invention can be obtained, as shown in Table 1.

Table 1

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (3)

1. A complementary circulating folded gain bootstrapped operational amplifier circuit with a preamplifier, comprising: a preamplifier circuit, a P-type complementary input branch, and an N-type complementary input branch, wherein:

the preamplifier circuit comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5, wherein:

the source electrode of the fifth NMOS tube N5 is grounded, and the grid electrode of the fifth NMOS tube N5 is connected with an N-type first bias voltage Vbn 1; the grid of the first NMOS transistor N1 is connected with a first fully differential signal VINN; the grid of the second NMOS transistor N2 is connected with a second fully differential signal VINP; the source electrode of the first NMOS transistor N1 is connected with the source electrode of the second NMOS transistor N2 and then is connected with the drain electrode of the fifth NMOS transistor N5; the grid electrodes of the third NMOS tube N3 and the fourth NMOS tube N4 are connected and then connected with an N-type zero bias voltage Vbn0, and the drain electrodes of the third NMOS tube N3 and the fourth NMOS tube N4 are connected and then connected with a power supply voltage VDD;

the P-type complementary input branch comprises: a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, wherein: the gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected and then connected to the first fully differential signal VINN; the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected and then connected with the second fully differential signal VINP;

the N-type complementary input branch comprises: sixteenth NMOS transistor N16, seventeenth NMOS transistor N17, eighteenth NMOS transistor N18, and nineteenth NMOS transistor N19, wherein: the gates of the sixteenth NMOS transistor N16 and the seventeenth NMOS transistor N17 are interconnected and then connected with the first fully differential signal VINN; the gates of the eighteenth NMOS transistor N18 and the nineteenth NMOS transistor N19 are interconnected and then connected with the second fully differential signal VINP.

2. The circuit of claim 1, wherein the circuit further comprises: the P-type offset voltage transistor part, the P-type offset tail current transistor pair part, the P-type cascode transistor part and the first operational amplifier are connected with the P-type cascode transistor part; wherein,

the P-type bias voltage transistor part comprises a fifth PMOS transistor P5, the source electrode of the fifth PMOS transistor P5 is connected with the power supply voltage VDD, the grid electrode of the fifth PMOS transistor P5 is connected with a P-type first bias voltage Vbp1, and the drain electrode of the fifth PMOS transistor P5 is simultaneously connected with the source electrodes of the first to fourth PMOS transistors P1-P4;

the P-type bias tail current transistor portion includes: a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a ninth NMOS transistor M9, wherein: the sources of the sixth to ninth NMOS transistors N6-N9 are all grounded; the gates of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are interconnected and then connected with the drain of the third PMOS transistor P3; the gates of the eighth NMOS transistor N8 and the ninth NMOS transistor N9 are interconnected and then connected with the drain of the second PMOS transistor P2; the drain electrodes of the sixth NMOS transistor N6 and the first PMOS transistor P1 are connected;

the P-type cascode transistor pair section includes: a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, and a thirteenth NMOS transistor N13, wherein: a source electrode of a tenth NMOS transistor N10 is connected to a drain electrode of the sixth NMOS transistor N6, a source electrode of an eleventh NMOS transistor N11 is connected to a drain electrode of the ninth NMOS transistor N9, a source electrode of a twelfth NMOS transistor N12 is connected to a drain electrode of the seventh transistor N7, a source electrode of a thirteenth NMOS transistor N13 is connected to a drain electrode of the eighth NMOS transistor N8, a drain electrode of the twelfth NMOS transistor N12 is connected to a drain electrode of the third PMOS transistor P3, a drain electrode of a thirteenth NMOS transistor N13 is connected to a drain electrode of the second PMOS transistor P2, and gate electrodes of the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13 are connected to an N-type second bias voltage Vbn 2;

the positive end of the power supply voltage of the first operational amplifier is connected with the drain electrode of the sixth PMOS tube P6, the negative end of the power supply voltage is connected with the drain electrode of the ninth PMOS tube P9, the positive output end outputs a first output signal POUTP to the grid electrode of the fifteenth PMOS tube P15, the negative output end outputs a second output signal POUTN to the grid electrode of the fourteenth PMOS tube P14, and the first bias voltage end PVCM is connected with an N-type bias voltage.

3. The circuit of claim 1, wherein the circuit further comprises:

the N-type bias voltage transistor part, the N-type bias tail current transistor part, the N-type cascode transistor part and the second operational amplifier are connected with the N-type cascode transistor part;

the N-type bias voltage transistor part comprises a twentieth NMOS transistor N20, the source electrode of the twentieth NMOS transistor N20 is grounded, the drain electrode of the twentieth NMOS transistor is simultaneously connected with the source electrodes of the sixteenth to nineteenth NMOS transistors N16-N19, and the grid electrode of the twentieth NMOS transistor N20 is connected with a common mode control signal VCMFB;

the N-type bias tail current transistor portion includes: a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8 and a ninth PMOS transistor P9, wherein the sources of the sixth to ninth PMOS transistors P6 to P9 are connected with the power supply voltage VDD; the gates of the sixth PMOS tube P6 and the seventh PMOS tube P7 are interconnected and then connected with the drain of the eighteenth NMOS tube N18; the gates of the eighth PMOS transistor P8 and the ninth PMOS transistor P9 are interconnected and then connected with the drain of the seventh NMOS transistor N7; the drain electrode of the sixth PMOS tube P6 and the drain electrode of the sixteenth MOS tube N16 are connected; the drains of a ninth PMOS tube P9 and a nineteenth NMOS tube N19 are connected;

the N-type cascode transistor portion includes: a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14 and a fifteenth PMOS tube P15, wherein the gates of the twelfth PMOS tube P12 and the thirteenth PMOS tube P13 are interconnected and then connected with a P-type second bias voltage Vbp 2; a source of a twelfth PMOS transistor P12 is connected to a drain of a seventh PMOS transistor P7, a drain of the twelfth PMOS transistor P12 is connected to a drain of the eighteenth NMOS transistor N18, a source of the thirteenth PMOS transistor P13 is connected to a drain of the eighth PMOS transistor P8, a drain of the thirteenth PMOS transistor P13 is connected to a drain of the seventeenth NMOS transistor N17, a source of the fourteenth PMOS transistor P14 is connected to a drain of the sixth PMOS transistor P6, a drain of the fourteenth PMOS transistor P14 is connected to a drain of the tenth NMOS transistor N10 to output a first differential signal VOUTP, a source of the fifteenth PMOS transistor P15 is connected to a drain of the ninth PMOS transistor P9, and a drain of the fifteenth PMOS transistor P15 is connected to a drain of the eleventh NMOS transistor N11 to output a second differential signal VOUTN;

the negative end of the power supply voltage of the second operational amplifier is connected with the source electrode of an eleventh NMOS tube N11, the positive end of the power supply voltage is connected with the source electrode of a tenth NMOS tube N10, the positive output end outputs a third output signal NOUTP to the grid electrode of the eleventh PMOS tube P11, the negative output end outputs a fourth output signal NOUTN to the grid electrode of the tenth NMOS tube N10, and the second bias voltage end NVCM is connected with a P-type bias voltage.

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