CN101621292B - Switch-capacitor integrator - Google Patents

Abstract

The invention discloses a switched capacitor integrator adopting a new class C inverter and a realization form of the switched capacitor integrator with a pseudo-differential structure. The switched capacitor integrator with pseudo-differential structure includes two novel C-class inverters (60) and capacitors of the prior art (sampling capacitor C _S , compensation capacitor C _C and integration capacitor C _I , etc.), switches (NMOS switches S2, S4 , S7 and S8, CMOS switches S3, S5 and bootstrap NMOS switches S1, S6 and S9, etc.), common mode feedback circuit (61). Two of the new class-C inverters are respectively located in the positive and negative branches of the integrator and are differentially symmetrical, forming a pseudo-differential structure. Through the body potential modulation function of the body potential modulator in the new type C inverter, the present invention overcomes the influence of the process deviation on the operating frequency, settling time, integration accuracy and power consumption of the switched capacitor integrator, without significantly increasing the power consumption. This greatly improves the stability and robustness of the integrator.

Description

Switched Capacitor Integrator

technical field

The invention relates to a switched capacitor integrator and a switched capacitor integrator with a pseudo-differential structure, belonging to the technical field of integrated circuits.

Background technique

In recent years, with the rapid development of informatization construction, signal and information processing has widely penetrated into various fields of scientific research, technological development, industrial production, national defense and national economy, and has become an important driving force for global economic and social development. Because of this, the design of signal processing chips has become a research hotspot for integrated circuit designers. In order to meet the needs of battery-driven portable devices and the energy-saving needs of large-scale systems, signal processing chips need to continue to move towards lower voltage, lower power consumption, and lower cost while ensuring high performance.

Integrator is an important functional circuit commonly used in signal processing chips, and it has a major impact on the overall performance of signal processing chips. In early signal processing circuits, circuit designers generally used resistors, capacitors, and amplifiers to form continuous-time circuits to form the required integrator transfer function and process the signal. However, the absolute error of resistance and capacitance limits its application in high-precision circuits. Later, people gradually adopted the switched capacitor integrator composed of MOS switch, capacitor and amplifier to process the signal accurately. The reason why the switched capacitor integrator can be successfully applied to high-precision signal processing is that the accuracy of the signal processing function is mainly related to the ratio of the capacitance. At the same time, it has good linearity and temperature characteristics, and is easy to realize in CMOS process.

In the switched capacitor integrator, the operational amplifier is an indispensable component module, and it is also the most important power consumption module. To achieve a very low power switched capacitor integrator, the design of a low voltage low power op amp is critical. It is a new low-voltage low-power circuit design technology to replace the traditional operational amplifier with a class-C inverter. The main part of the class C inverter is a push-pull inverter, as shown in Figure 1, the structure is quite simple, the power consumption is extremely low, and the chip occupies a small area. On state time is less than 50%. In practical applications, the class C inverter adopts dynamic bias technology, that is, its working state is constantly changing through the modulation of the input tube grid potential. In the design of the switched capacitor integrator, the class C inverter should switch reasonably between the following two different working states according to the performance requirements of the integrator at different phases.

1) High gain and low power consumption state: When both the PMOS input transistor M1 and the NMOS input transistor M2 are in the weak inversion region, the inverter has high gain and extremely low power consumption, but the transconductance and bandwidth are relatively small , for the sampling phase of the integrator and the settling phase of the integrating phase.

2) High slew rate and high current state: When M1 is in the strong inversion region and M2 is in the cut-off region (or M2 is in the strong inversion region and M1 is in the cut-off region), the transconductance of the MOS input transistor working in the strong inversion region is relatively high. Large, so that the inverter has a larger slew rate and output current, which is suitable for the slewing phase in the integral phase of the integrator. And because the other input tube is in the cut-off region, the conduction current of the entire inverter from the power supply to the ground is extremely small, which avoids unnecessary static power consumption.

According to the above principles, Youngcheol Chae et al. implemented a very low power consumption high precision switched capacitor based on a class C inverter in the article "A0.7V 36uW 85dB-DR Audio Δ∑Modulator Using Class-C Inverter" (ISSCC2008) Integrator. Wherein, in order to increase the steady-state gain, the inverter adopts a cascode structure as shown in FIG. 2 , wherein the bias potentials of the PMOS transistor M3 and the NMOS transistor M4 are the ground potential GND and the power supply potential V _DD respectively.

However, for the switched capacitor integrator using the prior art class C inverter, when it works in the sampling phase or the holding phase of the integration phase, the input tubes in the class C inverter all work in the weak inversion region, and its The transconductance is greatly affected by the process deviation (especially when the size of the MOS tube is large), which leads to serious deviations in the steady-state characteristics of the class C inverter such as gain, bandwidth, and static power consumption under different process angles, and the gain deviation It will affect the accuracy of charge sampling and transmission of the integrator, and the deviation of bandwidth and static power consumption will make the operating frequency and static power consumption of the integrator extremely unstable. When the Class C inverter is switched to a high slew rate and high current state, the influence of process deviation on the dynamic parameters such as the slew rate and the settling time of the C class inverter cannot be ignored, which makes the switched capacitor integrator work in the settling phase The deterioration of the settling time, integration accuracy and dynamic power consumption of the integrator may eventually lead to a decrease in the performance of the integrator or even a loss of function.

Contents of the invention

The technical problem to be solved by the present invention is to provide a switched capacitor integrator using a new class C inverter to overcome the fact that the transconductance of the class C inverter in the switched capacitor integrator of the prior art is greatly affected by the process deviation Large (especially when the size of the MOS tube is large), which leads to inaccurate charge sampling and transmission when the integrator works in the sampling phase or maintaining the phase, and the operating frequency and power consumption are extremely unstable; The deterioration of indicators such as accuracy and dynamic power consumption may eventually lead to insufficient integrator performance degradation or even loss of function.

Another technical problem to be solved by the present invention is to provide a switched capacitor integrator with a pseudo-differential structure using a new class-C inverter.

The switched capacitor integrator of the present invention adopts the following technical scheme, which includes a novel class-C inverter, a sampling capacitor, a compensation capacitor, an integrating capacitor and switches, etc., wherein the novel class-C inverter is single-ended input and single-ended output. The switched capacitor integrator uses the new class C inverter of the present invention to replace the traditional operational amplifier or the class C inverter of the prior art. While greatly reducing the power consumption of the circuit, it overcomes the influence of process deviation on itself and ensures Integrator robustness and practicality.

The novel C-class inverter is based on the prior art C-class inverter, adding a PMOS body potential modulator and an NMOS body potential modulator. Among them, the class C inverter in the prior art is used to realize the operation amplification function, and the PMOS body potential modulator and the NMOS body potential modulator are used to realize the body potential modulation of the PMOS input tube and the NMOS input tube of the inverter respectively, so as to weaken the process Deviations have adverse effects on Class C inverters.

The body potential modulator in the new type C inverter is composed of a MOS tube and a high-precision resistor, in which the MOS tube is of the same type as the corresponding inverter input tube (body potential modulation object), and the layout is matched symmetrically, with a width and length The ratio is fixed, and the gate-source voltage of the MOS transistor is the same as the gate-source bias voltage of the inverter input transistor in steady state. Therefore, the process deviation and temperature conditions of the MOS tube in the body potential modulator are approximately the same as those of the inverter input tube at any time, and the change trend of the drain-source current of the two MOS tubes is also the same. In other words, the MOS tube in the body potential modulator can "sense" the change characteristics of the transconductance, output current and other parameters of the corresponding inverter input tube at different process angles and temperatures, and is called an inductive MOS tube. The body terminal of the sensing MOS tube is connected to the source terminal, and the drain terminal is connected to a high-precision resistor. The high-precision resistor is used to realize the function of "sensing" the current signal (sensing the drain-source current of the MOS tube) to the voltage signal, and it acts as a load on the sensing MOS tube. The drain end of the tube feeds back the output voltage signal of the body potential modulator to the body end of the input tube of the inverter. The whole body potential modulator forms an "inductive feedback" loop for body potential modulation. Through the modulation of the output voltage signal of the body potential modulator on the corresponding inverter input tube body (that is, to adjust the body-source voltage of the inverter input tube), the transconductance and drain-source current of the inverter input tube are different It is more consistent in the case of the process angle. According to the MOS tube type of the body potential modulation object, the body potential modulator can be divided into a PMOS body potential modulator and an NMOS body potential modulator. In the PMOS body potential modulator, the source potential of the sensing PMOS transistor determines the maximum value of the body potential modulation range, which can be set according to actual applications. The potential at the other end of the high-precision resistor determines the minimum value of the body potential modulation range. In the NMOS body potential modulator, the source potential of the sensing NMOS tube determines the minimum value of the body potential modulation range, and the potential at the other end of the high-precision resistor determines the maximum value of the body potential modulation range.

Among the new class C inverters, the main structure of the prior art class C inverter can be a simple inverter or a cascode inverter, and the power supply voltage is slightly lower than that in the inverter. The sum of the threshold voltages of the two input transistors.

The sampling capacitor in the prior art is located at the signal input end, and is used for sampling the input signal when the integrator samples the phase, and accurately transfers its own charge to the integrating capacitor when integrating the phase.

The compensation capacitor of the prior art is located at the input end of the new type C inverter, which is used to eliminate the adverse effect of the offset voltage of the inverter, and forms a "virtual ground" at the lower plate to ensure the accuracy of charge transmission when the integrator integrates the phase .

The integrating capacitor in the prior art, also known as the feedback capacitor, forms a feedback loop between the lower plate of the compensation capacitor and the output terminal of the new type C inverter, and is used for the self-stored charge of the integrator to transfer to the next-stage circuit when the integrator samples the phase. transfer, and the accumulation of transferred charge to the sampling capacitor when the phase is integrated.

Switches in the prior art include NMOS switches, CMOS switches, and bootstrap NMOS switches. The bootstrap NMOS switch is located between the signal input terminal and the sampling capacitor for high linearity input signal sampling; two NMOS switches are respectively located between the upper and lower plates of the sampling capacitor and the input common mode level for setting and transmission Common mode level; two CMOS switches are respectively located between the upper and lower plates of the compensation capacitor and the upper plate of the integration capacitor, and are used for the transmission of charges between the capacitors.

The switched capacitor integrator is divided into a sampling phase and an integrating phase in actual work, and is controlled by a two-phase non-overlapping clock, and the integrating phase can be further divided into a slewing phase and a settling phase.

In the switched capacitor integrator, the class C inverter can realize two different working states of high gain, low power consumption and high slew rate and high current according to the difference in bias voltage at the input terminal of different working phases, as described below:

In the sampling phase, the node potential at the input terminal of the inverter is only the offset voltage of the inverter (set as V _OFF ), which is close to the common-mode level. Assuming that the threshold voltages of the two input tubes are approximately equal, and the input common-mode signal makes the input tubes of the inverter both in the weak inversion region, the stable state of high gain and low power consumption of the class C inverter can be realized. The introduction of the body potential modulator in the new type C inverter makes the gain, bandwidth and static power consumption of the inverter more consistent under different process angles, which is conducive to the accurate sampling and transmission of the switched capacitor integrator in the sampling phase charge , while reducing the sensitivity of the integrator's operating frequency and static power consumption to process variations.

In the establishment phase of the integral phase, the potential of the lower plate of the sampling capacitor suddenly changes to the common mode level, and the potential of the node at the input terminal of the inverter is pulled to -IN+V _OFF , where IN is the input sampled by the sampling capacitor in the sampling phase Signal. According to the polarity of the input signal, one input transistor in the inverter enters the strong inversion region, the other input transistor is cut off, and the Class C inverter enters a state of high slew rate and high current. In the holding phase of the integral phase, due to the negative feedback effect of the integral capacitor, the potential of the node at the input end of the inverter finally returns to the offset voltage V _OFF of the inverter, and the class C inverter re-enters the stability of high gain and low power consumption state. In the whole integration phase, the introduction of the body potential modulator in the new type C inverter makes the slew rate and dynamic power consumption of the inverter during the settling process more consistent under different process angles, thereby reducing the switching capacitor integrator The sensitivity of indicators such as settling time, integral accuracy and dynamic power consumption to process deviation improves the stability and robustness of the circuit.

It should be noted that the structure of the body potential modulator is quite simple, and the inductive MOS transistors M5 and M6 are both working in the weak inversion region, and the power consumption is very low, the typical value is 1% of the power consumption of the prior art class C inverter. /10 or so. Therefore, the introduction of the body potential modulator will not significantly increase the power consumption of the circuit, and is completely suitable for working environments with low voltage and low power consumption.

Pseudo-differential structure switched capacitor integrator of the present invention adopts following technical scheme, it comprises two novel C class inverters and the electric capacity (sampling electric capacity, compensating electric capacity and integral electric capacity etc.), switch (NMOS switch, CMOS switch) of prior art and bootstrap NMOS switches, etc.), common-mode feedback circuit. The two new type C inverters are respectively located in the positive and negative branches of the integrator, and the differential is symmetrical, forming a pseudo-differential structure, and the common-mode feedback circuit forms a common-mode feedback in the positive and negative branches of the integrator respectively. .

Common-mode feedback circuits of the prior art include:

The two common-mode feedback capacitors are located between the lower plate of the compensation capacitor and the input common-mode level in the sampling phase, and are respectively located between the lower plate of the compensation capacitor and the positive and negative output terminals of the integrator in the integration phase. The common-mode feedback capacitor It is used to detect the deviation between the output common mode level and the input common mode level, and feeds the deviation back to the integrator to form a common mode feedback loop;

Two bootstrap NMOS switches, respectively located between the lower plate of the common-mode feedback capacitor and the positive and negative output terminals of the integrator, are used for accurate sampling of the output signal in the common-mode feedback loop;

Two NMOS switches are respectively located between the lower plate of the common-mode feedback capacitor and the input common-mode level, and are used to set and transmit the common-mode level.

Different from the switched capacitor integrator with pseudo-differential structure realized by Youngcheol Chae et al., the switched capacitor integrator with pseudo-differential structure of the present invention adopts a more optimized topological structure, and it uses a sampling circuit comprising an integrating capacitor and related switches on the feedback loop. The holding branch replaces the original reset switch, and does not need to reset and clear the output terminal potential at each clock phase, so it relaxes the requirements for Class-C inverters (including new Class-C inverters and existing C-type inverters). class inverter) slew rate and settling time requirements. Although this topology has been used in differential switched capacitor integrators using traditional operational amplifiers, it is the first time that it is used in combination with Class C inverter technology to form a pseudo differential switched capacitor integrator.

Advantages and positive effects of the present invention: the switched capacitor integrator described in the present invention adopts a novel C-type inverter, through the body potential modulation of the body potential modulator in the novel C-type inverter at the input tube end of the inverter, The steady-state characteristics (gain, bandwidth, static power consumption, etc.) and dynamic characteristics (slew rate, settling time, dynamic power consumption, etc.) of the entire inverter are relatively consistent under different process angles, thereby reducing the switching capacitor integrator The sensitivity of indicators such as operating frequency, settling time, integral accuracy, and power consumption to process deviations greatly improves the stability and robustness of the circuit without significantly increasing power consumption.

Description of drawings

Figure 1 is a circuit structure diagram of a simple type C inverter;

Fig. 2 is a circuit structure diagram of a cascode type C inverter;

Fig. 3 is the circuit structural diagram of the novel class C inverter that the present invention adopts;

Fig. 4 is the schematic diagram of the switched capacitor integrator that adopts novel C class inverter of the present invention;

Fig. 5 is the two-phase non-overlapping clock of the switched capacitor integrator of the present invention and the curve diagram of the potential change at the input terminal of the class C inverter;

FIG. 6 is a circuit structure diagram of a switched capacitor integrator with a pseudo-differential structure according to the present invention.

Detailed ways

Embodiments of the invention:

Embodiment 1. The switched capacitor integrator proposed by the present invention includes a new class C inverter (hereinafter the same) with application number 2009103013271 (patent name: class C inverter using body potential modulator). The switched capacitor integrator replaces the traditional operational amplifier or the existing C-type inverter with a new type-C inverter, which greatly reduces the power consumption of the circuit and overcomes the influence of the process deviation on itself, ensuring the integral Robustness and practicality of the device.

Accompanying drawing 3 is the circuit structure diagram of the new class C inverter that adopts in the switched capacitor integrator, it is on the basis of prior art class C inverter 30, has increased PMOS body potential modulator 31 and NMOS body potential The modulator 32 (see the PMOS body potential modulator and the NMOS body potential modulator in the application number 2009103013271, the same below). Wherein the class C inverter 30 of the prior art is used to realize the operation amplification function, and the PMOS body potential modulator 31 and the NMOS body potential modulator 32 are respectively used to realize the body of the inverter PMOS input tube M1 and NMOS input tube M2 Potential modulation to weaken the adverse effects of process deviations on class C inverters.

Among the new class C inverters, the conventional class C inverter 30 is a cascode inverter, and the power supply voltage is slightly lower than the sum of the threshold voltages of the two input transistors in the inverter. Compared with the simple inverter, the gain of the cascode inverter is higher, which is beneficial to improve the establishment accuracy of the switched capacitor integrator. However, in some occasions where the accuracy requirement is not very high, the use of a simple inverter can increase the output swing and reduce the chip area.

The PMOS body potential modulator 31 in the new type C inverter is composed of the induction PMOS transistor M5 and the high-precision resistor R1, wherein the layout of the induction PMOS transistor M5 and the input transistor M1 of the inverter is matched symmetrically, and the width-to-length ratio is a fixed ratio ( between 1:5 and 1:20), and the gate-source voltage of M5 is the same as the gate-source bias voltage of M1 in the steady state of the weak inversion region (V _DDH -V _GP =V _DD -V _CM ), so M5 has always been in the weak inversion zone, which can "sense" the change characteristics of parameters such as transconductance and output current of M1 under different process angles and temperatures. Both the source terminal and the body terminal of M5 are connected to a high level V _DDH , and the drain terminal is connected to a high-precision resistor R1. R1 acts as a load on the drain terminal of M5 to feed back the output voltage signal V _BP of the body potential modulator 31 to the input tube M1 of the inverter. At the body end, the entire body potential modulator forms an "inductive feedback" loop for body potential modulation. The other end of R1 is connected to V _DDL (V _CM ≤ V _DDL < V _DD ), and R1 generally takes 20K~200KΩ. We can see that the range of the output voltage signal V _BP is slightly smaller than V _DDL ˜V _DDH . To avoid excessive power supply, V _GP and V _DD can be multiplexed, V _DDL and V _CM can be multiplexed, and V _DDH can be implemented on V _DD with a simple boost circuit or off-chip to achieve more than M1 Bulk Potential Modulation of Inverter Supply Voltage _VDD .

The body potential modulation process in the PMOS body potential modulator 31 is briefly described as follows:

When the process angle is tt (typical), set the output current of the sensing PMOS transistor M5 as I _tt , adjust the size of V _DDH , R1 and M5 so that the output voltage of the PMOS body potential modulator 31 is V _BP =V _CM +I _tt R1≈ V _DD , the body-source voltage of M1 is approximately zero at this time, and the circuit enters a typical working state.

When the process angle is ss, the absolute value of the threshold voltage of M1 becomes larger, which causes the transconductance and the bandwidth to decrease when M1 works in the weak inversion region, and the output current reaches the minimum value at this time. Since the sensing PMOS transistor M5 can "sense" the current change characteristic of M1, the sensing output current of M5 will also reach a minimum value, which is set as I _ss . Therefore, the output voltage V _BP of the body potential modulator 31 = V _CM + I _ss R1 < V _DD , and this voltage signal is fed back to the body terminal of M1, so that the body-source voltage of M1 can be lower than zero, and the absolute value of the threshold voltage can be slightly reduced , when M1 works in the weak inversion region, the transconductance and output current increase, and the negative feedback modulation of M1 parameters is realized. It should be noted that V _BP should not be too small, so as not to cause excessive leakage current due to excessive forward bias of the source-body junction of M1.

When the process angle is ff, the absolute value of the threshold voltage of M1 becomes smaller, causing the transconductance of M1 to increase. At this time, the induced output current of M5 reaches the maximum value, which is set as I _ff . The PMOS body potential modulator 31 feeds back the output voltage V _BP =V _CM +I _ff R1 >V _DD to the body terminal of M1, so that the absolute value of the threshold voltage of M1 is increased, the transconductance and output current are reduced, and the power consumption is reduced.

In fact, by adjusting parameters such as V _DDH , R1 and the size of M5, it is possible to ensure that the PMOS body potential modulator 31 outputs a more suitable V _BP under the three process angles, so that when M1 works in the weak inversion region, the gain, bandwidth and Static power consumption is more consistent.

The NMOS body potential modulator 32 in the new class C inverter is composed of an inductive NMOS transistor M6 and a high-precision resistor R2, wherein the inductive NMOS transistor M6 is symmetrically matched with the layout of the inverter input transistor M2, and the width-to-length ratio is a fixed ratio ( between 1:5 and 1:20), and the gate-source voltage of M6 is the same as the gate-source bias voltage of M2 in the steady state of the weak inversion region (V _GN -GNDL=V _GM -GND), similarly, The sensing NMOS transistor M6 can "sense" the change characteristics of parameters such as transconductance and output current of the inverter NMOS input transistor M2 under different process angles and temperatures. Both the source terminal and the body terminal of M6 are connected to the low-level GNDL, and the drain terminal of the NMOS transistor M6 is connected to a high-precision resistor R2, and R2 serves as a load to feed back the output voltage signal V _BN of the body potential modulator 32 to the body of the inverter input tube M2 terminal for body potential modulation. The other end of R2 is connected to GNDH (GND≤GNDH≤V _CM ), and R2 generally takes 20K～200KΩ. It can be seen that the range of the output voltage signal V _BN is smaller than GNDL˜GNDH. To avoid providing too much power supply, V _GN and GND can be multiplexed, GNDH and V _CM can be multiplexed, and GNDL can be implemented on GND with a simple step-down circuit or off-chip to achieve an M2 body smaller than GND potential modulation. By adjusting parameters such as GNDL, R2, and M6 size, it is possible to ensure that the body potential modulation module 32 outputs a relatively suitable V _BN under the three process angles, so that the gain, bandwidth, and static power consumption of M2 are more consistent when working in the weak inversion region. . It should be noted that V _BN should not be too large, so as not to cause excessive leakage current due to excessive forward bias of M2 body-source junction.

Accompanying drawing 4 is the schematic diagram of the switched capacitor integrator adopting the new class C inverter, which includes the new class C inverter 60 and the prior art sampling capacitor C _S , compensation capacitor C _C , integrating capacitor C _I and switches. The switched capacitor integrator is divided into a sampling phase and an integrating phase in actual work, and is controlled by using p1 and p2 two-phase non-overlapping clocks, as shown in Figure 5, the working mode of the switched capacitor integrator in the present invention is introduced in detail below .

The p1 phase is the sampling phase of the integrator, the switches S1, S4, S5 are closed, and the switches S2, S3 are open. At this time, the input signal IN is sampled to the capacitor C _S , the offset voltage V _OFF of the new type C inverter is sampled to the compensation capacitor C _C , and at the same time, the charge stored in the integration capacitor C _I in the previous phase is transferred to the next phase. stage circuit. In this phase, since the potential of node X at the input terminal of the inverter is only the offset voltage V _OFF of the inverter, which is close to the common-mode level, the two input transistors M1 and M2 both work in the weak inversion region, so the inverter The commutator is always in a stable state with high gain and low power consumption, which meets the requirements of the integrator on the inverter in the sampling phase.

In the p1 phase, the introduction of body potential modulators 31 and 32 in the new type C inverter makes the gain, bandwidth and static power consumption of the inverter more consistent under different process angles, which is beneficial to the switching capacitor integrator in sampling Accurate sampling and transfer of phase charge simultaneously reduces the sensitivity of the integrator's operating frequency and static power consumption to process variations. Moreover, since the input transistors M1 and M2 work in the weak inversion region, the output current level of the entire inverter is only tens of μA or even lower, which greatly reduces the power consumption of the system. It should be noted that the sampling phase has lower requirements on the transconductance and slew rate of the inverter, which is a necessary condition for the high-gain and low-power state application of the Class-C inverter.

The p2 phase is the integral phase of the integrator, the switches S2 and S3 are closed, and the switches S1, S4 and S5 are open. The integration phase includes a slewing phase and a settling phase. At the initial moment of the p2 phase, the integrator enters the establishment phase, and the potential of the lower plate of the sampling capacitor C _S suddenly changes to the common mode level. Since the potential difference between the two ends of the capacitor will not change abruptly, the upper plate of the sampling capacitor C _S (that is, node Y) and the potential of the input node X of the inverter both change abruptly, wherein the potential of X is pulled to -IN+V _OFF . According to the polarity of the input signal, one of the input transistors in the inverter enters the strong inversion region from the previous weak inversion region, which will generate a considerable transient current, while the other one will be turned off immediately. The new type C inverter Entering the state of high slew rate and high current, which just satisfies the requirement of the integrator on the high current output capability of the inverter in the establishment phase. Like the traditional integrator, the large output current of the inverter causes the charge of the sampling capacitor _CS to be transferred to the integrating capacitor C _I rapidly. Due to the negative feedback effect of the integral capacitor C _I , the potential of the input terminal node X of the inverter is gradually restored to V _OFF (the curve of the X potential change at the input terminal X of the type C inverter is shown in Figure 5), and the compensation The capacitor C _C always maintains the potential difference of V _OFF after the sampling phase of p1, so the lower plate (node Y) of the compensation capacitor is compensated as a "virtual ground", and the use of this autozeroing (Autozeroing) technology improves the integrator The establishment accuracy. Finally, the new type C inverter re-enters the stable state of high gain and low power consumption, and the integrator achieves stable establishment. At this time, the integrator enters the hold phase in the p2 phase.

In the p2 phase, the introduction of body potential modulators 31 and 32 in the new type C inverter makes the slew rate and dynamic power consumption of the inverter during the settling process more consistent under different process angles, thereby reducing the switching capacitance integral The sensitivity of indicators such as device settling time, integral accuracy and dynamic power consumption to process deviations improves the stability and robustness of the circuit. At the same time, because the new type C inverter has one input transistor in the cut-off region when the phase inverter is established, and both input transistors work in the weak inversion region during the maintenance phase, the entire integrator can be used at the cost of the lowest static power consumption The ability to obtain a larger slew rate.

It should be noted that the structure of the body potential modulators 31 and 32 is quite simple, and the inductive MOS transistors M5 and M6 therein both work in the weak inversion region, and the power consumption is very low. About 1/10 of the consumption. Therefore, the introduction of the body potential modulator will not significantly increase the power consumption of the circuit, and is completely suitable for working environments with low voltage and low power consumption.

The indicators such as the gain, bandwidth, phase margin and static power consumption of the new class C inverter and the prior art simple type, cascode type C inverter are in the state of high gain and low power consumption (the input tubes are all in the state of Weak inversion region) data comparison under different process corners is shown in Table 1, where the power supply voltage is 1.2V, the width-to-length ratio of M1 and M3 is 180μm/0.35μm, the width-to-length ratio of M2 and M4 is 60μm/0.35μm, M5 The width-to-length ratios of M1 and M6 are 1/8 of M1 and M2 respectively, and the load capacitance of the inverter is 5pF. In Table 1, among the new class C inverters, the class C inverter 30 in the prior art adopts a cascode structure. As can be seen from Table 1, in the state of high gain and low power consumption, the gain, bandwidth and static power consumption of the novel Class C inverter adopted in the present invention are relatively consistent under different process angles, which can ensure that the Class C inverter operates at ss There is sufficient gain and bandwidth at the process corner, and it can make its output current and static power consumption not too large at the ff process corner, while the simple and cascode type C inverters have large deviations, especially The deviation between the two indicators of bandwidth and static power consumption is very large.

Table 1:

In fact, the dynamic characteristics (slew rate, settling time, dynamic power consumption, etc.) of the Class C inverter in the state of high slew rate and high current are also directly related to the transconductance and output current of the input tube of the inverter. Therefore, the introduction of the bulk potential modulators 31 and 32 can also improve the sensitivity of the dynamic characteristics of the class C inverter to process variations. Since the dynamic indicators such as slew rate and settling time of the Class C inverter are closely related to the input bias conditions of the inverter in the state of high slew rate and high current, the input bias voltage of the inverter needs to be provided externally. Therefore, discussing the dynamic characteristics of a Class C inverter must be combined with a specific application environment. We will analyze it in combination with a switched capacitor integrator with a pseudo-differential structure in Embodiment 2. See Table 2 for specific data.

Embodiment two, the circuit structure of the pseudo-differential structure switched capacitor integrator that adopts the new class C inverter proposed by the present invention is shown in accompanying drawing 6, and it has included two described new class C inverters 60 and prior art The common mode feedback circuit 61.

The new class C inverter 60 has a single-ended input and a single-ended output, so it is necessary to use two differentially symmetrical new class C inverters 60 to form a pseudo-differential structure. The pseudo-differential structure can also improve common-mode noise and reduce abnormal linear while increasing the maximum swing of the signal.

The common-mode feedback circuit 61 in the prior art forms common-mode feedback in the forward and negative branches of the integrator respectively. In the p1 phase, S7 and S8 are closed, S6 and S9 are disconnected, and the common-mode feedback capacitor C _M is discharged to the common-mode level; in the p2 phase, S6 and S9 are closed, S7 and S8 are disconnected, and the common-mode feedback capacitor C _M Respectively connect the lower plate of the compensation capacitor C _C and the output end of the inverter to form a common mode feedback. At this time, the common-mode feedback capacitor C _M acts like an output common-mode voltage "detector". Once the detected output common-mode level deviates from the input common-mode level, the "detector" C _M will feed back the deviation to The integrator thus forms a common-mode feedback loop with a gain of C _M /C _I . The value of the common-mode feedback capacitor C _M should not be too small. If C _M is too small, the gain of the feedback loop will be too small, which will lead to inaccurate or even no establishment of the common-mode operating point; the value of the common-mode feedback capacitor C _M should not be too large. If C _M is too large, it will take too long to establish the common-mode operating point. Usually, it is better to take a few hundred fF.

Different from the switched capacitor integrator with a pseudo-differential structure realized by Youngcheol Chae et al., the switched capacitor integrator with a pseudo-differential structure of the present invention adopts a more optimized topology while including a novel class-C inverter 60. In the feedback loop, the original reset switch is replaced by a sample-and-hold branch circuit including an integral capacitor C _I and a related switch S5. In the p1 phase, the charge accumulated in the previous phase of the integrating capacitor C _I is retained, and the output potential of the integrator remains unchanged, and is not reset and cleared; in the p2 phase, the integrating capacitor C _I continues to receive the charge from the sampling capacitor C _S , The output terminal of the integrator starts a new establishment process from the potential of the p1 phase, and does not need to be re-established from the signal ground. If the oversampling rate of the input signal is higher, the potential at the output terminal of the integrator will not change too much in two adjacent clock phases, so the pseudo-differential structure switched capacitor integrator of the present invention relaxes the need for class C inverters (comprising The slew rate and settling time requirements of the new class C inverter and the prior art class C inverter) are particularly important when the clock frequency is relatively high. Since the slew rate and settling time of a Class C inverter are proportional to the size of the input tube of the inverter within a certain range, the topology of the present invention can appropriately reduce the size of the input tube of the inverter, thereby reducing the size of the inverter input tube. Inverter parasitic capacitance, reducing power consumption. Although this topology has been used in differential switched capacitor integrators (traditional operational amplifiers), it is the first time that it is used in combination with Class C inverter technology to form a pseudo differential switched capacitor integrator.

Table 2 is the dynamic index of the new class C inverter, the simple type in the prior art, and the cascode type C inverter in the state of high slew rate and high current, and the results of using these three class C inverters. Comparison of the indicators of the switched capacitor integrator with pseudo-differential structure, where the power supply voltage is 1.2V, the width-to-length ratio of M1 and M3 in the class C inverter is 180μm/0.35μm, the width-to-length ratio of M2 and M4 is 60μm/0.35μm, and the M5 The width and length ratios of M6 and M6 are respectively 1/8 of M1 and M2, the operating frequency of the integrator is 5MHz, the input differential signal amplitude is 0.4V, the capacitive load is 1pF, C _S = _CC =4.8pF, C _I =24pF, C _M =800fF. In Table 2, among the new class C inverters, the prior art class C inverter 30 adopts a cascode structure. It should be noted that the slew rate and settling time of the class C inverter are directly related to the integral capacitor and the load capacitor in the integrator.

Table 2:

It can be seen from Table 2 that in the state of high slew rate and high current, the use of the new type C inverter makes the indicators such as slew rate and maximum dynamic current relatively consistent at different process angles, which ensures the dynamic power of the inverter at ff process angle. The power consumption is not too high, and the slew rate at the ss process corner is avoided too small, thereby greatly reducing the sensitivity of the switching capacitor integrator settling time, integration accuracy and power consumption to process deviations, and the integration accuracy reaches 99.6%. above. In contrast, the switched capacitor integrators using simple and cascode type C inverters have large deviations in each index, and cannot even be fully established in the ss process corner, resulting in the loss of integrator functions.

Claims (4)

1. A switched capacitor integrator comprising Sampling capacitor C _S , compensation capacitor C _C , integrating capacitor C _I , bootstrap NMOS switches S1, NMOS switches S2, S4, and CMOS switches S3, S5; where the bootstrap NMOS switch S1 is located between the signal input terminal and the sampling capacitor C _S ; NMOS switches S2, S4 are respectively located between the upper and lower plates of the sampling capacitor C _S and the common mode level; CMOS switches S3, S5 are respectively located between the upper and lower plates of the compensation capacitor C _C and the upper plate of the integrating capacitor C _I ; It is characterized in that: it also includes The new class C inverter (60) adds a PMOS body potential modulator (31) and an NMOS body potential modulator (32) on the basis of the prior art class C inverter (30), and the power supply voltage V _DD Slightly lower than the sum of the threshold voltages of the two input transistors in the prior art Class C inverter (30); The class C inverter (30) of the prior art is a simple inverter formed by connecting a PMOS transistor and an NMOS transistor in series, or a cascode inverter; The PMOS body potential modulator (31) includes a PMOS transistor M5 and a resistor R1, and the drain of the PMOS transistor M5 is connected to a resistor R1, and the other end of the resistor R1 is connected to a power supply V _DDL ; the NMOS body potential modulator (32 ) includes an NMOS transistor M6 and a resistor R2, and the drain of the NMOS transistor M6 is connected to a resistor R2, and the other end of the resistor R2 is grounded _GNDH ; The switched capacitor integrator is controlled by two-phase non-overlapping clocks of p1 and p2. 2. A pseudo-differential structure switched capacitor integrator, which includes Two common-mode feedback circuits (61) respectively form common-mode feedback in the positive and negative branches of the integrator; Sampling capacitor C _S , compensation capacitor C _C and integral capacitor C _I and NMOS switch, CMOS switch and bootstrap NMOS switch; It is characterized in that: it also includes The two novel C-type inverters (60) according to claim 1 are respectively located in the positive and negative branches of the integrator, and the two novel C-type inverters (60) are differentially symmetrical to form a pseudo-differential structure. 3. pseudo-differential structure switched capacitor integrator according to claim 2, is characterized in that: it adopts to comprise integration capacitance C _I and The sample and hold branch of the relevant switch S5. 4. pseudo differential structure switched capacitor integrator according to claim 2, is characterized in that: common mode feedback circuit (61) comprises The two common-mode feedback capacitors C _M are located between the lower plate of the compensation capacitor C _C and the common mode level at the p1 phase, and respectively located between the lower plate of the compensation capacitor C _C and the positive and negative output terminals of the integrator at the p2 phase; The bootstrap NMOS switches S6 and S9 are respectively located between the lower plate of the common-mode feedback capacitor C _M and the positive and negative output terminals of the integrator; The NMOS switches S7 and S8 are respectively located between the lower plate of the common-mode feedback capacitor C _M and the common-mode level.

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