CN101951236B - Digital variable gain amplifier - Google Patents

Abstract

The invention discloses a digital variable gain amplifier, which utilizes a differential input end switch of an MOS (Metal Oxide Semiconductor) transistor and an MOS transistor diode positive/negative feedback switch to control the network and change equivalent input transconductance and the scale amplification factor of a current mirror so as to realize the function of digital variable gain amplification. The digital variable gain amplifier mainly comprises three parts of a differential input stage transconductance control network, a diode positive/negative feedback control network of the MOS transistor and an output load stage. The invention has the characteristics of stable direct current working point, less chip area, high gain control precision, large and relatively stable broadband, flexible gain control mode, novel thinking, simple circuit structure and the like corresponding to the traditional digital variable gain amplifier.

Description

A Digital Variable Gain Amplifier

technical field

The invention relates to a digital variable gain amplifier.

Background technique

As the key module of radio frequency receiver, variable gain amplifier has been a research hotspot in the research of radio frequency and analog integrated circuits. A variable gain amplifier requires a trade-off between performances such as gain control range, gain control accuracy, bandwidth, linearity, area, and power consumption. In order to have the same transient response and accurately defined settling time of the automatic gain control loop (AGC) under different signal powers, the variable gain amplifier must satisfy the change of the gain relative to the change of the control signal in dB. Variable gain amplifiers are mainly classified into analog variable gain amplifiers (VGA) and digital variable gain amplifiers (PGA). However, the digital control method of the digital variable gain amplifier is easy to realize, the gain control precision is high, and the structure is relatively simple, so it gradually becomes the mainstream.

Digital control gain amplifiers are mainly divided into two categories, namely closed-loop structure and open-loop structure: the closed-loop structure mainly controls the feedback network through digital switches, and changes the feedback factor to achieve digital gain control; the open-loop structure mainly has active degeneration structure, diode load structure, There are several forms of cascode differential peering.

The general closed-loop structure is composed of an operational amplifier and a feedback network. The operational amplifier can be a voltage type operational amplifier or a current type operational amplifier, and the feedback network can be a resistor feedback network or a switched capacitor feedback network. The resistance array or capacitor array of the feedback network is changed through a digital switch, so as to realize a linear dB change of the gain. The gain of the closed-loop structure is determined by the ratio of the resistor or capacitor, and the precision of the proportional resistor and capacitor in the process is high, so the closed-loop structure has the advantages of high gain control accuracy and high linearity. However, the digital variable gain amplifier with a closed-loop structure also brings many problems: firstly, the area of the voltage operational amplifier is large; based on the voltage operational amplifier, after changing the feedback network, the change of the feedback factor will lead to the change of the bandwidth, that is, the larger the gain , the smaller the bandwidth; using a current-mode operational amplifier, although it can ensure that the bandwidth basically does not change with the gain, the power consumption is too large; in addition, using a resistor feedback network, the chip is very large, and the noise performance will also deteriorate; using switched capacitors The feedback network has a complex structure, a large chip area, and needs to be analyzed in discrete time, causing certain difficulties.

The source degeneration structure adopted by the open-loop structure, that is, the differential input stage plus the source degeneration resistance, the transconductance approximately has a linear relationship with the source degeneration resistance, and the output load stage is also composed of resistance; in order to ensure the stability of the output common-mode voltage, generally through the digital switch Change the source degeneration resistor network to achieve digitally variable gain. Although this method has a simple structure and a small area, its linearity is not high, and both linearity and noise will be affected when the source degeneration resistor network is changed.

In order to increase the linearity of the source-degenerated open-loop structure, the most effective method is to increase the equivalent input transconductance through a local feedback. At this time, although the linearity is improved, the problem is that the chip area becomes larger and the power Consumption increases. The diode load structure consists of a differential input stage and a diode load stage, and the gain is the product of the differential input transconductance and the output diode load. In order to ensure that the gain is not affected by the process angle (that is, it is not affected by the change of electron mobility and hole mobility), the type of the load diode MOS transistor needs to be equal to the type of the differential input stage MOS transistor, and a current mirror is needed to realize it. . The transconductance of the differential input stage or the transconductance of the load diode is changed by controlling the proportional amplification factor of the current source or the current mirror through the digital switch, so as to realize the linear change of the gain in dB. This method has simple structure, small area and high gain control accuracy, but the change of the control gain will cause the change of the DC static operating point and cause the problem of excessive power consumption. The cascode amplifier structure consists of a differential input stage, a common-gate amplifier stage, and a load resistor. By changing the common-gate switch network of the common-gate amplifier, the ratio of the small-signal change current of the input stage to the output load stage is changed. , so that the gain can be changed linearly. The circuit with this structure has larger bandwidth, relatively simple structure, less noise, and smaller chip area, and changing the common gate switch network of the common gate amplifier stage has no impact on the DC operating point of the entire circuit. However, since the gain of this circuit structure is the product of the differential input transconductance and the output resistance, and the differential input transconductance is easily changed by process and other factors, and the resistance value of the resistor is also easily changed by process changes, so the gain control accuracy is not high. Linearity degree is also lower.

Contents of the invention

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a digital variable gain amplifier with stable DC operating point, small chip area, high gain control precision, high and relatively constant bandwidth, and simple circuit structure.

Technical scheme: in order to achieve the above object, the technical scheme adopted in the present invention is:

A digital variable gain amplifier (programmable gain amplifier), which uses the MOS transistor differential input switch control network and the MOS transistor diode positive/negative feedback switch control network to change the proportional amplification factor of the equivalent input transconductance and the current mirror, thereby realizing Digital variable gain amplification function, the digital variable gain amplifier includes a differential input stage transconductance control network, a MOS transistor diode positive/negative feedback control network, and an output load stage in three parts:

The differential input stage transconductance control network includes a bias current source Iref, a diode-connected first PMOS transistor and a second PMOS transistor as a tail current source, and six PMOS transistors in the differential input stage, namely the third PMOS transistor, the four PMOS transistors, fifth PMOS transistors, sixth PMOS transistors, seventh PMOS transistors and eighth PMOS transistors;

The MOS transistor diode positive/negative feedback control network includes a first NMOS transistor and a second NMOS transistor connected to a load by a diode, and also includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor ;

The output load stage includes two common-source NMOS seventh NMOS transistors and eighth NMOS transistors, two common-gate NMOS ninth NMOS transistors, a tenth NMOS transistor, two diode-connected PMOS ninth PMOS transistors and Tenth PMOS transistor.

The differential input stage transconductance control network and the MOS transistor diode positive and negative feedback control network constitute the main circuit part of the digital variable gain amplifier. The bias current source Iref and the first PMOS transistor generate a bias voltage to the gate of the second PMOS transistor; the second PMOS transistor acts as a tail current source to provide a bias current for the differential input stage, and the bias current source Iref is connected to the first PMOS transistor. The drain and the gate of the PMOS transistor, the gates of the first PMOS transistor and the second PMOS transistor are connected, and the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply; the third PMOS transistor, the fifth PMOS transistor and the first PMOS transistor The gates of the seven PMOS transistors are connected to the positive stage of the input signal, the sources of the three PMOS transistors are connected together, and connected to the drain of the second PMOS transistor as the tail current, and their substrates are connected to their respective sources Connected; the gates of the fourth PMOS transistor, the sixth PMOS transistor and the eighth PMOS transistor are connected to the negative stage of the input signal, and the sources of these three PMOS transistors are connected together, and connected with the drain of the second PMOS transistor as the tail current are connected to each other, and their substrates are connected to their respective sources; the gate of the first NMOS transistor is connected to the drain to form a diode connection, the source of which is connected to the ground, and the drain is connected to the drain of the third PMOS transistor, and at the same time The drain is connected to the drain of the fifth PMOS transistor through the MOS switch a2+, and connected to the drain of the sixth PMOS transistor through the MOS switch a2-; the gate of the second NMOS transistor is connected to the drain to form a diode connection, and the source Grounded, the drain is connected to the drain of the fourth PMOS transistor, and the drain is connected to the drain of the sixth PMOS transistor through the MOS switch a2+, and connected to the drain of the fifth PMOS transistor through the MOS switch a2-; the third NMOS transistor The gate of the first NMOS transistor is connected to the gate, its drain is connected to the gate of the first NMOS transistor through a MOS switch a1+, and its drain is connected to the gate of the second NMOS transistor through another switch a1-; The gate of the fourth NMOS transistor is connected to the gate of the second NMOS transistor, its drain is connected to the gate of the second NMOS transistor through a MOS switch a1+, and its drain is connected to the gate of the first NMOS transistor through another switch a1- The gate is connected; the source of the fifth NMOS transistor is grounded, the gate is connected to its own drain through a MOS switch a3, and its gate is connected to the drain of the seventh PMOS transistor through another MOS switch a3; the sixth NMOS transistor The source of the source is grounded, the gate is connected to its own drain through a MOS switch a3, and its gate is connected to the drain of the eighth PMOS transistor through another MOS switch a3; the gate of the seventh NMOS transistor is connected to the first NMOS transistor The gate of the NMOS transistor is connected, and its drain is connected with the source of the ninth NMOS transistor; the gate of the eighth NMOS transistor is connected with the gate of the second NMOS transistor, and its drain is connected with the source of the tenth NMOS transistor; The gate of the NMOS transistor is connected to a fixed bias voltage, and its drain is used as the positive terminal of the output stage and the ninth PM The gate of the OS transistor is connected; the gate of the tenth NMOS transistor is connected to a fixed bias voltage, and its drain is connected to the gate of the tenth PMOS transistor as the negative terminal of the output stage; the gate of the ninth PMOS transistor is connected to its drain , forming a diode load connection; the gate of the tenth PMOS transistor is connected to its drain to form a diode load connection; all twelve MOS switches are composed of MOS transistors.

The equivalent transconductance of the differential input stage is controlled by the MOS switch; the on and off of the MOS switch is controlled by the opposite digital signal, that is, the drain of the fourth NMOS transistor is connected to its gate to form a negative feedback diode connection, or the The drain of the fourth NMOS transistor is connected to the drain of the first NMOS transistor to form a positive feedback diode connection; at the same time, it is used as a full differential amplifier to maintain symmetry, and the opposite digital signal is used to control the on and off of the MOS switch, that is, to control the third NMOS The drain of the transistor is connected to its own gate to form a negative feedback diode connection, or the drain of the third NMOS transistor is connected to the drain of the second NMOS transistor to form a positive feedback diode connection.

The gate of the seventh NMOS transistor is connected to the gate of the first NMOS transistor, the gate of the eighth NMOS transistor is connected to the gate of the second NMOS transistor; the gate of the ninth NMOS transistor is connected to a fixed bias voltage, and is connected to the gate of the second NMOS transistor Seven NMOS transistors form a cascode structure; the gate of the tenth NMOS transistor is connected to a fixed bias voltage to form a cascode structure with the eighth NMOS transistor; the gate of the ninth PMOS transistor is connected to the drain, and the source is connected to The power supply forms a diode-connected output load, and its gate and drain are used as the positive terminal of the differential output signal; the gate of the tenth PMOS transistor is connected to the drain, and the source is connected to the power supply to form a diode-connected output load, and its gate , The drain is used as the negative terminal of the differential output signal. The digital MOS switch and the seventh PMOS transistor, the eighth PMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are shunted to ensure the stability of the DC operating point during gain switching, that is, to stabilize the output common-mode voltage.

Beneficial effects: a numerical variable gain amplifier provided by the present invention has a novel idea and a simple structure, adopts a digital MOS switch to control the selection of the feedback polarity of the NMOS diode, and changes the proportional amplification factor of the current mirror, thereby realizing a digital variable gain amplifier. Function. This structure effectively utilizes MOS transistors, the circuit area is greatly reduced, the gain control precision is high, and the bandwidth is large and relatively constant.

Description of drawings

Fig. 1 is a schematic structural diagram of a main circuit of a digital variable gain amplifier of the present invention;

Fig. 2 is a schematic structural diagram of a differential input terminal switch-controlled transconductance circuit of the present invention;

Fig. 3 is the structural schematic diagram of MOS positive and negative feedback diode connection circuit of the present invention;

Fig. 4 is a schematic structural diagram of a traditional digital switch control variable gain amplifier circuit;

Fig. 5 is a simulation diagram of the frequency characteristic of the digital variable gain amplifier of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 1, Figure 2 and Figure 3, it is a schematic structural diagram of a digital variable gain amplifier, which uses the MOS transistor differential input switch control network and the MOS transistor diode positive and negative feedback switch control network to change the equivalent input The proportional amplification factor of the transconductance and the current mirror realizes the digital variable gain amplification function. The digital variable gain amplifier mainly includes a differential input stage transconductance control network, a MOS transistor diode positive/negative feedback control network, and an output load stage three parts:

The differential input stage transconductance control network includes a bias current source Iref, a diode-connected first PMOS transistor MP1 and a second PMOS transistor MP2 as a tail current source, and six PMOS transistors in the differential input stage, that is, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8;

The MOS transistor diode positive/negative feedback control network includes a first NMOS transistor MN1 and a second NMOS transistor MN2 connected to the load, and also includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6;

The output load stage includes two seventh NMOS transistors MN7 and eighth NMOS transistors MN8 of common-source NMOS, a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10 of two common-gate NMOSs, and a second diode-connected PMOS transistor MN10. Nine PMOS transistors MP9 and tenth PMOS transistors MP10.

The differential input stage transconductance control network, the MOS transistor diode positive and negative feedback control network constitute the main circuit part of the digital variable gain amplifier. The bias current source Iref and the first PMOS transistor MP1 generate a bias voltage to the gate of the second PMOS transistor MP2; the second PMOS transistor MP2 acts as a tail current source to provide a bias current for the differential input stage, and its source is connected to the power supply VDD; the gates of the third PMOS transistor MP3, the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 are connected to the positive stage Vin+ of the input signal, and the sources of these three PMOS transistors are connected together, and connected with the first as the tail current source. The drains of the two PMOS transistors PM2 are connected, and their substrates are all connected to the source; the gates of the fourth PMOS transistor MP4, the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8 are connected to the negative stage Vin- of the input signal, these three The sources of the two PMOS transistors are connected together, and are connected with the drain of the second PMOS transistor MP2 as the tail current source, and their substrates are all connected with the source; the gate of the first NMOS transistor MN1 is connected with the drain, A diode connection mode is formed, the source is grounded to GND, the drain is connected to the drain of the third PMOS transistor MP3, and the drain is connected to the drain of the fifth PMOS transistor MP5 through the MOS switch a2+, and connected to the sixth PMOS transistor MP5 through the MOS switch a2- The drain of the transistor MP6 is connected; the gate of the second NMOS transistor MN2 is connected to the drain to form a diode connection, the source is grounded to GND, the drain is connected to the drain of the fourth PMOS transistor MP4, and the drain is passed through the MOS switch a2+ It is connected with the drain of the sixth PMOS transistor MP6, and is connected with the drain of the fifth PMOS transistor MP5 through the MOS switch a2-; the gate of the third NMOS transistor MN3 is connected with the gate of the first NMOS transistor MN1, and its drain is connected through A MOS switch a1+ is connected to the gate of the first NMOS transistor MN1, and its drain is connected to the gate of the second NMOS transistor MN2 through another switch a1-; the gate of the fourth NMOS transistor MN4 is connected to the gate of the second NMOS transistor MN2 The gate is connected, its drain is connected to the gate of the second NMOS transistor MN2 through a MOS switch a1+, and its drain is connected to the gate of the first NMOS transistor MN1 through another switch a1-; the source of the fifth NMOS transistor MN5 The gate is connected to its own drain through a MOS switch a3, and its gate is connected to the drain of the seventh PMOS transistor MP7 through another MOS switch a3; the source of the sixth NMOS transistor MN6 is grounded, and the gate is connected to the drain through another MOS switch a3. A MOS switch a3 is connected to its own drain, and its gate is connected to the drain of the eighth PMOS transistor MP8 through another MOS switch a3; the gate of the seventh NMOS transistor MN7 is connected to the gate of the first NMOS transistor MN1, Its drain is connected to the source of the ninth NMOS transistor MN9; the gate of the eighth NMOS transistor MN8 is connected to the gate of the second NMOS transistor MN2, and its drain is connected to the tenth NMOS transistor MN2. The source of the MOS transistor MN10 is connected; the gate of the ninth NMOS transistor MN9 is connected to a fixed bias voltage Vb, and its drain is used as the output stage positive terminal Vout+, and is connected to the gate of the ninth PMOS transistor MP9; the tenth NMOS transistor The gate of MN10 is connected to a fixed bias voltage Vb, and its drain is used as the negative terminal Vout- of the output stage, and is connected to the gate of the tenth PMOS transistor MP10; the gate of the ninth PMOS transistor MP9 is connected to its drain to form a diode Load connection; the gate of the tenth PMOS transistor MP10 is connected to its drain to form a diode load connection; twelve MOS switches are composed of MOS transistors, and the opening and closing of the MOS switches are controlled by selecting the gate voltage of the MOS switches.

The equivalent transconductance of the differential input stage is controlled by the MOS switch; the on and off of the MOS switch is controlled by the opposite digital signal a1+, a1-, that is, the drain of the fourth NMOS transistor MN4 is controlled to be connected to its own gate to form negative feedback Diode connection, or connect the drain of the fourth NMOS transistor MN4 to the drain of the first NMOS transistor MN1 to form a positive feedback diode connection; at the same time as a full differential amplification, maintaining symmetry, the opposite digital signal a1+, a1- to control the MOS The switch is turned on and off, that is, to control the drain of the third NMOS transistor MN3 to connect to its own gate to form a negative feedback diode connection, or to connect the drain of the third NMOS transistor MN3 to the drain of the second NMOS transistor MN2 to form a positive feedback diode connection. Feedback diode connection.

The gate of the seventh NMOS transistor MN7 is connected to the gate of the first NMOS transistor MN1, the gate of the eighth NMOS transistor MN8 is connected to the gate of the second NMOS transistor MN2; the gate of the ninth NMOS transistor MN9 is connected to a fixed bias Set the voltage Vb to form a cascode structure with the seventh NMOS transistor MN7; the gate of the tenth NMOS transistor MN10 is connected to a fixed bias voltage Vb to form a cascode structure with the eighth NMOS transistor MN6; the ninth PMOS transistor MP9 The gate of the MP10 is connected to the drain, and the source is connected to the power supply VDD to form an output load connected by a diode, and its gate and drain are used as the positive terminal of the differential output signal; the gate of the tenth PMOS transistor MP10 is connected to the drain, and the source Connect to the power supply VDD to form a diode-connected output load, and its gate and drain are used as the negative end of the differential output signal. The stability of the DC operating point during gain switching is ensured by the digital MOS switch and the shunting of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the fifth NMOS transistor MN5, and the sixth NMOS transistor MN6, that is, the stable output common-mode voltage.

The gain control principle of the traditional digital variable gain amplifier is very intuitive. As shown in Figure 4, the voltages of a1 and a2 are directly controlled by switches. When the voltage of a1 is connected to the gate voltage Vb of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 When the a2 voltage is grounded, the proportional amplification factor of the NMOS current mirror increases, and the proportion of the differential input small signal current flowing through the mirror current source to the output load stage becomes larger, so that the gain of the entire amplifier becomes larger. When the voltage of a1 is grounded, and the voltage of a2 is connected to the gate voltage vb of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10, the proportional amplification factor of the NMOS current mirror becomes smaller, and the gain of the entire amplifier becomes smaller. This method has simple structure, simple gain control method, and stable output common-mode voltage. But it also brings a series of problems. First, the ninth NMOS transistor MN9 of the NMOS transistor, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14 is directly connected with the output stage, and there is a large amount of parasitic capacitance at this time, so that the bandwidth of the amplifier becomes smaller. In addition, the gain control range of this structure is small. If the gain control range is increased, more current mirror arrays need to be added. At this time, the power consumption is too high, the chip area becomes larger, and the bandwidth further deteriorates.

In order to solve these problems, the differential input stage transconductance control network shown in Figure 2 and the positive and negative feedback control network of the MOS transistor diode shown in Figure 3 can be used. In Figure 2, the drain connection of the differential input stage is controlled by the MOS switch and the opposite digital control signal a2+, a2-, which can be a negative feedback connection to increase the equivalent input transconductance, or a positive feedback connection , so that the equivalent input transconductance is reduced, and when there is no need to increase or decrease the equivalent input transconductance, it is necessary to shunt through a group of differential input PMOS, so as to ensure that the overdrive voltage of the differential input is equal under different gain control modes , the DC operating point is stabilized by the output stage. In FIG. 3 , the connection mode of the NMOS diode is controlled by the MOS switch and the opposite digital control signals a1+ and a1- whether it is a positive feedback connection or a negative feedback connection. The positive feedback connection mode can make the proportional amplification factor of the current mirror larger, and the negative feedback connection mode can make the proportional amplification factor of the current mirror smaller. The overall circuit is shown in Figure 1. Through the control of the differential input stage transconductance control network and the MOS transistor diode positive and negative feedback control network through digital signals, a wide range of gain control can be achieved. The common gate transistor MN9 of the output stage , MN10 increases the output impedance of the current mirror at the same time, and plays the role of isolation. When the gain is switched, the parasitic capacitance of the output stage does not change, so the 3dB bandwidth changes relatively little. In addition, the seventh PMOS transistor MP7 , the eighth PMOS transistor MP8 , the fifth NMOS transistor MN5 , the sixth NMOS transistor MN6 and the switch ensure the stability of the DC operating point of the whole circuit when the gain is switched. The gain of the entire amplifier is only related to the PMOS transconductance of the differential input pole, the PMOS transconductance of the output diode connection and the proportional current mirror amplification factor controlled by the digital switch. In order to further improve the gain control range, a differential input stage transconductance control network and a MOS transistor diode positive/negative feedback control network can be added. As long as the negative feedback is greater than the positive feedback, there will be no loop stability issues. Figure 5 shows the simulation results under CMOS process conditions, it can be seen that the gain control accuracy is better and the 3dB bandwidth is higher.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also possible. It should be regarded as the protection scope of the present invention.

Claims (2)

1. digital variable gain amplifier is characterized in that: described amplifier comprise differential input stage mutual conductance control network, MOS transistor diode just/negative feedback control network and output load stage three parts:

Described differential input stage mutual conductance control network comprises bias current sources Iref, a PMOS transistor (MP1), the 2nd PMOS transistor (MP2), the 3rd PMOS transistor (MP3), the 4th PMOS transistor (MP4), the 5th PMOS transistor (MP5), the 6th PMOS transistor (MP6), the 7th PMOS transistor (MP7) and the 8th PMOS transistor (MP8);

Described MOS transistor diode just/the negative feedback control network comprises the first nmos pass transistor (MN1), the second nmos pass transistor (MN2), the 3rd nmos pass transistor (MN3), the 4th nmos pass transistor (MN4), the 5th nmos pass transistor (MN5) and the 6th nmos pass transistor (MN6);

Described output load stage comprises the 7th nmos pass transistor (MN7), the 8th nmos pass transistor (MN8), the 9th nmos pass transistor (MN9), the tenth nmos pass transistor (MN10), the 9th PMOS transistor (MP9), the tenth PMOS transistor (MP10);

In the described differential input stage mutual conductance control network, bias current sources Iref connects the drain and gate of a PMOS transistor (MP1), the grid of the one PMOS transistor (MP1) and the 2nd PMOS transistor (MP2) is connected, and the source electrode of a PMOS transistor (MP1) and the 2nd PMOS transistor (MP2) connects power supply (VDD); The grid of the 3rd PMOS transistor (MP3), the 5th PMOS transistor (MP5) and the 7th PMOS transistor (MP7) connects the positive level (Vin+) of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with the drain electrode of the 2nd PMOS transistor (MP2), their substrate all links to each other with separately source electrode; The grid of the 4th PMOS transistor (MP4), the 6th PMOS transistor (MP6) and the 8th PMOS transistor (MP8) connects the negative level (Vin-) of input signal, the source electrode of these three PMOS pipes is connected together, and link to each other with the drain electrode of the 2nd PMOS transistor (MP2), their substrate all links to each other with separately source electrode; The grid of the first nmos pass transistor (MN1) links to each other with drain electrode, form the diode connected mode, its source ground (GND), drain electrode links to each other with the drain electrode of the 3rd PMOS transistor (MP3), simultaneously drain electrode links to each other with the drain electrode of the 5th PMOS transistor (MP5) by MOS switch a2+, links to each other with the drain electrode of the 6th PMOS transistor (MP6) by MOS switch a2-; The grid of the second nmos pass transistor (MN2) links to each other with drain electrode, form the diode connected mode, source ground (GND), drain electrode links to each other with the drain electrode of the 4th PMOS transistor (MP4), simultaneously drain electrode links to each other with the drain electrode of the 6th PMOS transistor (MP6) by MOS switch a2+, links to each other with the drain electrode of the 5th PMOS transistor (MP5) by MOS switch a2-; The grid of the 3rd nmos pass transistor (MN3) links to each other with the grid of the first nmos pass transistor (MN1), its drain electrode links to each other with the grid of the first nmos pass transistor (MN1) by a MOS switch a1+, and its drain electrode links to each other with the grid of the second nmos pass transistor (MN2) by another one switch a1-; The grid of the 4th nmos pass transistor (MN4) links to each other with the grid of the second nmos pass transistor (MN2), its drain electrode links to each other with the grid of the second nmos pass transistor (MN2) by a MOS switch a1+, and its drain electrode links to each other with the grid of the first nmos pass transistor (MN1) by another one switch a1-; The source ground of the 5th nmos pass transistor (MN5), grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the drain electrode of the 7th PMOS transistor (MP7) by another one MOS switch a3; The source ground of the 6th nmos pass transistor (MN6), grid links to each other with the drain electrode of oneself by a MOS switch a3, and its grid links to each other with the drain electrode of the 8th PMOS transistor (MP8) by another one MOS switch a3; The grid of the 7th nmos pass transistor (MN7) links to each other with the grid of the first nmos pass transistor (MN1), and its drain electrode links to each other with the source electrode of the 9th nmos pass transistor (MN9); The grid of the 8th nmos pass transistor (MN8) links to each other with the grid of the second nmos pass transistor (MN2), and its drain electrode links to each other with the source electrode of the tenth nmos pass transistor (MN10); The grid of the 9th nmos pass transistor (MN9) connects fixing bias voltage (Vb), and its drain electrode links to each other as the grid of output stage anode (Vout+) with the 9th PMOS transistor (MP9); The grid of the tenth nmos pass transistor (MN10) connects fixing bias voltage (Vb), and its drain electrode links to each other as the grid of output stage negative terminal (Vout-) with the tenth PMOS transistor (MP10); The grid of the 9th PMOS transistor (MP9) links to each other with its drain electrode, forms diode load and connects; The grid of the tenth PMOS transistor (MP10) links to each other with its drain electrode, forms diode load and connects; 12 MOS switches all are made of metal-oxide-semiconductor.

2. a kind of digital variable gain amplifier according to claim 1, it is characterized in that: the grid of the 7th nmos pass transistor (MN7) links to each other with the grid of the first nmos pass transistor (MN1), and the grid of the 8th nmos pass transistor (MN8) links to each other with the grid of the second nmos pass transistor (MN2); The grid of the 9th nmos pass transistor (MN9) connects fixing bias voltage (Vb), forms cascodes with the 7th nmos pass transistor (MN7); The grid of the tenth nmos pass transistor (MN10) connects fixing bias voltage (Vb) and forms cascodes with the 8th nmos pass transistor (MN6); The grid of the 9th PMOS transistor (MP9) links to each other with drain electrode, and source electrode connects power supply (VDD), forms the output loading that diode connects, and its grid, drains as the anode of differential output signal; The grid of the tenth PMOS transistor (MP10) links to each other with drain electrode, and source electrode connects power supply (VDD), forms the output loading that diode connects, and its grid, drains as the negative terminal of differential output signal.

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