CN102386907B - Integrating circuit - Google Patents

Abstract

The invention discloses an integrating circuit, which utilizes a first capacitor and a first switching unit to sample an input signal in a time-sharing way, and then utilizes a second capacitor with larger capacitance value to carry out charge distribution with the first capacitor so as to store sampled voltage. While the charge is distributed, the integrating circuit conducts the voltage originally stored on the second capacitor to one end of the first capacitor originally coupled to the grounding end so as to improve the voltage level of the first capacitor, and the second capacitor can obtain a corresponding voltage rising value. Therefore, the integrating circuit can obtain higher accuracy and linearity.

Description

Integrator circuit

technical field

The present invention relates to an integrating circuit, and in particular to an integrating circuit which utilizes the charge distribution theory of capacitance to achieve high resolution and low phase difference.

Background technique

Integrators are common analog circuits that are mainly used for integral operations in mathematics. A typical voltage integrator is implemented using a voltage divider circuit composed of resistors and capacitors. Since the current passing through the capacitor is related to the speed of voltage change, that is, the result of the voltage being differentiated by time, the divided voltage across the capacitor can be regarded as the integral result of the input voltage, and the divided voltage across the resistor can be regarded as the input voltage The differential result. In the prior art, operational amplifiers are often used in integrating circuits or differential circuits to achieve the effect of adjusting input impedance and output impedance.

Another existing low-frequency integrator uses an analog-to-digital converter (Analog to Digital Converter, ADC) to convert the signal into a digital signal and then integrates it, but the accuracy of the circuit integration is limited by the resolution of the ADC . Although the use of a high-resolution ADC can improve the accuracy of the integrator, it will increase the cost of circuit design. In addition, in the prior art, it is necessary to use a low-pass filter to filter out the high frequency to obtain the DC component and then integrate it. However, the lower the frequency component is to be filtered out, the larger the capacitor value will be required, which will increase the cost. Phase drop is also produced and can cause system controlled low frequency oscillations.

Contents of the invention

The invention provides an integrating circuit, which utilizes the charge distribution principle of a capacitor to realize a low-frequency hybrid integrating circuit, which not only has high resolution, but also does not cause a large phase difference, and can achieve low-cost and high-efficiency effects.

The present invention proposes an integrating circuit, which includes a first energy storage element, a first switching unit, a second switching unit and a second energy storage element. The first energy storage element is coupled between a first end and a second end. The first switching unit is coupled between the first terminal and an input terminal and between the second terminal and the ground terminal, and is used for selectively conducting the first terminal and the input terminal and selectively conducting the second terminal and the ground terminal. The second switching unit is coupled to the first terminal, the second terminal and a third terminal, and is used for selectively conducting the first terminal and the third terminal and selectively conducting the voltage of the first terminal to the second terminal. The second energy storage element is coupled between the third end and the ground end.

In an embodiment of the present invention, when the first switching unit conducts the first terminal and the input terminal and conducts the second terminal and the ground terminal, the second switching unit does not conduct the first terminal and the third terminal.

In an embodiment of the present invention, when the second switching unit conducts the first terminal and the third terminal and conducts the voltage of the first terminal to the second terminal, the first switching unit does not conduct the first terminal and the input terminal and The second end and the ground end are not conducted.

In an embodiment of the present invention, the first switching unit includes a first switch and a second switch. The first switch is coupled between the first terminal and the input terminal, and the second switch is coupled between the second terminal and the ground terminal. Wherein, the first switch and the second switch are controlled by a first control signal.

In an embodiment of the present invention, the second switching unit includes a third switch, a first unity gain amplifier and a fourth switch. The third switch is coupled between the first terminal and the third terminal, and the input of the first unit gain amplifier is coupled to the first terminal. The fourth switch is coupled between the output of the first unit gain amplifier and the second terminal. Wherein the third switch and the fourth switch are controlled by a second control signal.

In an embodiment of the present invention, when the first control signal is enabled, the second control signal is disabled.

In an embodiment of the present invention, the integration circuit further includes a fifth switch coupled between the third terminal and the ground terminal. The first energy storage element is a first capacitor, the second energy storage element is a second capacitor, and the capacitance of the first capacitor is smaller than the capacitance of the second capacitor.

In an embodiment of the present invention, the integration circuit further includes an output buffer unit coupled between the third terminal and an output terminal. The output buffer unit includes a second unit gain amplifier, a sixth switch, a third unit gain amplifier and a third capacitor. The input of the second unit gain amplifier is coupled to the third end, and one end of the sixth switch is coupled to the output of the second unit gain amplifier. The input of the third unit gain amplifier is coupled to the other end of the sixth switch, and the output of the third unit gain amplifier is coupled to the output end. The third capacitor is coupled between the input of the third unit gain amplifier and the ground terminal.

The beneficial effect of the present invention is that, based on the above, the integrating circuit proposed by the present invention uses the capacitor charge distribution principle to compress and store the time-division sampled voltage in the capacitor, thereby improving the linearity of the integrating circuit. In addition, compared with the existing integrator, the accuracy of the integrating circuit of the present invention is not limited by the resolution of the ADC and there is no problem of excessive phase difference, and can achieve the goal of low cost and high performance.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a functional block diagram of an integrating circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of an integrating circuit according to this embodiment.

FIG. 3 is a schematic diagram of waveforms according to this embodiment.

Wherein, the reference signs are explained as follows:

100, 200: integrating circuit

110: the first switching unit

120: the first energy storage element

130: second switching unit

140: Second energy storage element

150: output buffer unit

310～360: waveform

T1～T3: first to third terminal

GND: ground terminal

TIN: input terminal

TOUT: output terminal

SW1～SW6: the first to sixth switches

C1～C3: first to third capacitors

GA1～GA3: first to third unity gain amplifiers

CON1~CON3: first to third control signals

VIN: input signal

VOUT: output signal

Detailed ways

Please refer to FIG. 1 , which is a functional block diagram of an integrating circuit according to an embodiment of the present invention. The integrating circuit 100 includes a first switching unit 110 , a first energy storage element 120 , a second switching unit 130 , a second energy storage element 140 and an output buffer unit 150 . The first energy storage element 120 is coupled between the first terminal T1 and the second terminal T2, the first switching unit 110 is coupled between the first terminal T1 and the input terminal TIN, and is coupled between the second terminal T2 and the ground terminal GND, It is used to selectively connect the first terminal T1 with the input terminal TIN and selectively connect the second terminal T2 with the ground terminal GND. The second switching unit 130 is coupled to the first terminal T1, the second terminal T2 and the third terminal T3, and is used for selectively conducting the first terminal T1 and the third terminal T3 and selectively conducting the voltage of the first terminal T1 to the third terminal T3. Two-terminal T2. The second energy storage element 140 is coupled between the third terminal T3 and the ground terminal GND. The output buffer unit 150 is coupled between the third terminal T3 and the output terminal TOUT.

Wherein, when the first switching unit 110 is connected to the first terminal T1 and the input terminal TIN and is connected to the second terminal T2 and the ground terminal GND, the second switching unit 130 is not connected to the first terminal T1 and the third terminal T3. When the second switching unit 130 conducts the first terminal T1 and the third terminal T3 and conducts the voltage of the first terminal T1 to the second terminal T2, the first switching unit 110 does not conduct the first terminal T1 and the input terminal TIN and does not The second terminal T2 is connected to the ground terminal GND. The first switching unit 110 is mainly used to determine the sampling rate of the input signal VIN. Every time the first terminal T1 is connected to the input terminal TIN and the second terminal T2 is connected to the ground terminal GND, the input signal VIN is sampled once. The voltage of the input signal VIN will be stored in the first energy storage element 120, and then the first switching unit 110 will close the conduction path, and then the second switching unit 130 will conduct the third terminal T3 and the first terminal T1, and turn the second switching unit 130 on. The voltage of the terminal T1 is transmitted to the second terminal T2 to boost the reference voltage of the first energy storage element 120 . At this time, the charge in the first energy storage element 120 will be distributed in the first energy storage element 120 and the second energy storage element 140 to boost the voltage of the third terminal T3. In this way, the effect of voltage integration can be achieved.

In addition, it is worth noting that the first switching unit 110 and the second switching unit 130 are mainly used to switch the conduction path, which can be realized by using multiple switches or multiplexers or switching elements, and this embodiment is not limited . The first energy storage element 120 and the second energy storage element 140 can be realized by a single capacitor or multiple capacitors, which is not limited in this embodiment. The output buffer unit 150 is mainly used to adjust the output impedance, and can be formed by a buffer circuit or a unity gain amplifier, which is not limited in this embodiment.

Next, the implementation details of the integration circuit of this embodiment will be further described. Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a diagram of the integration circuit according to this embodiment. In the integrating circuit 200 shown in FIG. 2 , the first switching unit 110 includes a first switch SW1 and a second switch SW2 , and the second switching unit 130 includes a third switch SW3 and a fourth switch SW4 and a first unity gain amplifier GA1 . The first energy storage element 120 is implemented by a first capacitor C1, and the second energy storage element 140 is implemented by a second capacitor C2. The output buffer unit 150 includes a second unity gain amplifier GA2, a third unity gain amplifier GA3, a sixth switch SW6 and a third capacitor C3. The integration circuit 200 further includes a fifth switch SW5 coupled between the third terminal T3 and the ground terminal GND for guiding the charges in the second capacitor C2 to the ground terminal GND to reset the integration circuit 200 .

The first capacitor C1 is coupled between the first terminal T1 and the second terminal T2, and the second capacitor C2 is coupled between the third terminal and the ground terminal GND. The first switch SW1 is coupled between the first terminal T1 and the input terminal TIN, and the second switch SW2 is coupled between the second terminal T2 and the ground terminal GND. The third switch SW3 is coupled between the first terminal T1 and the third terminal T3, and the input of the first unity gain amplifier GA1 is coupled to the first terminal T1. The fourth switch SW4 is coupled between the output of the first unit gain amplifier GA1 and the second terminal T2. The second unity gain amplifier GA2 is coupled between the third terminal T3 and the sixth switch SW6 , and the third unity gain amplifier GA3 is coupled between the other terminal of the sixth switch SW6 and the output terminal TOUT. Wherein, the first to third unit gain amplifiers GA1 - GA3 are realized by negative feedback operational amplifiers, but this embodiment is not limited thereto. In addition, it should be noted that the coupling relationship between the above elements includes direct or indirect or parallel electrical connection, as long as the required electrical signal transmission function can be achieved, the present embodiment is not limited.

The first switch SW1 and the second switch SW2 are controlled by the first control signal CON1 , and the third switch SW3 and the fourth switch SW4 are controlled by the second control signal CON2 . When the first control signal CON1 is enabled, the first switch SW1 and the second switch SW2 are turned on, otherwise they are not turned on. When the second control signal CON2 is enabled, the third switch SW3 and the fourth switch SW4 are turned on, otherwise they are not turned on. Please refer to FIG. 3 for the waveforms of the first control signal CON1 and the second control signal CON2 . FIG. 3 is a schematic diagram of the waveforms according to this embodiment. Please refer to FIG. 2 and FIG. 3 at the same time. During the integration operation, the first control signal CON1 is used to control the sampling frequency, and each enable (such as waveform 310) will change the input signal VIN during its enable period. The voltage is stored in the first capacitor C1. When the first control signal CON1 is enabled, the second control signal CON2 is disabled. After the first control signal CON1 is disabled, the second control signal CON2 is then enabled (such as waveform 340), so that the charge in the first capacitor C1 can be distributed to the second capacitor C2 to compress the voltage of the input signal VIN stored in the second capacitor C2.

When the second control signal CON2 is enabled, the third switch SW3 and the fourth switch SW4 are turned on, so the voltage of the third terminal T3 is transmitted to the second terminal T2 to push up the DC level of the first capacitor C1, so that The voltage difference between the two ends of the first capacitor C1 can be applied on the original DC level (voltage) of the third terminal T3. Then, the charge distribution principle of the capacitor is used to allow the second capacitor C2 to obtain a corresponding voltage rise value, thereby achieving the effect of integration. The above-mentioned voltage rise value of the second capacitor C2 can be regarded as a compressed value of the input signal VIN, and its ratio is related to the capacitance values of the first capacitor C1 and the second capacitor C2. Assuming that the capacitance value of the first capacitor C1 is represented by C1, and the capacitance value of the second capacitor C2 is represented by C2, after the first control signal CON1 is enabled, the charge stored in the first capacitor C1 can be expressed as formula (1) , and after the second control signal CON2 is enabled, the voltage rise of the second capacitor C2 is as shown in formula (2).

Q＝C1×V1＝C2×V1′---------Formula (1)

${V1}^{\′}=\frac{C1}{C2}\×V1$ --------------- Formula (2)

Wherein, V1 in the above formula represents the voltage value of the input signal VIN when it is extracted, and V1' represents the voltage rise value at the third terminal T3 after distribution. That is to say, after the second control signal CON2 is enabled, the voltage at the third terminal T3 will increase due to charge distribution, and the increased voltage difference is V1'. It can be seen from the above formula that V1' has a certain proportional relationship with V1, and the ratio is related to the capacitance values C1 and C2. Therefore, by controlling the timing of the first control signal CON1, the effect of time-division sampling of the input signal VIN can be achieved, while controlling the timing of the second control signal CON2 will redistribute the charge to the second capacitor C2, so that the voltage of the third terminal T3 Get the corresponding rising value to achieve the effect of integral. On the other hand, if the input signal VIN is negative, then V1 is negative, which will cause the voltage difference across the second capacitor C2 to decrease, which also has an integral result. After the description of the above-mentioned embodiments, those skilled in the art should be able to infer the implementation manner thereof, and details are not repeated here.

In addition, the capacitance value of the first capacitor C1 in this embodiment will be smaller than the capacitance value of the second capacitor C2, for example, 100C1=C2, so as to prevent the second capacitor C2 from generating an excessively high voltage during the integration process and exceeding the normal voltage of the circuit. working interval, but this embodiment is not limited to the above proportional relationship.

In addition, the fifth switch SW5 can be used to reset the integration circuit 200. When the third control signal CON3 is enabled (please refer to the waveform 360 in FIG. 3), the charge in the second capacitor C2 will be guided to the ground terminal GND to reset Integrator circuit 200. Therefore, before performing the integral operation, the third control signal CON3 is first enabled to reset the voltage of the third terminal T3 to zero.

In the output buffer unit 150, the second unity gain amplifier GA2 conducts the voltage of the third terminal T3 to the third capacitor C3, and the sixth switch SW6 is used to maintain the charge stored in the third capacitor C3 to avoid leakage current occurs. The third unit gain amplifier GA3 outputs the integration result to the output terminal TOUT to generate the output signal VOUT. The output signal VOUT is proportional to the integration result of the input signal VIN, and the proportional relationship is related to the capacitance values of the first capacitor C1 and the second capacitor C2. After the description of the above-mentioned embodiments, those skilled in the art should be able to infer the calculation method, and details are not repeated here.

To sum up, the present invention utilizes the principle of charge distribution of capacitors to implement a low-frequency integrating circuit. The integrating circuit can compress and store time-sampled voltages to achieve the effect of a linear integrator. In addition, the present invention does not need to use an ADC to achieve the integration effect, which can effectively reduce the circuit cost and achieve more accurate integration results.

Although the preferred embodiments of the present invention have been disclosed above, the present invention is not limited to the above embodiments, and any person skilled in the art may make some modifications and changes without departing from the disclosed scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (9)

1. An integrating circuit, characterized in that the integrating circuit comprises: a first energy storage element coupled between a first end and a second end; A first switching unit, coupled between the first terminal and an input terminal and coupled between the second terminal and a ground terminal, the first switching unit includes a first switch for selectively conducting the first terminal selectively conducting with the input terminal and the second terminal and the ground terminal with a second switch; A second switching unit, coupled to the first terminal, the second terminal and a third terminal, for selectively conducting the first terminal and the third terminal and selectively conducting the voltage of the third terminal to the the second end; and a second energy storage element coupled between the third terminal and the ground terminal; Wherein, the second switching unit includes: a third switch, coupled between the first terminal and the third terminal; a first unity gain amplifier, the input of the first unity gain amplifier is coupled to the first end; and A fourth switch is coupled between the output of the first unit gain amplifier and the second terminal. 2. The integrating circuit according to claim 1, wherein when the first switching unit connects the first terminal and the input terminal and connects the second terminal and the ground terminal, the second switching unit does not The first terminal and the third terminal are connected. 3. The integrating circuit according to claim 1, wherein when the second switching unit conducts the first terminal and the third terminal and conducts the voltage of the third terminal to the second terminal, the first switching unit The unit does not conduct the first end and the input end and does not conduct the second end and the ground end. 4. The integrating circuit as claimed in claim 1, characterized in that the first switch, coupled between the first terminal and the input terminal; and The second switch is coupled between the second terminal and the ground terminal. 5. The integrating circuit according to claim 4, wherein the first switch and the second switch are controlled by a first control signal, and the third switch and the fourth switch are controlled by a second control signal . 6. The integrating circuit as claimed in claim 5, wherein when the first control signal is enabled, the second control signal is disabled. 7. The integrating circuit according to claim 1, characterized in that the integrating circuit further comprises: A fifth switch is coupled between the third end and the ground end. 8. The integrating circuit according to claim 1, wherein the first energy storage element is a first capacitor, the second energy storage element is a second capacitor, and the capacitance of the first capacitor is smaller than that of the first capacitor. The capacitance value of the second capacitor. 9. The integrating circuit according to claim 1, characterized in that the integrating circuit further comprises: An output buffer unit, coupled between the third end and an output end, the output buffer unit includes: a second unity gain amplifier, the input of the second unity gain amplifier is coupled to the third end; a sixth switch, one end of the sixth switch is coupled to the output of the second unity gain amplifier; a third unit gain amplifier, the input of the third unit gain amplifier is coupled to the other end of the sixth switch, and the output of the third unit gain amplifier is coupled to the output end; and A third capacitor is coupled between the input of the third unit gain amplifier and the ground terminal.

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