CN103294099B - Second-order curvature temperature-compensation circuit for band-gap reference - Google Patents
Second-order curvature temperature-compensation circuit for band-gap reference Download PDFInfo
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Abstract
本发明涉及一种适用于带隙基准的二阶曲率温度补偿电路。本发明针对现有带隙基准的二阶曲率温度补偿电路不适用于一些特定工艺的问题,公开了一种新型的二阶曲率温度补偿电路。本发明的技术方案是,用于带隙基准的二阶曲率温度补偿电路,包括,PMOS管:M15、M16、M17、M18、M19,NMOS管:M20、M21。其中,M15的栅极连接经过部分一阶温度补偿的带隙基准电压信号,并作为所述二阶曲率补偿电路的输入端。M16的栅极作为所述二阶曲率补偿电路的输出端。本发明由工作在亚阈值区的PMOS管M15和M16实现电压叠加,在已经部分一阶温度补偿的带隙基准电压的基础上再叠加一个同时具有一阶和二阶温度补偿效果的电压量,从而产生最终的二阶曲率补偿带隙基准输出电压。
The invention relates to a second-order curvature temperature compensation circuit suitable for a bandgap reference. Aiming at the problem that the second-order curvature temperature compensation circuit of the existing bandgap reference is not suitable for some specific processes, the invention discloses a novel second-order curvature temperature compensation circuit. The technical solution of the present invention is that the second-order curvature temperature compensation circuit used for the bandgap reference includes PMOS transistors: M15, M16, M17, M18, M19, and NMOS transistors: M20 and M21. Wherein, the gate of M15 is connected to the bandgap reference voltage signal after part of the first-order temperature compensation, and serves as the input end of the second-order curvature compensation circuit. The gate of M16 serves as the output terminal of the second-order curvature compensation circuit. In the present invention, voltage superposition is realized by the PMOS transistors M15 and M16 working in the sub-threshold region, and a voltage quantity with both first-order and second-order temperature compensation effects is superimposed on the basis of the bandgap reference voltage that has been partially first-order temperature compensated. This produces the final second-order curvature-compensated bandgap reference output voltage.
Description
技术领域technical field
本发明涉及集成电路技术,特别涉及一种适用于带隙基准的二阶曲率温度补偿电路。The invention relates to integrated circuit technology, in particular to a second-order curvature temperature compensation circuit suitable for bandgap references.
背景技术Background technique
基准源是电子系统中非常重要的一个模块,其特性直接关系到系统的整体性能。因此高性能基准源在众多应用中扮演着重要的角色,其覆盖了模拟电路、数字电路和混合信号电路领域。在众多的基准源中,带隙基准源使用最为广泛。为了提高带隙基准的输出精度,学术界提出了多种高阶曲率补偿方法,例如平方项的温度补偿、指数型温度补偿、分段线性补偿和与温度相关的电阻比例补偿等。The reference source is a very important module in the electronic system, and its characteristics are directly related to the overall performance of the system. Therefore, high-performance reference sources play an important role in many applications, covering the fields of analog circuits, digital circuits and mixed-signal circuits. Among the many reference sources, the bandgap reference source is the most widely used. In order to improve the output accuracy of the bandgap reference, a variety of high-order curvature compensation methods have been proposed in academia, such as square-term temperature compensation, exponential temperature compensation, piecewise linear compensation, and temperature-dependent resistance ratio compensation.
现有技术的带隙基准二阶曲率温度补偿电路,通常都是在经过一阶温度补偿(或部分一阶温度补偿)基础上,叠加二阶温度补偿项来实现的,典型电路结构如图1所示。其中图1a和b分别为两种常用电路结构形式,包括电流源、电阻R以及三极管T1、T2等。其中电流源可以是正温电流源和/或负温电流源,通常由饱含PMOS管(P型场效应晶体管)、NMOS管(N型场效应晶体管)和双极型三极管的电路构成。图1a和b示出了两种采用正温电流源的二阶曲率温度补偿电路,正温电流源产生的电流分别为I1和I2,且I1=c1T,I2=c2T。图1所示电路可以实现指数型二阶曲率温度补偿。其输出基准电压VREF的表达式为The bandgap reference second-order curvature temperature compensation circuit in the prior art is usually realized by superimposing second-order temperature compensation items on the basis of first-order temperature compensation (or part of first-order temperature compensation). The typical circuit structure is shown in Figure 1 shown. Figures 1a and b show two commonly used circuit structures, including a current source, a resistor R, and transistors T 1 and T 2 . The current source can be a positive temperature current source and/or a negative temperature current source, and is usually composed of a circuit including a PMOS transistor (P-type field effect transistor), an NMOS transistor (N-type field effect transistor) and a bipolar transistor. Figure 1a and b show two second-order curvature temperature compensation circuits using a positive temperature current source. The currents generated by the positive temperature current source are I 1 and I 2 respectively, and I 1 =c 1 T, I 2 =c 2 T. The circuit shown in Figure 1 can realize exponential second-order curvature temperature compensation. The expression of its output reference voltage VREF is
其中,VBE1是NPN型三极管T1基极和发射极之间的电压,c1、c2是与温度无关的常数,T是绝对温度,β∞是共发射极电流增益的最大值,ΔEG是发射极的带隙缩小因子,k是玻耳兹曼常数。上式中c1RT项用于对三极管BE结电压做一阶温度补偿,项实现对三极管BE结电压的指数型二阶曲率温度补偿。该电路虽然结构简单,但它需要使用电阻,而且对工艺要求高,必须使用双极型工艺或BiCMOS工艺才能实现。电路适用范围和灵活性受到极大限制。Among them, V BE1 is the voltage between the base and emitter of NPN transistor T 1 , c 1 and c 2 are constants independent of temperature, T is the absolute temperature, β ∞ is the maximum value of common emitter current gain, ΔE G is the bandgap reduction factor of the emitter, and k is the Boltzmann constant. The term c 1 RT in the above formula is used for first-order temperature compensation of the BE junction voltage of the triode, The term realizes the exponential second-order curvature temperature compensation for the BE junction voltage of the triode. Although the structure of this circuit is simple, it requires the use of resistors, and has high requirements on the process, so it must be realized by using a bipolar process or a BiCMOS process. Circuit scope and flexibility are greatly limited.
发明内容Contents of the invention
本发明所要解决的技术问题,就是针对现有带隙基准的二阶曲率温度补偿电路需要使用电阻,不适用于一些特定工艺(没有电阻或电阻模型不精确的工艺,例如标准数字CMOS工艺)的问题,提供一种新型的二阶曲率温度补偿电路。The technical problem to be solved by the present invention is that the second-order curvature temperature compensation circuit for the existing bandgap reference needs to use resistors, which is not suitable for some specific processes (processes without resistance or inaccurate resistance models, such as standard digital CMOS processes) To solve the problem, a new type of second-order curvature temperature compensation circuit is provided.
本发明解决所述技术问题,采用的技术方案是,用于带隙基准的二阶曲率温度补偿电路,包括,PMOS管:M15、M16、M17、M18、M19,NMOS管:M20、M21;其中,M15的栅极连接经过部分一阶温度补偿的带隙基准电压信号,并作为所述二阶曲率补偿电路的输入端,M15的源极与衬底相连并连接M17的漏极、M18的漏极以及M16的源极,M15的漏极连接地电位;M17的栅极连接正温电流源的输出节点,M17的源极连接电源电压;M18的栅极连接负温电流源的输出节点并与M19的栅极相连,M18的源极连接电源电压;M16的源极与衬底相连,M16的栅极和漏极相连并连接M20的漏极,作为所述二阶曲率补偿电路的输出端;M19的漏极连接M21的栅极和漏极以及M20的栅极,M19的源极连接电源电压;M20和M21的源极均连接地电位。The present invention solves the technical problem, and adopts the technical solution that is used for the second-order curvature temperature compensation circuit of the bandgap reference, including PMOS tubes: M15, M16, M17, M18, M19, and NMOS tubes: M20, M21; , the gate of M15 is connected to the bandgap reference voltage signal through part of the first-order temperature compensation, and is used as the input terminal of the second-order curvature compensation circuit, the source of M15 is connected to the substrate and connected to the drain of M17 and the drain of M18 pole and the source of M16, the drain of M15 is connected to the ground potential; the gate of M17 is connected to the output node of the positive temperature current source, and the source of M17 is connected to the power supply voltage; the gate of M18 is connected to the output node of the negative temperature current source and connected with The gate of M19 is connected, the source of M18 is connected to the power supply voltage; the source of M16 is connected to the substrate, the gate of M16 is connected to the drain and connected to the drain of M20, as the output end of the second-order curvature compensation circuit; The drain of M19 is connected to the gate and drain of M21 and the gate of M20, the source of M19 is connected to the power supply voltage; the sources of M20 and M21 are both connected to the ground potential.
具体的,所述正温电流源包括,PMOS管:M00、M4、M5,NMOS管:M0、M1、M2、M3,PNP型三极管:Q1、Q2、Q3;其中,M00的栅极为正温电流源的输出节点,M00的栅极的与漏极相连,并且连接M0的漏极、M5的栅极和M4的栅极,M00的源极连接电源电压;M0的栅极连接M5的漏极和M3的漏极,M0的源极连接Q3的发射极;M5的源极连接电源电压;M4的漏极连接M2的漏极和栅极、M3的栅极以及M1的栅极,M4的源极连接电源电压;M3的源极连接Q2的发射极;Q3的集电极与基极均连接地电位;M2的源极连接M1的漏极;M1的源极连接Q1的发射极;Q2、Q1的集电极与基极均连接地电位。Specifically, the positive temperature current source includes PMOS transistors: M00, M4, M5, NMOS transistors: M0, M1, M2, M3, PNP transistors: Q1, Q2, Q3; wherein, the gate of M00 is a positive temperature current The output node of the source, the gate of M00 is connected to the drain, and connected to the drain of M0, the gate of M5 and the gate of M4, the source of M00 is connected to the power supply voltage; the gate of M0 is connected to the drain of M5 and The drain of M3, the source of M0 is connected to the emitter of Q3; the source of M5 is connected to the power supply voltage; the drain of M4 is connected to the drain and gate of M2, the gate of M3 and the gate of M1, and the source of M4 Connect the power supply voltage; the source of M3 is connected to the emitter of Q2; the collector and base of Q3 are connected to the ground potential; the source of M2 is connected to the drain of M1; the source of M1 is connected to the emitter of Q1; Both collector and base are connected to ground potential.
具体的,所述负温电流源包括,PMOS管:M10,M11、M14,NMOS管:M6、M7、M8、M9、M12、M13;其中M14的栅极为负温电流源的输出节点,M14的栅极与漏极相连,并且连接M13的漏极、M10的栅极和M11的栅极,M14的源极连接电源电压;M13的栅极连接M10的漏极和M8的漏极,M13的源极连接M12的漏极和栅极;M10的源极连接电源电压;M11的漏极连接M9的漏极和栅极、M8的栅极以及M7的栅极,M11的源极连接电源电压;M8的源极连接M6的漏极和栅极;M9的源极连接M7的漏极;M6、M7、M12的源极均连接地电位。Specifically, the negative temperature current source includes, PMOS transistors: M10, M11, M14, NMOS transistors: M6, M7, M8, M9, M12, M13; wherein the gate of M14 is the output node of the negative temperature current source, and the gate of M14 The gate is connected to the drain, and is connected to the drain of M13, the gate of M10 and the gate of M11, the source of M14 is connected to the power supply voltage; the gate of M13 is connected to the drain of M10 and the drain of M8, and the source of M13 The pole is connected to the drain and gate of M12; the source of M10 is connected to the power supply voltage; the drain of M11 is connected to the drain and gate of M9, the gate of M8 and the gate of M7, and the source of M11 is connected to the power supply voltage; M8 The source of M6 is connected to the drain and gate of M6; the source of M9 is connected to the drain of M7; the sources of M6, M7 and M12 are all connected to the ground potential.
本发明的有益效果是,电路适用范围和灵活性得到了显著改善。本发明的二阶曲率温度补偿电路,与现有的二阶曲率温度补偿电路相比,在电路结构方面,不需要使用电阻,在工艺方面,其可以适用于标准数字CMOS工艺。The beneficial effect of the invention is that the application range and flexibility of the circuit are significantly improved. Compared with the existing second-order curvature temperature compensation circuit, the second-order curvature temperature compensation circuit of the present invention does not need to use resistors in terms of circuit structure, and can be applied to standard digital CMOS technology in terms of technology.
附图说明Description of drawings
图1现有技术带隙基准指数型二阶曲率温度补偿电路结构示意图;Fig. 1 is a schematic structural diagram of a bandgap reference exponential type second-order curvature temperature compensation circuit in the prior art;
图2本发明实施例的带隙基准二阶曲率温度补偿电路结构示意图;Fig. 2 is a schematic structural diagram of a bandgap reference second-order curvature temperature compensation circuit according to an embodiment of the present invention;
图3本发明实施例的正温电流源电路结构图;The structure diagram of the positive temperature current source circuit of the embodiment of the present invention of Fig. 3;
图4本发明实施例的负温电流源电路结构图。FIG. 4 is a structural diagram of a negative temperature current source circuit according to an embodiment of the present invention.
其中,M00、M4、M5、M10、M11、M14、M15、M16、M17、M18、M19为PMOS管;M0、M1、M2、M3、M6、M7、M8、M9、M12、M13、M20、M21为NMOS管;Q1、Q2、Q3为PNP型三极管;T1、T2为NPN型三极管;R为电阻。Among them, M00, M4, M5, M10, M11, M14, M15, M16, M17, M18, M19 are PMOS tubes; M0, M1, M2, M3, M6, M7, M8, M9, M12, M13, M20, M21 is NMOS tube; Q1, Q2, Q3 are PNP transistors; T1, T2 are NPN transistors; R is resistance.
具体实施方式Detailed ways
下面结合附图及实施例对本发明作进一步详细描述。The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
本发明用于带隙基准的二阶曲率温度补偿电路,如图2所示,包括,PMOS管:M15、M16、M17、M18、M19,NMOS管:M20、M21。其中,M15的栅极连接经过部分一阶温度补偿的带隙基准电压信号VREF1作为本发明二阶曲率温度补偿电路的输入端,源极与衬底相连再连接M17的漏极、M18的漏极以及M16的源极与衬底,M15的漏极连接地电位VSS。M17的栅极连接正温电流源的输出节点VP,源极连接电源电压VDD。M18的栅极连接负温电流源的输出节点VC并与M19的栅极相连,M18的源极连接电源电压VDD。M16的源极与衬底相连,M16的栅极和漏极相连并连接M20的漏极,M16的栅极还是本发明二阶曲率温度补偿电路的输出端VREF2。M19的漏极连接M21的栅极和漏极以及M20的栅极,M19的源极连接电源电压VDD。M20的源极和M21的源极均连接地电位VSS。The second-order curvature temperature compensation circuit for the bandgap reference of the present invention, as shown in FIG. 2 , includes PMOS transistors: M15, M16, M17, M18, M19, and NMOS transistors: M20 and M21. Among them, the gate of M15 is connected to the bandgap reference voltage signal VREF1 through part of the first-order temperature compensation as the input terminal of the second-order curvature temperature compensation circuit of the present invention, and the source is connected to the substrate and then connected to the drain of M17 and the drain of M18 And the source of M16 is connected to the substrate, and the drain of M15 is connected to the ground potential VSS. The gate of M17 is connected to the output node VP of the positive temperature current source, and the source is connected to the power supply voltage VDD. The gate of M18 is connected to the output node VC of the negative temperature current source and connected to the gate of M19, and the source of M18 is connected to the power supply voltage VDD. The source of M16 is connected to the substrate, the gate of M16 is connected to the drain and is connected to the drain of M20, and the gate of M16 is also the output terminal VREF2 of the second-order curvature temperature compensation circuit of the present invention. The drain of M19 is connected to the gate and drain of M21 and the gate of M20, and the source of M19 is connected to the power supply voltage VDD. Both the source of M20 and the source of M21 are connected to the ground potential VSS.
上述正温电流源的一种电路实现方案见图3所示,包括,PMOS管:M00,M4、M5,NMOS管:M0、M1、M2、M3,PNP型三极管:Q1、Q2、Q3。M00的栅极为正温电流源的输出节点VP,该节点VP与漏极相连,并且连接M0的漏极以及M5的栅极和M4的栅极,M00的源极连接电源电压VDD。M0的栅极连接M5的漏极和M3的漏极,M0的源极连接Q3的发射极。M5的源极连接电源电压VDD。M4的漏极连接M2的漏极和栅极、M3的栅极以及M1的栅极,M4的源极连接电源电压VDD。M3的源极连接Q2的发射极。Q3的集电极与基极均连接地电位VSS。M2的源极连接M1的漏极。M1的源极连接Q1的发射极。Q2与Q1的集电极与基极均连接地电位VSS。A circuit implementation scheme of the above-mentioned positive temperature current source is shown in Figure 3, including PMOS transistors: M00, M4, M5, NMOS transistors: M0, M1, M2, M3, and PNP transistors: Q1, Q2, Q3. The gate of M00 is the output node VP of the positive temperature current source, and the node VP is connected to the drain, and is connected to the drain of M0, the gates of M5 and the gates of M4, and the source of M00 is connected to the power supply voltage VDD. The gate of M0 is connected to the drain of M5 and the drain of M3, and the source of M0 is connected to the emitter of Q3. The source of M5 is connected to the power supply voltage VDD. The drain of M4 is connected to the drain and gate of M2, the gate of M3 and the gate of M1, and the source of M4 is connected to the power supply voltage VDD. The source of M3 is connected to the emitter of Q2. Both the collector and the base of Q3 are connected to the ground potential VSS. The source of M2 is connected to the drain of M1. The source of M1 is connected to the emitter of Q1. The collectors and bases of Q2 and Q1 are both connected to the ground potential VSS.
上述负温电流源的一种电路实现方案见图4所示,包括,PMOS管:M10,M11、M14,NMOS管:M6、M7、M8、M9、M12、M13。M14的栅极为负温电流源的输出节点VC,该输出节点VC与漏极相连,并且连接M13的漏极以及M10的栅极和M11的栅极,M14的源极连接电源电压VDD。M13的栅极连接M10的漏极和M8的漏极,M13的源极连接M12的漏极和栅极。M10的源极连接电源电压VDD。M11的漏极连接M9的漏极和栅极、M8的栅极以及M7的栅极,M11的源极连接电源电压VDD。M8的源极连接M6的漏极和栅极。M9的源极连接M7的漏极。M6的源极、M7的源极、M12的源极均连接地电位VSS。A circuit implementation scheme of the above-mentioned negative temperature current source is shown in FIG. 4 , including PMOS transistors: M10, M11, M14, and NMOS transistors: M6, M7, M8, M9, M12, and M13. The gate of M14 is the output node VC of the negative temperature current source, the output node VC is connected to the drain, and is connected to the drain of M13, the gates of M10 and M11, and the source of M14 is connected to the power supply voltage VDD. The gate of M13 is connected to the drain of M10 and the drain of M8, and the source of M13 is connected to the drain and gate of M12. The source of M10 is connected to the power supply voltage VDD. The drain of M11 is connected to the drain and gate of M9, the gate of M8 and the gate of M7, and the source of M11 is connected to the power supply voltage VDD. The source of M8 is connected to the drain and gate of M6. The source of M9 is connected to the drain of M7. The source of M6, the source of M7, and the source of M12 are all connected to the ground potential VSS.
图2中,IP是正温电流源产生的电流Ibias的F倍,F是与温度无关的量。IC1和IC2是负温电流源产生的电流。这里IC1和IC2由同一负温电流源产生,有:IC1=IC2=IC。工作在亚阈值区的PMOS管M15和M16实现电压叠加,在已经部分一阶温度补偿的带隙基准电压VREF1的基础上再叠加一个同时具有一阶和二阶温度补偿效果的电压量,从而产生最终的二阶曲率温度补偿带隙基准输出电压VREF2。In Figure 2, I P is F times of the current I bias generated by the positive temperature current source, and F is a quantity independent of temperature. I C1 and I C2 are the currents generated by the negative temperature current source. Here I C1 and I C2 are generated by the same negative temperature current source, as follows: I C1 =I C2 =I C . The PMOS transistors M15 and M16 working in the sub-threshold region implement voltage superposition, and on the basis of the bandgap reference voltage VREF1 that has been partially compensated for the first-order temperature, a voltage quantity with both first-order and second-order temperature compensation effects is superimposed, thereby generating The final second-order curvature temperature compensated bandgap reference output voltage VREF2.
如图3所示,该正温电流源产生的正温电流Ibias可以表示为As shown in Figure 3, the positive temperature current I bias generated by the positive temperature current source can be expressed as
其中in
VT是热电压,表示MOS管的宽长比,COX是MOS管栅极氧化物单位面积电容量,m是PNP型三极管Q1和Q2的发射极面积之比,q是单位电荷量。NMOS管中的电子迁移率可以表示为μN(T)=μ0NT-n,μ0N是与温度无关的常数,n是与掺杂浓度有关的常数,一般工艺中其值为1.5左右。V T is the thermal voltage, Indicates the width-to-length ratio of the MOS tube, C OX is the capacitance per unit area of the gate oxide of the MOS tube, m is the ratio of the emitter area of the PNP transistor Q1 and Q2, and q is the unit charge. The electron mobility in the NMOS tube can be expressed as μ N (T) = μ 0N T -n , μ 0N is a constant independent of temperature, n is a constant related to doping concentration, and its value is about 1.5 in general processes.
如图4所示,电流IC可以表示为其中As shown in Figure 4, the current I C can be expressed as in
VTHN是NMOS管的阈值电压。NMOS管的阈值电压可以表示为V THN is the threshold voltage of the NMOS tube. The threshold voltage of the NMOS transistor can be expressed as
VTHN(T)=VTHN(T00)-αVTN(T-T00)=β-αVTNTV THN (T)=V THN (T 00 )-α VTN (TT 00 )=β-α VTN T
其中T00为参考温度,αVTN是NMOS管的阈值电压温度系数,αVTN>0,β=VTHN(T00)+αVTNT00。因此,电流IC可以进一步表示为Where T 00 is the reference temperature, α VTN is the threshold voltage temperature coefficient of the NMOS transistor, α VTN >0, β=V THN (T 00 )+α VTN T 00 . Therefore, the current I C can be further expressed as
其中,αVTN<<β。Wherein, α VTN << β.
工作在亚阈值区的PMOS管漏极电流ID可以表示为则源极与栅极之间电压其中,ID0=μP(T)COX(η-1)VT 2,VTHP是PMOS管的阈值电压,μP(T)是PMOS管中的空穴迁移率,η是亚阈值区斜率。图2中PMOS管M15和M16均工作在亚阈值区且具有相同的宽长比。流过M15的电流ID15=IP=FIbias,流过M16的电流ID16=IC=IC1=IC2。其中F是与温度无关的量,可以改变MOS管的宽长比来调节其数值。那么就有The drain current ID of the PMOS transistor working in the sub-threshold region can be expressed as The voltage between source and gate Wherein, I D0 =μ P (T)C OX (η-1)V T 2 , V THP is the threshold voltage of the PMOS tube, μ P (T) is the hole mobility in the PMOS tube, and η is the subthreshold region slope. In Fig. 2, PMOS transistors M15 and M16 both work in the sub-threshold region and have the same width-to-length ratio. Current I D15 =I P =FI bias flowing through M15, and I D16 =I C =I C1 =I C2 flowing through M16. Among them, F is a quantity independent of temperature, and its value can be adjusted by changing the width-to-length ratio of the MOS tube. then there is
其中 当有电流Ibias流过PNP型三极管的发射极时,其发射极与基极之间的电压in When a current I bias flows through the emitter of the PNP transistor, the voltage between the emitter and the base
其中E是一个与温度无关的常数,VG0是温度为0K时硅的带隙电压。PNP型三极管中基极电子迁移率可以表示为μ(T)=μ0T-ε,其中μ0是与温度无关的常数,ε是与掺杂浓度有关的常数。Where E is a temperature-independent constant, and V G0 is the bandgap voltage of silicon at a temperature of 0K. The base electron mobility in a PNP transistor can be expressed as μ(T)=μ 0 T -ε , where μ 0 is a constant independent of temperature, and ε is a constant related to doping concentration.
VREF1是经过部分一阶温度补偿的带隙基准电压,VREF1=VEB(T)+A0VT,A0是与温度无关的量,可以改变MOS管的宽长比来调节A0的数值。则有VREF1 is a bandgap reference voltage with partial first-order temperature compensation, VREF1=V EB (T)+A 0 V T , A 0 is a temperature-independent quantity, and the value of A 0 can be adjusted by changing the width-to-length ratio of the MOS tube . then there is
其中A1=ln(Eδ1),A3=n-ε+2,A4=2η。设零温点时的温度为T0,可以把VREF2的表达式改写为Wherein A 1 =ln(Eδ 1 ), A 3 =n-ε+2, A 4 =2η. Assuming that the temperature at zero temperature point is T 0 , the expression of VREF2 can be rewritten as
在T=T0附近对上式进行二阶泰勒展开,有Carrying out the second-order Taylor expansion of the above formula around T=T 0 , we have
VREF2≌a+bT+cT2 (2)VREF2≌a+bT+cT 2 (2)
其中in
根据公式(2),想要同时实现一阶和二阶温度补偿,必须有b=c=0,即According to the formula (2), if you want to realize the first-order and second-order temperature compensation at the same time, you must have b=c=0, that is
在公式(3)中,只有T0是可变的量,那么就可以通过调节零温点T0,从而使得上式成立。具体地讲,将公式(1)对温度求偏导数并令该偏导数为零,即得到In formula (3), only T 0 is a variable quantity, then the above formula can be established by adjusting the zero temperature point T 0 . Specifically, calculate the partial derivative of formula (1) with respect to temperature and set the partial derivative to zero, namely get
解出T0=f(F,A0),表示T0是关于F和A0的函数,也就是说可以改变MOS管的宽长比来调节F和A0的大小进而改变零温点T0,使得公式(3)成立。这样便可以实现对三极管BE结电压的二阶温度补偿。Solve T 0 =f(F,A 0 ), which means that T 0 is a function of F and A 0 , that is to say, the width-to-length ratio of the MOS tube can be changed to adjust the size of F and A 0 and then change the zero temperature point T 0 , so that formula (3) holds. In this way, the second-order temperature compensation of the BE junction voltage of the triode can be realized.
综上可以看出,本发明提出的带隙基准二阶曲率温度补偿电路,不需要使用电阻,可以在标准CMOS工艺中实现,这样使得其适用范围和灵活性得到显著改善。In summary, it can be seen that the bandgap reference second-order curvature temperature compensation circuit proposed by the present invention does not need to use resistors, and can be realized in standard CMOS technology, so that its application range and flexibility are significantly improved.
本领域的普通技术人员将会意识到,这里描述的实施例是为了帮助读者理解本发明的原理,本发明的保护范围并不局限于这样的特别陈述和实施例,比如上述正温电流源和负温电流源,就可以采用各种结构不同的电路来实现,这些变形和组合仍然在本发明的保护范围内。Those of ordinary skill in the art will appreciate that the embodiment described here is to help the reader understand the principle of the present invention, and the protection scope of the present invention is not limited to such special statements and embodiments, such as the above-mentioned positive temperature current source and The negative temperature current source can be realized by using various circuits with different structures, and these deformations and combinations are still within the protection scope of the present invention.
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