CN103309392B - A kind of second-order temperature compensate without amplifier whole CMOS reference voltage source - Google Patents

Abstract

The present invention relates to field of analog integrated circuit, it discloses a kind of novel second-order temperature compensate without amplifier whole CMOS reference voltage source, the problem that chip occupying area is large, power consumption is high that the structure solving the reference voltage source in conventional art is brought, this reference voltage source comprises voltage reference biasing circuit, CTAT voltage generation circuit, PTAT voltage generation circuit and reference voltage output-stage circuit; The output terminal of described voltage reference biasing circuit is connected with described CTAT voltage generation circuit and reference voltage output-stage circuit; Described CTAT voltage generation circuit and being connected with its described reference voltage output-stage circuit meeting image current relation; The output terminal of described PTAT voltage generation circuit is connected with described reference voltage output-stage circuit; The output terminal of described reference voltage output stage, as the output terminal of whole CMOS reference voltage source, exports constant reference voltage; The present invention is applicable in the mimic channel of demand reference voltage source.

Description

A second-order temperature-compensated all-CMOS reference voltage source without op-amp

technical field

The invention relates to the field of analog integrated circuits, in particular to a second-order temperature-compensated full CMOS reference voltage source without an operational amplifier in the field.

Background technique

With the development of integrated circuit technology, the design and manufacture of integrated circuits tend to be high-density, high-complexity, and high-precision. In almost all analog circuits, the reference voltage source or reference current source is an indispensable basic circuit module. Having a high-precision reference voltage output is particularly important to improve the performance of the circuit, so designing a circuit with a high-precision bandgap reference voltage It has become a demand for analog and mixed circuit design. In the actual reference circuit, in addition to requiring as low voltage as possible, low power consumption, low temperature coefficient, and high power supply rejection ratio, it also requires the smallest possible layout chip area.

The structure of the bandgap reference voltage source in the traditional technology has the following disadvantages: the use of BJT technology takes up more chip area; the use of operational amplifier structure not only increases the chip area, but also increases the circuit power consumption; low power consumption The trend requires the circuit current to be reduced again and again, making it inevitable to use a resistor that occupies a considerable area, which will inevitably increase the chip area.

The structure of the bandgap reference voltage source in the traditional technology is shown in FIG. 1 , which includes PMOS transistors MP1 and MP2, transistors Q1 and Q2, first to third resistors R1, R2A, R2B, and an operational amplifier OP101. The sources of the PMOS transistors MP1 and MP2 are connected to the DC voltage source VDD, the gates are connected to the output terminal OUT of the operational amplifier OP101, the drain of the first PMOS transistor MP1 is connected to one end of the resistor R2A, and the other end of the resistor R2A It is connected to the inverting input terminal INN of the operational amplifier OP101, and connected to the emitter of the transistor Q2, the drain of the second PMOS transistor MP2 is connected to one end of the resistor R2B, and the other end of the resistor R2B is connected to the non-inverting input terminal of the operational amplifier OP101 The INP is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the emitter of the transistor Q1, and the gates and collectors of the transistors Q1 and Q2 are grounded.

In the above-mentioned bandgap reference voltage source circuit, the operational amplifier OP101 puts the circuit in a negative feedback state, clamps the voltages of point A and point B, and makes the voltages of the two points equal, and the transistors Q1 and Q2 are both parasitic vertical bipolar transistors (BJT). The reference voltage formula of the bandgap reference voltage circuit is:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BE</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; N</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; B</span>}}<span\; class="notranslate">\; )</span>$

In the above formula, V _BE1 is the base-emitter voltage of Q1, V _T is the thermoelectric potential V _T =0.026V, and N is the number of transistors Q1 connected in parallel. It can be seen that the reference voltage source uses the forward conduction voltage V _BE of the bipolar transistor BE junction with a negative temperature coefficient to compensate with the thermal voltage V _T with a positive temperature coefficient to obtain a reference voltage that is insensitive to temperature changes.

Contents of the invention

The technical problem to be solved by the present invention is: to propose a new type of second-order temperature compensation full CMOS reference voltage source without op-amp, to solve the problem of large occupied chip area and high power consumption caused by the structure of the reference voltage source in the traditional technology. question.

The solution adopted by the present invention to solve the above-mentioned technical problems is: a second-order temperature compensation full CMOS reference voltage source without operational amplifier, including: voltage reference bias circuit, CTAT (complementary with absolute temperature) voltage generation circuit, PTAT (complementary with absolute temperature) Temperature is directly proportional) voltage generation circuit and reference voltage output stage circuit; The output end of described voltage reference bias circuit is connected with described CTAT voltage generation circuit and reference voltage output stage circuit; Described CTAT voltage generation circuit and it satisfy mirror current The described reference voltage output stage circuit of relation is connected; The output end of described PTAT voltage generating circuit is connected with described reference voltage output stage circuit; The output end of described reference voltage output stage circuit is used as the output end of whole CMOS reference voltage source, output a constant reference voltage.

Further, the voltage reference bias circuit includes a DC current source and a first PMOS transistor; the source terminal of the first PMOS transistor is connected to a power supply, its drain terminal is connected to its gate terminal, and its drain terminal is connected to the DC current source One end of the current source is connected, and the other end of the current source is connected to ground. In this way, the current flowing through the first PMOS transistor will be mirrored to the CTAT voltage generation circuit and the reference voltage output stage circuit to provide a suitable bias current.

Further, the CTAT voltage generating circuit includes a second PMOS transistor, a third PMOS transistor, a sixth PMOS transistor forming a current mirror, a fourth PMOS transistor, a fifth PMOS transistor forming a coupled pair, and a sixth PMOS transistor operating in a saturation region. One NMOS transistor, the second NMOS transistor working in the subthreshold region, and the third NMOS transistor; the source terminals of the second PMOS transistor, the third PMOS transistor, and the sixth PMOS transistor forming the current mirror are all connected to the power supply, and the gate Both terminals are connected to the gate terminal of the first PMOS transistor to provide a suitable bias current; the drain terminal of the second PMOS transistor is connected to the drain terminal and gate terminal of the first NMOS transistor operating in the saturation region; The source terminal of the first NMOS transistor working in the saturation region is grounded; the drain terminal of the sixth PMOS transistor is connected to the drain terminal and the gate terminal of the second NMOS transistor working in the subthreshold region; The source terminal of the second NMOS transistor in the threshold region is grounded; the drain terminal of the third PMOS transistor is connected to the source terminal of the fourth PMOS transistor and the source terminal of the fifth PMOS transistor; the source terminal of the fourth PMOS transistor The gate terminal is connected to the drain terminal of the first NMOS transistor; the gate terminal of the fifth PMOS transistor is connected to the drain terminal of the second NMOS transistor; the drain terminal of the fourth PMOS transistor is grounded; the fifth PMOS transistor The drain terminal of the third NMOS transistor is connected to the gate terminal and the drain terminal of the third NMOS transistor; the source terminal of the third NMOS transistor is grounded.

Further, the PTAT voltage generation circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a resistor; the source terminals of the seventh PMOS transistor and the eighth PMOS transistor are connected to a power supply The gate terminal of the seventh PMOS transistor is connected to the gate terminal and the drain terminal of the eighth PMOS transistor; the drain terminal of the eighth PMOS transistor is connected to the drain terminal of the sixth NMOS transistor; the sixth The gate terminal of the NMOS transistor is connected to the gate terminal and the drain terminal of the fifth NMOS transistor; the drain terminal of the fifth NMOS transistor is connected to the drain terminal of the seventh PMOS transistor; the source terminal of the fifth NMOS transistor grounding; the source terminal of the sixth NMOS transistor is used as an output terminal connected to the reference voltage output stage circuit, and is connected to one terminal of the resistor, and the other terminal of the resistor is grounded.

The reference voltage output stage circuit includes a ninth PMOS transistor, a tenth PMOS transistor and an eleventh PMOS transistor forming a coupled pair, and a fourth NMOS transistor; the source terminal of the ninth PMOS transistor is connected to a power supply, and the gate terminal is connected to a power supply. The gate terminal of the first PMOS transistor is connected, and the drain terminal is connected with the source terminals of the tenth PMOS transistor and the eleventh PMOS transistor; the gate terminal of the tenth PMOS transistor is connected with the source terminal of the sixth NMOS transistor, and its drain The terminal is grounded; the gate terminal of the eleventh PMOS transistor is connected to its drain terminal as the output terminal of the reference voltage output stage circuit; the drain terminal of the fourth NMOS transistor is connected to the drain terminal of the eleventh PMOS transistor, The gate terminal is connected to the gate terminal of the third NMOS transistor, and the source terminal thereof is grounded.

The beneficial effects of the present invention are: by using two MOS devices with different threshold voltages to realize the reference voltage output with second-order compensation, the temperature coefficient of the output voltage is significantly reduced; by optimizing the circuit structure, the traditional voltage reference source is removed The operational amplifier structure greatly reduces power consumption; by using the full CMOS process to replace the traditional BJT, CMOS hybrid process and optimizing the circuit structure, it avoids the large use of voltage dividing resistors in the traditional structure, which greatly reduces The area of the layout chip is reduced; thus, the power consumption of the circuit and the layout area are reduced at the same time, and the production cost of the reference source is reduced.

Description of drawings

FIG. 1 is a schematic structural diagram of a bandgap reference voltage source in the conventional technology;

Fig. 2 is a schematic structural diagram of a full CMOS reference voltage source without an operational amplifier in the present invention;

Fig. 3 is a simulation diagram of the first-order derivative of the difference ΔV _gs between the gate-source voltage of the MN2 tube and the MN1 tube in the 202 module with respect to temperature;

Figure 4 is a schematic diagram of the simulation of the second derivative of the difference ΔV _gs between the gate-source voltage of the MN2 tube and the MN1 tube with respect to temperature in the 202 module;

Fig. 5 is a schematic diagram of the simulation results of the output voltage temperature coefficient according to the embodiment of the present invention;

In the figure, 201 is a voltage reference bias circuit, 202 is a CTAT voltage generating circuit, 203 is a PTAT voltage generating circuit, 204 is a reference voltage output stage circuit, MP1 is a first PMOS transistor, MP2 is a second PMOS transistor, and MP3 is a second PMOS transistor. Three PMOS transistors, MP4 is the fourth PMOS transistor, MP5 is the fifth PMOS transistor, MP6 is the sixth PMOS transistor, MP7 is the seventh PMOS transistor, MP8 is the eighth PMOS transistor, MP9 is the ninth PMOS transistor, MP10 is the tenth PMOS transistor, MP11 is the eleventh PMOS transistor, MN1 is the first NMOS transistor, MN2 is the second NMOS transistor, MN3 is the third NMOS transistor, MN4 is the fourth NMOS transistor, MN5 is the fifth NMOS transistor, MN6 is the sixth NMOS transistor, R is a resistor, and IDC is a DC current source.

Detailed ways

Below in conjunction with accompanying drawing and embodiment the scheme of the present invention will be further described:

Referring to FIG. 2 , the full CMOS reference voltage source without an op amp in this example includes four parts: a voltage reference bias circuit 201, a CTAT voltage generation circuit 202, a PTAT voltage generation circuit 203, and a reference voltage output stage circuit 204;

For the voltage reference bias circuit 201, it includes a DC current source IDC and a first PMOS transistor MP1; the source terminal of the first PMOS transistor MP1 is connected to the power supply VDD, its drain terminal is connected to its gate terminal, and the drain terminal of MP1 is connected to the DC current source One end of IDC is connected, and the other end of current source IDC is connected to ground. In this way, the current flowing through MP1 will be mirrored to the CTAT voltage generation circuit 202 and the reference voltage output stage circuit 204 to provide a suitable bias current;

For the CTAT voltage generating circuit 202, it includes the second PMOS transistor MP2, the third PMOS transistor MP3, the sixth PMOS transistor MP6 forming a current mirror, and the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 forming a coupled pair, and the working The first NMOS transistor MN1 in the saturation region, the second NMOS transistor MN2 operating in the subthreshold region, and the third NMOS transistor MN3; the second PMOS transistor MP2, the third PMOS transistor MP3, and the sixth PMOS transistor that form a current mirror The source terminals of the transistor MP6 are all connected to the power supply VDD, and the gate terminals are connected to the gate terminal of the first PMOS transistor MP1 to provide a suitable bias current; The drain terminal of the first NMOS transistor MN1 is connected to the gate terminal; the source terminal of the first NMOS transistor MN1 working in the saturation region is grounded; the drain terminal of the sixth PMOS transistor MP6 is connected to the gate terminal working in the subthreshold region The drain terminal of the second NMOS transistor MN2 is connected to the gate terminal; the source terminal of the second NMOS transistor MN2 operating in the subthreshold region is grounded; the drain terminal of the third PMOS transistor MP3 is connected to the fourth PMOS transistor MP4 The source terminal is connected to the source terminal of the fifth PMOS transistor MP5; the gate terminal of the fourth PMOS transistor MP4 is connected to the drain terminal of the first NMOS transistor MN1; the gate terminal of the fifth PMOS transistor MP5 is connected to the The drain terminal of the second NMOS transistor MN2; the drain terminal of the fourth PMOS transistor MP4 is grounded; the drain terminal of the fifth PMOS transistor MP5 is connected to the gate terminal and the drain terminal of the third NMOS transistor MN3; The source terminals of the three NMOS transistors MN3 are grounded;

For the PTAT voltage generating circuit 203, it includes the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 and the resistor R; the seventh PMOS transistor MP7, the eighth PMOS transistor MP8 The source terminals are connected to the power supply VDD; the gate terminal of the seventh PMOS transistor MP7 is connected to the gate terminal and the drain terminal of the eighth PMOS transistor MP8; the drain terminal of the eighth PMOS transistor MP8 is connected to the sixth PMOS transistor MP8. The drain of the NMOS transistor MN6 is connected; the gate of the sixth NMOS transistor MN6 is connected to the gate and drain of the fifth NMOS transistor MN5; the drain of the fifth NMOS transistor MN5 is connected to the seventh PMOS The drain end of the transistor MP7 is connected; the source end of the fifth NMOS transistor MN5 is grounded; the source end of the sixth NMOS transistor MN6 is used as an output end connected to the reference voltage output stage circuit, and is connected to one end of the resistor R, The other end of the resistor R is grounded;

For the reference voltage output stage circuit 204, it includes the ninth PMOS transistor MP9, the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 forming a coupling pair, and the fourth NMOS transistor MN4; the source terminal of the ninth PMOS transistor MP9 It is connected to the power supply VDD, the gate terminal is connected to the gate terminal of the first PMOS transistor MP1, and the drain terminal is connected to the source terminals of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11; the gate terminal of the tenth PMOS transistor MP10 terminal is connected with the source terminal of the sixth NMOS transistor MN6, and its drain terminal is grounded; the gate terminal of the eleventh PMOS transistor MP11 is connected with its drain terminal as the output terminal of the reference voltage output stage circuit; the fourth NMOS transistor MN4 The drain terminal of the transistor is connected to the drain terminal of the eleventh PMOS transistor MP11, the gate terminal is connected to the gate terminal of the third NMOS transistor MN3, and the source terminal thereof is grounded.

As can be seen from FIG. 2, the relationship between the four modules of the voltage reference bias circuit 201, the CTAT voltage generation circuit 202, the PTAT voltage generation circuit 203, and the reference voltage output stage circuit 204 is: the voltage reference bias circuit 201 The output terminal—the gate terminal of MP1 is connected to the gate terminals of MP2, MP3, and MP6 in the CTAT voltage generating circuit 202; the output terminal of 201—the gate terminal of MP1 is connected to the gate terminal of MP9 in the reference voltage output stage circuit 204. The gate terminal of MN3 in the CTAT voltage generating circuit 202 is connected to the gate terminal of MN4 in the reference voltage output stage circuit 204 to satisfy the mirror current relationship. The output terminal of the PTAT voltage generation circuit 203 , the source terminal Vptat of MN6 , is connected to the gate terminal of MP10 in the reference voltage output stage circuit 204 module. The gate terminal VREF of MP11 in the reference voltage output stage circuit 204 serves as the output terminal of the entire voltage reference source, and outputs a constant reference voltage.

The voltage at point Y in the reference voltage output stage circuit 204 is equal to:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; Y</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; GS</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 11</span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; GS</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Among them, V _Y is the voltage at point Y, V _{GS_MP11} is the gate-source voltage of MP11 tube, V _{GS_MP10} is the gate-source voltage of MP10 tube, V _ref is the gate terminal voltage of MP11, which is also the reference output voltage, and V _PTAT is the gate terminal voltage of MP10 tube .

The above formula (1) can be changed to:

V _ref =V _{GS_MP10} -V _{GS_MP11} +V _PTAT (2)

The CTAT voltage generating circuit 202 module includes PMOS current mirror transistors MP2, MP3, MP6, PMOS coupling transistors MP4, MP5, and a low-threshold NMOS transistor MN1 (its width-to-length ratio is W ₁ : L ₁ ) working in the saturation region. A high-threshold NMOS transistor MN2 (with a width-to-length ratio of W ₂ : L ₂ ) in the sub-threshold region, and an NMOS current mirror transistor MN3. The gate-source voltage of the low-threshold NMOS transistor MN1 operating in the saturation region is equal to:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; sat</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Wherein, V _{GS_sat_1} is the gate-source voltage of MN1 working in the saturation region, V _{th_1} is the threshold voltage of MN1, V _{th_1} (T)=V _{th_1} (T ₀ )+K _th1 (TT ₀ ). I _D1 is the current of MN1, I _D1 =I ₁ -K ₁ T, μ _n1 is the mobility of MN1, C _ox1 is the capacitance of the unit gate oxide layer of MN1, and W ₁ /L ₁ is the width-to-length ratio of MN1.

The gate-source voltage of the high-threshold NMOS transistor MN2 working in the sub-threshold region is equal to:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; sub</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Wherein, V _{GS_sub_2} is the gate-source voltage of MN2 working in the subthreshold region, V _{th_2} is the threshold voltage of MN2, V _{th_2} (T)=V _{th_2} (T ₀ )+K _th2 (TT ₀ ). _ID2 is the current of MN2, m is the slope parameter of the subthreshold gate-source voltage, _ID2 =I ₂ -K ₂ T. μ _n2 is the mobility of MN2, C _ox2 is the unit gate oxide layer capacitance of MN2, W ₂ /L ₂ is the width-to-length ratio of MN2.

Because V _x =V _{gs_MP5} +V _{gs_MN2} =V _{gs_MP4} +V _{gs_MN1} ; (5)

so $\begin{array}{c}\mathrm{\&Delta;}{V}_{\mathrm{gs}}=V_{\mathrm{gs}\_\mathrm{MP}4}-V_{\mathrm{gs}\_\mathrm{MP}5}=V_{\mathrm{gs}\_\mathrm{MN}2}-V_{\mathrm{gs}\_\mathrm{MN}1}=V_{\mathrm{the\; th}\_2}-V_{\mathrm{the\; th}\_1}+\\ m{V}_T\ln \left(\frac{I_{\mathrm{D.}2}}{V_T^2{\mathrm{\&mu;}}_{\mathrm{no}2}{C}_{\mathrm{ox}2}{W}_2/L_2}\right)-\sqrt{\frac{2I_{\mathrm{D.}1}}{{\mathrm{\&mu;}}_{\mathrm{no}1}{C}_{\mathrm{ox}1}{W}_1/L_1}}\end{array}---\left(6\right)$

The first derivative of ΔV _gs with respect to temperature:

$\frac{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}}{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; ln</span>}\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; T</span>}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; k</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}{<span\; class="notranslate">\; [</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; ]</span>}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

The second derivative of ΔV _gs with respect to temperature:

$\frac{{<span\; class="notranslate">\; \&PartialD;</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}}{{<span\; class="notranslate">\; \&PartialD;</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}}{\mathrm{<span\; class="notranslate">\; wxya</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; B</span>}}}{\mathrm{<span\; class="notranslate">\; q</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>\sqrt{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

In equation (8), by setting the parameters reasonably, the

$\frac{K_1^2}{2(I_1-K_{1}T)\sqrt{2{\mathrm{\&beta;}}_1(l_1-K_{1}T)}}=\frac{{\mathrm{mK}}_2{K}_B}{q(I_2-K_{2}T)}+\frac{{2\mathrm{mK}}_B}{q^T}+\frac{{\mathrm{mK}}_2{K}_B}{q{(I_2-K_{2}T)}^2},$ Making the second-order derivative of ΔV _gs have a zero point means that ΔV _gs realizes the second-order compensation with respect to temperature.

Accompanying drawing 3 is the simulation result of ΔV _gs with respect to the first order derivative of temperature, and accompanying drawing 4 is the simulation result of ΔV _gs with respect to the second order derivative of temperature. It can be seen from Figures 3 and 4 that the second-order compensation of ΔV _gs with respect to temperature can be obtained by properly adjusting circuit parameters.

Since the MP3 tube in the 202 module and the MP9 tube in the 204 module satisfy a 1:G mirror image relationship; the MN3 tube in the 202 module and the MN4 tube in the 204 module also satisfy a 1:G mirror image relationship. Therefore, the MP4 pipe and the MP5 pipe in the 202 module meet the 1:G mirror image relationship with the MP10 pipe and the MP11 pipe in the 204 module respectively. And because MP4, MP5, MP10, MP11 tube width to length ratio is the same as W: L, that is:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; gs</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 10</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; *</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; gs</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 11</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; gs</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 11</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; *</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{{\mathrm{<span\; class="notranslate">\; gs</span>}}_{\mathrm{<span\; class="notranslate">\; MP</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}$

so: $V_{{\mathrm{gs}}_{\mathrm{MP}10}}-V_{{\mathrm{gs}}_{\mathrm{MP}11}}=\sqrt{G}(V_{{\mathrm{gs}}_{\mathrm{MP}4}}-V_{{\mathrm{gs}}_{\mathrm{MP}5}})---\left(9\right)$

The PTAT voltage generating circuit 203 module includes PMOS transistors MP7, MP8, NMOS transistors MN5, MN6, and a resistor R. This is a typical PTAT circuit, output voltage:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}<span\; class="notranslate">\; *</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\sqrt{\mathrm{<span\; class="notranslate">\; K</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

Among them, (W/L) _MN5 is the width-to-length ratio of the MN5 tube, and K is the ratio of the width-to-length ratio of the MN6 tube to the MN5 tube. V _PTAT is a voltage proportional to temperature.

Combining Equation (2), Equation (6), Equation (10):

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}<span\; class="notranslate">\; =</span>\sqrt{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; wxya</span>}\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; wxya</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; PTAT</span>}}<span\; class="notranslate">\; =</span>\\ \sqrt{\mathrm{<span\; class="notranslate">\; G</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; ]</span><span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; MN</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}}<span\; class="notranslate">\; *</span>\\ \frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\sqrt{\mathrm{<span\; class="notranslate">\; K</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

The first term in the above equation (11) is the negative temperature coefficient voltage with second-order compensation characteristics, the second term It is a positive temperature coefficient voltage, and a reference voltage insensitive to temperature can be obtained by adjusting the circuit parameter values reasonably. Figure 5 is a schematic diagram of the simulation results of the temperature coefficient of the output voltage. It can be seen from the figure that compared with the traditional structure, the temperature coefficient is lower and has the characteristics of second-order compensation.

It should be noted that the solutions claimed in the present invention include but are not limited to the above-mentioned embodiments. Equivalent modifications/replacements made by those skilled in the art based on the descriptions of the above-mentioned embodiments without departing from the spirit of the present invention are all included in this within the scope of protection of the invention.

Claims (3)

1. a second-order temperature compensate without amplifier whole CMOS reference voltage source, it is characterized in that, comprising: voltage reference biasing circuit (201), CTAT voltage generation circuit (202), PTAT voltage generation circuit (203) and reference voltage output-stage circuit (204); The output terminal of described voltage reference biasing circuit (201) is connected with described CTAT voltage generation circuit (202) and reference voltage output-stage circuit (204); Described CTAT voltage generation circuit (202) and being connected with its described reference voltage output-stage circuit (204) meeting image current relation; The output terminal of described PTAT voltage generation circuit (203) is connected with described reference voltage output-stage circuit (204); The output terminal of described reference voltage output-stage circuit (204) as the output terminal of whole CMOS reference voltage source, to export constant reference voltage;

Described voltage reference biasing circuit (201) comprises DC current source (IDC), the first PMOS transistor (MP1); The source of described first PMOS transistor (MP1) connects power supply (VDD), its drain terminal is connected with its grid end, and its drain terminal is connected with one end of described DC current source (IDC), the other end of described current source (IDC) is connected to ground;

Described CTAT voltage generation circuit (202) comprises the second PMOS transistor (MP2), the 3rd PMOS transistor (MP3), the 6th PMOS transistor (MP6) that form current mirror, and form coupling right the 4th PMOS transistor (MP4), the 5th PMOS transistor (MP5), and be operated in first nmos pass transistor (MN1) of saturation region, be operated in second nmos pass transistor (MN2) of subthreshold region, and the 3rd nmos pass transistor (MN3); The source of second PMOS transistor (MP2) of described formation current mirror, the 3rd PMOS transistor (MP3), the 6th PMOS transistor (MP6) all connects power supply (VDD), and grid end is all connected with the grid end of the first PMOS transistor (MP1); The drain terminal of described second PMOS transistor (MP2) is connected with grid end with the described drain terminal being operated in first nmos pass transistor (MN1) of saturation region; The described source ground connection being operated in first nmos pass transistor (MN1) of saturation region; The drain terminal of described 6th PMOS transistor (MP6) is connected with grid end with the described drain terminal being operated in second nmos pass transistor (MN2) of subthreshold region; The described source ground connection being operated in second nmos pass transistor (MN2) of subthreshold region; The drain terminal of described 3rd PMOS transistor (MP3) is connected with the source of described 5th PMOS transistor (MP5) with the source of described 4th PMOS transistor (MP4); The grid end of described 4th PMOS transistor (MP4) connects the drain terminal of described first nmos pass transistor (MN1); The grid end of described 5th PMOS transistor (MP5) connects the drain terminal of described second nmos pass transistor (MN2); The drain terminal ground connection of described 4th PMOS transistor (MP4); The drain terminal of described 5th PMOS transistor (MP5) is connected with drain terminal with the grid end of described 3rd nmos pass transistor (MN3); The source ground connection of described 3rd nmos pass transistor (MN3).

2. a kind of second-order temperature as claimed in claim 1 compensate without amplifier whole CMOS reference voltage source, it is characterized in that, described PTAT voltage generation circuit (203) comprises the 7th PMOS transistor (MP7), the 8th PMOS transistor (MP8), the 5th nmos pass transistor (MN5), the 6th nmos pass transistor (MN6) and resistance (R); The source of described 7th PMOS transistor (MP7), the 8th PMOS transistor (MP8) is all connected with power supply (VDD); The grid end of described 7th PMOS transistor (MP7) is connected with drain terminal with the grid end of described 8th PMOS transistor (MP8); The drain terminal of described 8th PMOS transistor (MP8) is connected with the drain terminal of described 6th nmos pass transistor (MN6); The grid end of described 6th nmos pass transistor (MN6) is connected with drain terminal with the grid end of described 5th nmos pass transistor (MN5); The drain terminal of described 5th nmos pass transistor (MN5) is connected with the drain terminal of described 7th PMOS transistor (MP7); The source ground connection of described 5th nmos pass transistor (MN5); The source of described 6th nmos pass transistor (MN6) as the output terminal connecting reference voltage output-stage circuit (204), and is connected with one end of described resistance (R), the other end ground connection of described resistance (R).

3. a kind of second-order temperature as claimed in claim 2 compensate without amplifier whole CMOS reference voltage source, it is characterized in that, described reference voltage output-stage circuit (204) comprises the 9th PMOS transistor (MP9), forms the tenth right PMOS transistor (MP10) of coupling and the 11 PMOS transistor (MP11), the 4th nmos pass transistor (MN4); The source of described 9th PMOS transistor (MP9) is connected with power supply (VDD), grid end is connected with the grid end of the first PMOS transistor (MP1), and drain terminal is connected with the source of the 11 PMOS transistor (MP11) with described tenth PMOS transistor (MP10); The grid end of described tenth PMOS transistor (MP10) is connected with the source of the 6th nmos pass transistor (MN6), its drain terminal ground connection; The grid end of described 11 PMOS transistor (MP11) is connected with its drain terminal as the output terminal of this reference voltage output-stage circuit (204); The drain terminal of described 4th nmos pass transistor (MN4) is connected with the drain terminal of described 11 PMOS transistor (MP11), and grid end is connected with the grid end of the 3rd nmos pass transistor (MN3), its source ground connection.