CN104375553A - Bandgap reference circuit and base current compensation circuit - Google Patents
Bandgap reference circuit and base current compensation circuit Download PDFInfo
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- CN104375553A CN104375553A CN201410756287.0A CN201410756287A CN104375553A CN 104375553 A CN104375553 A CN 104375553A CN 201410756287 A CN201410756287 A CN 201410756287A CN 104375553 A CN104375553 A CN 104375553A
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Abstract
The invention discloses a base current compensation circuit for the bandgap reference of a double triode PN junction tandem structure. The circuit comprises a first current mirror mirroring the branch current to be compensated, a sampling triode receiving the mirrored branch current to sample the base current of a triode to be compensated, and a second current mirror mirroring the base current and outputting to a branch to be compensated. The accuracy is guaranteed, and the situation that the reference voltage coefficient is large caused by the base current can be eliminated effectively. The invention further discloses a bandgap reference circuit with the base current compensation circuit, the effect of operational amplifier offset voltage can be reduced, and the situation that the reference voltage coefficient is large caused by the base current is eliminated.
Description
Technical Field
The present application relates to integrated circuits, and more particularly to voltage reference sources for use in integrated circuits.
Background
The voltage reference source is widely applied to analog and digital-analog hybrid integrated circuits as an independent functional module, and the performance of the voltage reference source determines the reliability of the whole chip. The circuit structures of the voltage reference sources are many, and the band-gap reference sources are widely applied.
The conventional band-gap reference source will affect the current density of the collector of the triode due to the existence of the base current, and the consistency of the collector currents of the triode on the two branches of the input end of the operational amplifier cannot be ensured, so that a larger reference voltage temperature drift coefficient is caused, and base current compensation is required. For example: the invention patent application with the application number of 201010127309.9 and the name of 'self-adaptive base current compensation curvature corrected band gap reference source' discloses a band gap reference source comprising a self-adaptive base current compensation circuit, which is used for compensating the situation that only one triode is arranged in one branch. However, the offset voltage of the operational amplifier with the band gap reference structure has a large error ratio to the output voltage, and the offset voltage changes along with the temperature, so that the temperature coefficient of the output voltage is increased.
Generally, the input offset voltage influence of the operational amplifier is reduced by using a structure of connecting two PN junctions in series, namely: the branch circuit of the input end of the operational amplifier is connected in series through two PNP triodes, and the base electrode of one PNP triode is connected to the emitting electrode of the other PNP triode. The junction voltage of the negative temperature coefficient of the base electrode-emitting electrode of the triode and the voltage difference of the base electrode and the emitting electrode with positive temperature coefficients are added to obtain the reference voltage independent of temperature. Namely: the zero temperature coefficient output is obtained by taking two quantities with opposite temperature coefficients and adding them with appropriate weights. As shown in fig. 1, the conventional bandgap reference source includes a cascode current mirror (MOS transistors M3, M6, M1, M7, M2, M8, M9, M4, M33, M34), an operational amplifier a1, a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q7, and resistors R1 and R2. The characteristics of the triodes are the same, and the emitter junction areas of the triodes Q1, Q2 and Q7 are 1/n of those of Q3 and Q4.
The negative temperature coefficient is derived as follows:
the voltage VBE of the emitter and the base of the PNP triode is as follows:
VT denotes a thermal voltage with a positive temperature coefficient (VT ═ kT/q, k IS boltzmann constant, q IS an electronic charge), IC denotes a collector current, and IS denotes a saturation current.
Assuming the IC remains unchanged, the derivative of VBE with respect to temperature T:
eg ≈ 1.12eV is the bandgap energy of silicon, m ≈ 1.5.
Equation (2) gives the temperature coefficient of the base-emitter voltage at a given temperature T.
The positive temperature coefficient voltage generation is derived as:
neglecting the base current, the collector currents of the transistors Q1 and Q3 are equal, and the collector currents of the transistors Q2 and Q4 are equal. Then from equation (3) it follows:
2ΔVBE＝2VT ln n (4)
therefore, the output reference voltage obtained by adding the positive and negative temperature coefficients is as shown in equation (5):
VOUT＝k1VBE+k2ΔVBE (5)
the reference output of zero temperature coefficient can be obtained by properly selecting the values of K1 and K2.
In the actual circuit, the collector currents of the transistors Q1 and Q3 and Q2 and Q4 are not equal due to the existence of the base current, and the current flows as shown in fig. 2, which can be obtained by the following steps in fig. 2:
IE＝IE1＝IE2＝IE3＝IE4 (6)
IE1＝IB1+IC1-IB2 (7)
IE3＝IB3+IC3-IB4 (8)
IE2＝IB2+IC2 (9)
IE4＝IB4+IC4 (10)
IE＝(1+β)IB (11)
the compounds represented by formulas (6) to (11) can be obtained by bringing formula (3):
in equation (12), collector current IC2 is approximately equal to IC4, and thus equation (13) is obtained.
As can be seen from equation (13), the base current is introduced in the equation (second term in parentheses) compared to the case of neglecting the base current. The reference output will be unstable due to the uncertainty in the base currents IB1 and IB 3.
In addition, when the circuit works, the triode is in a linear region, the chip adopts a CMOS (complementary metal oxide semiconductor) process, the current amplification factor beta of the triode is very small, the current flowing into the base electrode of the emitter is relatively large, and the existence of the base electrode current causes a large reference voltage temperature drift coefficient. Therefore, as described in the patent application with application number 201010555886.8 entitled "a high-precision bandgap reference source circuit based on emitter current compensation", the bandgap reference source with such a structure is subjected to base current compensation to eliminate the phenomenon that the temperature coefficient of the reference voltage is large due to the base current. However, the invention patent application does not disclose a specific structure of the base compensation circuit.
Disclosure of Invention
One of the purposes of the present application is to provide a base current compensation circuit for a bandgap reference source of a double-triode PN junction series structure, which can sample and obtain a compensation current having the same characteristic as a base current, and effectively reduce the phenomenon of a large temperature coefficient of a reference voltage caused by the base current while ensuring the accuracy of compensation.
Another objective of the present application is to provide a bandgap reference source circuit including the above base current compensation circuit, which reduces the influence of offset voltage of the operational amplifier and also reduces the phenomenon of large temperature coefficient of the reference voltage caused by the base current.
According to a first aspect of the present application, a base current compensation circuit for a bandgap reference source is provided, a branch where a transistor to be compensated in the bandgap reference source is located is connected, an input end of an operational amplifier of the bandgap reference source is connected to a PN junction series structure of a dual transistor, and the compensation circuit includes:
a first current mirror mirroring the current of the branch;
the sampling triode receives the branch current of the mirror image so as to sample the base current of the triode to be compensated; and
and the second current mirror mirrors the base current obtained by sampling of the sampling triode and outputs the base current to the branch circuit.
According to the scheme, compensation current is sampled from the triode to be compensated through the triode with the same characteristics, and the branch to be compensated is added, so that the phenomenon that the reference voltage temperature coefficient is large due to base current is effectively reduced.
In some embodiments, the second current mirror comprises:
the N-type cascode current mirror mirrors the base current output by the sampling triode; and
and the P-type cascode current mirror mirrors the base current output by the N-type cascode current mirror and outputs the base current to the branch circuit. The compensation current with the same characteristics as the base current is obtained through the cascade current source mirror image, and the compensation accuracy is guaranteed.
In some embodiments, the N-type cascode current mirror includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein,
the drain electrode of the third NMOS tube is connected with the output end of the sampling triode, the grid electrode of the third NMOS tube is connected with the output end of the first current mirror, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube;
the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is connected with the output end of the sampling triode;
the source electrode of the second NMOS tube is grounded, the grid electrode of the second NMOS tube is connected with the output end of the sampling triode, and the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube;
the grid electrode of the first NMOS tube is connected with the output end of the first current mirror;
the P-type cascode current mirror comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein,
the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the fourth PMOS tube is connected with bias voltage, and the source electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube;
the source electrode of the third PMOS tube is connected with a power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first PMOS tube is connected with a power supply, the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube, and the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube;
and the grid electrode of the second PMOS tube is connected with bias voltage, and the drain electrode of the second PMOS tube is connected with the branch circuit.
In some embodiments, the first current mirror comprises: a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube, wherein,
the source electrode of the fifth PMOS tube is connected with a power supply, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube;
the grid electrode of the sixth PMOS tube is connected with bias voltage;
the source electrode of the seventh PMOS tube is connected with a power supply, the grid electrode of the seventh PMOS tube is connected with the output end of the operational amplifier, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the eighth PMOS tube is connected with bias voltage;
and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the eighth PMOS tube and serves as the output end of the first current mirror.
In some embodiments, the characteristics and the emitter junction area of the sampling triode and the triode to be compensated are the same, the emitter of the sampling triode is connected with the output end of the first current mirror, the collector of the sampling triode is grounded, and the base of the sampling triode is used as the output end of the sampling triode.
According to a second aspect of the present invention, there is provided a bandgap reference source circuit comprising:
an operational amplifier;
the first triode PN junction series branch circuit is connected with the inverting input end of the operational amplifier and comprises a first triode to be compensated;
the second double triode PN junction series branch circuit is connected with the non-inverting input end of the operational amplifier and comprises a third triode to be compensated; and
a fifth triode to be compensated in the reference voltage output branch;
the bandgap reference source circuit further includes:
the base current compensation circuit according to the first aspect of the present invention compensates the base current of the first triode for the PN junction series branch of the first triode;
the base current compensation circuit of the first aspect of the present invention compensates the base current of the third triode for the PN junction series branch of the second triode; and
the base current compensation circuit according to the first aspect of the present invention compensates the base current of the fifth transistor for the reference voltage output branch.
According to the scheme, the compensation accuracy is guaranteed, and meanwhile the phenomenon that the temperature coefficient of the reference voltage is large due to the base current can be effectively reduced.
In some embodiments, the first triac PN junction series branch further comprises a second triac;
the PN junction series branch of the second triode further comprises a fourth triode;
the bandgap reference source circuit further includes: a cascode current mirror for leading out the first to fifth current output terminals;
the base electrode of the first triode is grounded, the collector electrode of the first triode is grounded, and the emitter electrode of the first triode is connected with the first current output end;
the emitter of the second triode is connected with the inverting input end of the operational amplifier and the second current output end, the collector is grounded, and the base is connected with the emitter of the first triode;
an emitter of the fourth triode is connected with a non-inverting input end and a third current output end of the operational amplifier through a first resistor, a collector is grounded, and a base is connected with an emitter of the third triode;
an emitter of the third triode is connected with the fourth current output end, a base of the third triode is grounded, and a collector of the third triode is grounded;
the base electrode of the fifth triode is grounded, the collector electrode of the fifth triode is grounded, and the emitter electrode of the fifth triode is connected with the fifth current output end through the second resistor; the fifth current output end is a reference voltage output end;
and the emitter of the second triode, the emitter of the fourth triode and the emitter of the fifth triode are respectively connected with the output ends of the base current compensation circuits respectively corresponding to the emitters.
In some embodiments, the first, second and fifth transistors each have an emitter junction area that is 1/n of the emitter junction area of the third and fourth transistors.
Drawings
FIG. 1 shows a conventional bandgap reference circuit;
FIG. 2 schematically illustrates the flow of current before compensation in the circuit of FIG. 1;
FIG. 3 schematically indicates the flow of compensation current in the circuit of FIG. 1;
FIG. 4 is a circuit diagram of a bandgap reference source circuit in accordance with one embodiment of the present invention;
FIG. 5 is a circuit diagram of a base current compensation circuit of the bandgap reference circuit shown in FIG. 4;
FIG. 6 is a graph of output voltage versus temperature without the base current compensation circuit;
FIG. 7 is a graph of output voltage versus temperature using a base current compensation circuit;
FIG. 8 shows the power supply output current without the base compensation current circuit added;
fig. 9 shows the case of the power supply output current added to the base compensation current circuit.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the conventional bandgap reference circuit adopts a classic two-transistor bandgap reference source structure (a dual-transistor PN junction series structure), so that the influence of input offset voltage of the operational amplifier can be effectively reduced. Specifically, the bandgap reference circuit includes: the circuit comprises a cascode current mirror, an operational amplifier A1, first to fifth triodes Q1-Q5, a first resistor R1 and a second resistor R2, wherein:
the cascode current mirror leads out first to fifth current output ends Iout1 to Iout5, and each current output end outputs the same mirror current. The cascode current mirror is composed of PMOS tubes M3, M6, M1, M7, M2, M8, M4, M9, M33 and M34. Every two PMOS tubes form a group of cascode structures, and a current output end is led out. Taking PMOS transistors M3, M6 as examples: the source electrode and the substrate of the PMOS tube M6 are connected with a power supply VDDA, the drain electrode is connected with the source electrode of the PMOS tube M3, and the grid electrode is connected with the output end of the operational amplifier A1; the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M6, the substrate is connected to a power supply VDDA, the gate is connected to a bias voltage (the gates of the PMOS transistors M1, M2, M4, and M33 are connected to serve as the bias voltage of the cascode structure), and the drain is a first current output terminal Iout 1.
The first triode Q1 and the second triode Q2 form a first triode PN junction series branch. The base of the first triode Q1 is grounded, the collector is grounded, and the emitter is connected with the first current output end Iout 1. The emitter of the second triode Q2 is connected with the inverting input end of the operational amplifier A1 and the second current output end Iout2, the collector is grounded, and the base is connected with the emitter of the first triode Q1.
The third triode Q3 and the fourth triode Q4 form a second double-triode PN junction series branch; the emitter of the fourth triode Q4 is connected with the non-inverting input terminal of the operational amplifier a1 and the third current output terminal Iout3 through the first resistor R1, the collector is grounded, and the base is connected with the emitter of the third triode Q3. An emitter of the third triode Q3 is connected with the fourth current output end Iout4, a base of the third triode Q3 is grounded, and a collector of the third triode Q3 is grounded.
The fifth transistor Q7 is in the reference voltage output branch. The base electrode of the fifth triode Q7 is grounded, the collector electrode is grounded, and the emitter electrode is connected with the fifth current output end Iout5 through a second resistor R2; the fifth current output terminal Iout5 serves as a reference voltage output terminal VOUT.
The characteristics of all the triodes are the same. The emitter junction areas of the first transistor Q1, the second transistor Q2, and the fifth transistor Q7 are each 1/n of the emitter junction area of the third transistor Q3 and the fourth transistor Q4.
The conventional bandgap reference circuit is used as a part of the bandgap reference source circuit of the invention, and can effectively reduce the influence of input offset voltage of the operational amplifier. Meanwhile, in order to eliminate the phenomenon that the temperature coefficient of the reference voltage is large due to the base current, the band-gap reference source circuit further comprises a base current compensation part, and the base current compensation part is realized by taking the base current compensation circuit as the basis. The base current compensation circuit of one embodiment of the present invention is described in detail below:
according to one embodiment of the invention, the base current compensation circuit is applied to a band-gap reference source in which two triodes are connected in series in one branch, namely, the input end of an operational amplifier A1 of the band-gap reference source is connected with a double-triode PN junction series structure. The base current compensation circuit is connected with a branch where a triode to be compensated in a band gap reference source is located. Taking the bandgap reference circuit of fig. 1 as an example, as shown in fig. 3, the bandgap reference circuit includes a first triode PN junction series branch (the first triode Q1 is the triode to be compensated), a second triode PN junction series branch (the third triode Q3 is the triode to be compensated), and a reference voltage output branch (the fifth triode Q7 is the triode to be compensated).
According to one embodiment of the present invention, a base current compensation circuit includes: the sampling circuit comprises a first current mirror, a sampling triode and a second current mirror. The first current mirror is used for mirroring the current of the branch circuit needing compensation;
the sampling triode Q5 receives the mirrored branch current to sample the base current of the triode to be compensated;
the second current mirror mirrors the base current output by the sampling transistor Q5 and outputs the base current to the branch needing compensation.
Specifically, referring to fig. 5, the characteristics and the emitter junction area of the sampling transistor Q5 are the same as those of the transistor to be compensated, the emitter of the sampling transistor Q5 is connected to the output end of the first current mirror, the collector is grounded, and the base is used as the output end of the sampling transistor.
The second current mirror includes: an N-type cascode current mirror and a P-type cascode current mirror.
The N type cascode current mirror is used for mirroring the base current output by the sampling triode, and specifically comprises: a first NMOS transistor M17, a second NMOS transistor M18, a third NMOS transistor M19, and a fourth NMOS transistor M20.
The drain of the third NMOS transistor M19 is connected to the output terminal of the sampling transistor Q5 (the base of the sampling transistor Q5, the same applies below), the gate is connected to the output terminal of the first current mirror, and the source is connected to the drain of the fourth NMOS transistor M20.
The source of the fourth NMOS transistor M20 is grounded, and the gate is connected to the output terminal of the sampling transistor Q5.
The source of the second NMOS transistor M18 is grounded, the gate is connected to the output terminal of the sampling transistor Q5, and the drain is connected to the source of the first NMOS transistor M17.
The gate of the first NMOS transistor M17 is connected to the output terminal of the first current mirror.
The substrate of each of the first NMOS transistor M17, the second NMOS transistor M18, the third NMOS transistor M19 and the fourth NMOS transistor M20 is grounded.
And the P-type cascode current mirror is used for mirroring the base current output by the N-type cascode current mirror and outputting the base current to a branch circuit needing compensation. Specifically, the P-type cascode current mirror comprises a first PMOS transistor M10, a second PMOS transistor M5, a third PMOS transistor M12 and a fourth PMOS transistor M11. Wherein,
the drain electrode of the fourth PMOS tube M11 is connected with the drain electrode of the first NMOS tube M17, the grid electrode is connected with the bias voltage Vbias2 of the cascode structure, and the source electrode is connected with the drain electrode of the third PMOS tube M12;
the source electrode of the third PMOS tube M12 is connected with a power supply VDDA, and the grid electrode is connected with the drain electrode of the first NMOS tube M17;
the source electrode of the first PMOS tube M10 is connected with a power supply, the drain electrode is connected with the source electrode of the second PMOS tube M5, and the grid electrode is connected with the drain electrode of the first NMOS tube M17;
the gate of the second PMOS transistor M5 is connected to the bias voltage Vbias2, and the drain is connected to the branch requiring compensation.
The substrates of the first PMOS transistor M10, the second PMOS transistor M5, the third PMOS transistor M12 and the fourth PMOS transistor M11 are connected with a power supply VDDA.
The first current mirror includes: a fifth PMOS transistor M14, a sixth PMOS transistor M13, a seventh PMOS transistor M16, and an eighth PMOS transistor M15.
The source of the fifth PMOS transistor M14 is connected to the power supply VDDA, the drain is connected to the source of the sixth PMOS transistor M13, and the gate is connected to the drain of the first NMOS transistor M17.
The gate of the sixth PMOS transistor M13 is coupled to the bias voltage.
The source of the seventh PMOS transistor M16 is connected to the power supply VDDA, the gate is connected to the output terminal Vbias1 of the operational amplifier a1, and the drain is connected to the source of the eighth PMOS transistor M15.
The gate of the eighth PMOS transistor M15 is coupled to the bias voltage.
The drain of the sixth PMOS transistor M13 is connected to the drain of the eighth PMOS transistor M15, and serves as the output terminal of the first current mirror.
The substrates of the fifth PMOS transistor M14, the sixth PMOS transistor M13, the seventh PMOS transistor M16 and the eighth PMOS transistor M15 are connected to a power supply VDDA.
In summary, the base current compensation part included in the bandgap reference source circuit of the present invention includes:
a base current compensation circuit for compensating the base current of the first triode Q1 for the PN junction series branch of the first triode;
a base current compensation circuit for compensating the base current of the third triode Q3 for the PN junction series branch of the second triode; and
and a base current compensation circuit for compensating the base current of the fifth triode Q7 for the reference voltage output branch.
Since the emitter junction areas of the first transistor Q1, the second transistor Q2, and the fifth transistor Q7 are 1/n of the emitter junction areas of the third transistor Q3 and the fourth transistor Q4, the current IA is compensated for in the first dual transistor PN junction series branch, as shown in fig. 3; compensating current InA for a PN junction series branch of a second triode; the reference voltage output branch is compensated for current IA.
Therefore, referring to fig. 4, the base current compensation portion included in the bandgap reference source circuit of the present invention includes:
the base current compensation module a, which is connected to the emitter of the second transistor Q2 and compensates the current IA, corresponds to the base current compensation circuit of the present invention, and is composed of a transistor Q6, PMOS transistors M21, M22, M23, M24, M25, M26, M27, M28, and NMOS transistors M29, M30, M31, and M32.
And a base current compensation module nA which is connected with the emitter of the fourth triode Q4 and compensates the current InA, namely the base current compensation circuit of the invention.
And a compensation current IA output by the mirror image base electrode current compensation module A is connected with an emitter electrode of the fifth triode Q7 and compensates the current IA.
The operation principle of the current compensation circuit is explained in conjunction with the actual circuit. Taking the base current compensation module nA (i.e., the base current compensation circuit of the present invention) as an example, the analysis is performed.
As shown in fig. 5, all cascode current mirrors are guaranteed to be in mirror relation, and are derived by: since the currents flowing into the cascode current sources M19 and M20 are the base currents of Q5, and the base currents of the cascode current sources M17 and M18 mirror Q5, then through the mirror relationship of M11, M12, M5 and M10, InA, which is the base current of Q5, can be obtained; since M13, M14, M15, M16 and the output bias of the operational amplifier ensure that Q5 and Q3 are in the same operating state, and Q5 and Q3 have the same emitter area and tube characteristics, it can be found that the base currents of Q5 and Q3 are the same, and similarly, it can be found that IA is equal to the base currents of Q6 and Q1. The following formula can thus be derived:
InA＝IB3 (14)
IA＝IB1 (15)
from the current trend of fig. 3 and from kirchhoff current rules, one can obtain:
IE＝IC1+IB1-IB2＝IC2+IB2-IB1 (16)
IE＝IC3+IB3-IB4＝IC4+IB4-IB3 (17)
by bringing formulae (16) and (17) into formula (13):
since the collector currents of Q4 and Q2 are equal, equation (18) can be converted to:
2ΔVBE＝2VT ln n (19)
the formula (19) is the same as the formula (4). Since the base current is eliminated, the temperature drift phenomenon of the reference voltage caused by the current flowing in the emitter is eliminated.
And verifying the base current compensation circuit. Fig. 6 and 7 are temperature drift characteristics before and after compensation with the base current. Fig. 6 shows the output voltage versus temperature without the base current compensation circuit. Fig. 7 shows the output voltage versus temperature curve after the base current compensation circuit is used. Scanning the temperature zone from-55 ℃ to 125 ℃. In the variation range of the whole temperature zone, the variation range of the output reference of FIG. 6 with the temperature is 2.7mV, and the corresponding temperature drift coefficient is 12.35 ppm/deg.C. In the variation range of the whole temperature zone, the variation range of the output reference of FIG. 7 with the temperature is 1.85mV, and the corresponding temperature drift coefficient is 8.44 ppm/deg.C.
After the starting circuit is included, when the power supply voltage is 2.5V, the power supply current is aligned in front and back directions after the compensation current circuit is added, as shown in fig. 8 and 9. FIG. 8 shows the output current of the power supply without the current compensation circuit, which is 20.51uA according to the output result; fig. 9 shows the output current of the power supply added with the current compensation circuit, and 21.01uA can be obtained through the output result. After the base current compensation circuit is added, the power supply current is only increased by 0.5uA, and the increased power consumption is very small.
In summary, the cascode current mirror and the base current sampling triode can compensate the base current with the same magnitude and characteristics as the base current. Through comparison of actual circuit verification results, the base current compensation circuit of the invention has obvious effect of improving the temperature curve of the reference output, and therefore, the band-gap reference output with high stability can be obtained.
The foregoing are only some embodiments of the invention. It will be apparent to those skilled in the art that several similar changes and modifications can be made without departing from the inventive concept herein, and these are to be considered within the scope of the invention.
Claims (8)
1. The utility model provides a band gap is base current compensation circuit for reference source, connects the branch road at the triode that waits to compensate in the band gap reference source, the input termination of the operational amplifier of band gap reference source is two triode PN junction series connection structure, its characterized in that includes:
a first current mirror mirroring the current of the branch;
the sampling triode receives the branch current of the mirror image so as to sample the base current of the triode to be compensated; and
and the second current mirror mirrors the base current obtained by sampling of the sampling triode and outputs the base current to the branch circuit.
2. The base current compensation circuit for a bandgap reference source according to claim 1, wherein the second current mirror comprises:
the N-type cascode current mirror mirrors the base current output by the sampling triode; and
and the P-type cascode current mirror mirrors the base current output by the N-type cascode current mirror and outputs the base current to the branch circuit.
3. The base current compensation circuit for a bandgap reference according to claim 2,
the N-type cascode current mirror comprises a first NMOS transistor (M17), a second NMOS transistor (M18), a third NMOS transistor (M19) and a fourth NMOS transistor (M20), wherein,
the drain electrode of the third NMOS tube (M19) is connected with the output end of the sampling triode, the grid electrode of the third NMOS tube is connected with the output end of the first current mirror, and the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube (M20);
the source electrode of the fourth NMOS tube (M20) is grounded, and the grid electrode of the fourth NMOS tube is connected with the output end of the sampling triode;
the source electrode of the second NMOS tube (M18) is grounded, the grid electrode of the second NMOS tube is connected with the output end of the sampling triode, and the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube (M17);
the grid electrode of the first NMOS tube (M17) is connected with the output end of the first current mirror;
the P-type cascode current mirror comprises a first PMOS tube (M10), a second PMOS tube (M5), a third PMOS tube (M12) and a fourth PMOS tube (M11), wherein,
the drain electrode of the fourth PMOS tube (M11) is connected with the drain electrode of the first NMOS tube (M17), the grid electrode of the fourth PMOS tube is connected with bias voltage, and the source electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube (M12);
the source electrode of the third PMOS tube (M12) is connected with a power supply, and the grid electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube (M17);
the source electrode of the first PMOS tube (M10) is connected with a power supply, the drain electrode of the first PMOS tube (M10) is connected with the source electrode of the second PMOS tube (M5), and the grid electrode of the first PMOS tube (M17) is connected with the drain electrode of the first NMOS tube;
the grid electrode of the second PMOS tube (M5) is connected with bias voltage, and the drain electrode of the second PMOS tube is connected with the branch circuit.
4. The base current compensation circuit for a bandgap reference source according to claim 3, wherein the first current mirror comprises: a fifth PMOS transistor (M14), a sixth PMOS transistor (M13), a seventh PMOS transistor (M16), and an eighth PMOS transistor (M15), wherein,
the source electrode of the fifth PMOS tube (M14) is connected with a power supply, the drain electrode of the fifth PMOS tube (M14) is connected with the source electrode of the sixth PMOS tube (M13), and the grid electrode of the fifth PMOS tube is connected with the drain electrode of the first NMOS tube (M17);
the grid electrode of the sixth PMOS tube (M13) is connected with a bias voltage;
the source electrode of the seventh PMOS tube (M16) is connected with a power supply, the grid electrode of the seventh PMOS tube is connected with the output end of the operational amplifier, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube (M15);
the grid electrode of the eighth PMOS tube (M15) is connected with a bias voltage;
the drain electrode of the sixth PMOS tube (M13) is connected with the drain electrode of the eighth PMOS tube (M15) and is used as the output end of the first current mirror.
5. The base current compensation circuit for a bandgap reference source as claimed in claim 4, wherein the sampling transistor and the transistor to be compensated have the same characteristics and emitter junction area, and the emitter of the sampling transistor is connected to the output terminal of the first current mirror, the collector is grounded, and the base is used as the output terminal of the sampling transistor.
6. A bandgap reference source circuit comprising:
an operational amplifier;
the first triode PN junction series branch circuit is connected with the inverting input end of the operational amplifier and comprises a first triode (Q1) to be compensated;
the second double triode PN junction series branch circuit is connected with the non-inverting input end of the operational amplifier and comprises a third triode (Q3) to be compensated; and
a fifth transistor (Q7) to be compensated in the reference voltage output branch;
wherein the bandgap reference source circuit further comprises:
the base current compensation circuit of any of claims 1 to 5 for compensating said first triac PN junction series branch for a base current of a first transistor (Q1);
the base current compensation circuit of any of claims 1 to 5 for compensating said second triac PN junction series branch for a base current of a third triode (Q3); and
the base current compensation circuit of any of claims 1 to 5 that compensates the reference voltage output branch for the base current of a fifth transistor (Q7).
7. The bandgap reference source circuit as recited in claim 6,
the first triode PN junction series branch further comprises a second triode (Q2);
the second triode PN junction series branch further comprises a fourth triode (Q4);
the bandgap reference source circuit further includes: a cascode current mirror for leading out the first to fifth current output terminals;
the base electrode of the first triode (Q1) is grounded, the collector electrode of the first triode is grounded, and the emitter electrode of the first triode is connected with the first current output end;
the emitter of the second triode (Q2) is connected with the inverting input end of the operational amplifier and the second current output end, the collector is grounded, and the base is connected with the emitter of the first triode (Q1);
the emitter of the fourth triode (Q4) is connected with the non-inverting input end and the third current output end of the operational amplifier through a first resistor (R1), the collector is grounded, and the base is connected with the emitter of the third triode (Q3);
the emitter of the third triode (Q3) is connected with the fourth current output end, the base is grounded, and the collector is grounded;
the base electrode of the fifth triode (Q7) is grounded, the collector electrode of the fifth triode is grounded, and the emitter electrode of the fifth triode is connected with the fifth current output end through a second resistor (R2); the fifth current output end is a reference voltage output end;
and the emitter of the second triode (Q2), the emitter of the fourth triode (Q4) and the emitter of the fifth triode (Q7) are respectively connected with the output ends of the base current compensation circuits corresponding to the emitters.
8. The bandgap reference source circuit as claimed in claim 7, wherein the emitter junction areas of the first transistor (Q1), the second transistor (Q2) and the fifth transistor (Q7) are 1/n of the emitter junction area of the third transistor (Q3) and the fourth transistor (Q4).
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