CN116069114A - Bandgap Reference Circuit - Google Patents

Abstract

The present disclosure provides bandgap reference circuits. The band gap reference circuit comprises a band gap reference sub-circuit, a compensation current generation sub-circuit and a current mirror sub-circuit; the current mirror sub-circuit is respectively connected with the compensation current generation sub-circuit and the band gap reference sub-circuit; the band gap reference sub-circuit is used for generating a band gap reference voltage; the compensation current generation sub-circuit is used for generating compensation current with temperature characteristics; the current mirror sub-circuit is used for mirroring the compensation current to generate mirror current, and voltage compensation is carried out on the band gap reference voltage through the mirror current.

Description

Bandgap Reference Circuit

technical field

The present disclosure relates to electronic circuits, and more particularly, to a bandgap reference circuit.

Background technique

Since the resistors, transistors and other devices in the analog circuit have a certain temperature coefficient, the basic voltage provided is affected by the temperature to a certain extent, resulting in deviation. In analog circuits, a voltage reference that is almost independent of temperature is often required to provide accurate biasing for transistors and other circuit components, so bandgap reference circuits are widely used.

The principle of the bandgap reference circuit is to add two voltages with positive and negative temperature coefficients at a certain temperature with appropriate weights. Due to their opposite temperature characteristics, a voltage reference with zero temperature coefficient can be approximated to reduce Minimal output voltage variation due to temperature drift. However, since the two voltages with positive and negative temperature coefficients have different orders, there are high-order components that cannot be offset and compensated between the two voltages, resulting in insufficient accuracy of the bandgap reference circuit.

Contents of the invention

An object of the present disclosure is to provide a bandgap reference circuit for performing voltage compensation on the bandgap reference subcircuit, which can perform voltage compensation on the bandgap reference subcircuit and improve the accuracy of the bandgap reference subcircuit.

According to a first aspect of the present disclosure, a bandgap reference circuit is provided.

The bandgap reference circuit includes a bandgap reference subcircuit, a compensation current generation subcircuit and a current mirror subcircuit; the current mirror subcircuit is connected to the compensation current generation subcircuit and the bandgap reference subcircuit respectively; the The bandgap reference subcircuit is used to generate a bandgap reference voltage; the compensation current generation subcircuit is used to generate a compensation current with temperature characteristics; the current mirror subcircuit is used to mirror the compensation current to generate a mirror image current, and perform voltage compensation on the bandgap reference voltage through the mirror current.

Optionally, the compensation current generation sub-circuit includes a first triode; the collector of the first triode is connected to the working voltage terminal of the bandgap reference circuit; the emitter of the first triode The pole is connected to the bandgap reference subcircuit to provide an operating voltage to the bandgap reference subcircuit; the base of the first triode generates the compensation current.

Optionally, the compensation current generation sub-circuit includes a first triode; the collector of the first triode is connected to the working voltage terminal of the bandgap reference circuit; the emitter of the first triode The pole is connected to the first current source; the base of the first triode generates the compensation current.

Optionally, the current mirror subcircuit includes a first current mirror, a second current mirror, and a first resistor; the first mirror current port of the first current mirror, the base of the first triode, and the first resistor of the first resistor One end is respectively connected to the first circuit node; the first mirror current port of the second current mirror is connected to the second end of the first resistor; the second mirror current port of the first current mirror, the second mirror current port of the second current mirror The ports are respectively connected to the second circuit node; the current mirror subcircuit is connected to the bandgap reference subcircuit, including: the second circuit node is connected to the bandgap reference subcircuit.

Optionally, the first current mirror is a cascode current mirror.

Optionally, the first current mirror includes first to sixth PMOS transistors; the gates of the first to third PMOS transistors are connected together, and the sources of the first to third PMOS transistors are respectively connected to the bandgap reference The working voltage end of the circuit is connected; the gates of the fourth to sixth PMOS transistors are connected together; the drain of the first PMOS transistor is connected to the source of the fourth PMOS transistor, and the drain of the second PMOS transistor is connected to the fifth PMOS transistor The source of the third PMOS transistor is connected to the source of the sixth PMOS transistor; the drain of the fourth PMOS transistor is connected to the second current source, and the drain of the fifth PMOS transistor is connected to the first circuit node. The drain of the sixth PMOS transistor is connected to the second circuit node; the drain of the first PMOS transistor is connected to the gate, and the drain of the fourth PMOS transistor is connected to the gate; wherein, the drain of the fifth PMOS transistor is the first current The first mirror current port of the mirror, and the drain of the sixth PMOS transistor is the second mirror current port of the first current mirror.

Optionally, the second current mirror includes first to fourth NMOS transistors; the gate of the first NMOS transistor is connected to the gate of the second NOMS transistor; the gate of the third NMOS transistor is connected to the gate of the fourth NOMS transistor pole connection; the drain of the first NMOS transistor is connected to the second end of the first resistor, and the drain of the second NMOS transistor is connected to the second circuit node; the source of the first NMOS transistor is connected to the drain of the third NMOS transistor , the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; the drain of the first NMOS transistor is connected to the gate, and the drain and gate of the third PMOS transistor are connected; the source of the third NMOS transistor is connected to the gate of the fourth NMOS transistor. The sources of the fourth NOMS transistors are respectively grounded; wherein, the drain of the first NMOS transistor is the first mirror current port of the second current mirror, and the drain of the second NMOS transistor is the second mirror current port of the second current mirror.

Optionally, the bandgap reference subcircuit includes an operational amplifier, a second transistor, a third transistor, a second resistor, and a third resistor; the first input of the operational amplifier and the collector of the second transistor connection, the second input terminal is connected to the collector of the third transistor; the base of the second transistor is connected to the base of the third transistor, and the emitter of the third transistor is connected to the first resistor of the second resistor One end is connected, the emitter of the second transistor is connected to the second end of the second resistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is grounded; the operational amplifier The output terminal of the third transistor is connected to the base of the third transistor to output the bandgap reference voltage; the second circuit node is connected to the bandgap reference subcircuit, including: the second circuit node and the third resistor The first end is connected.

Optionally, the bandgap reference subcircuit includes an operational amplifier, a second triode, a third triode, a second resistor, a third resistor, and a fourth resistor; the first input of the operational amplifier and the second triode The collector of the transistor is connected, the second input terminal is connected with the collector of the third transistor; the base of the second transistor is connected with the base of the third transistor, and the emitter of the third transistor is connected with the third transistor The first end of the second resistor is connected, the emitter of the second triode is connected to the second end of the second resistor; the second end of the second resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor It is connected to the first end of the third resistor, and the second end of the third resistor is grounded; the output end of the operational amplifier is connected to the base of the second triode to output the bandgap reference voltage; the second circuit node is connected to the The bandgap reference subcircuit connection includes: the second circuit node is connected to the first end of the third resistor.

Optionally, the first transistor is an NPN transistor, the second transistor is an NPN transistor, and the third transistor is an NPN transistor.

The bandgap reference circuit provided by the embodiments of the present disclosure has a high-order temperature compensation function, which makes the bandgap reference circuit more insensitive to temperature changes, and the output bandgap reference voltage curve is gentler and has smaller amplitude changes, realizing Output of high precision bandgap reference voltage.

Other features of the present disclosure and advantages thereof will become apparent through the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram of a bandgap reference circuit provided by an embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a bandgap reference circuit provided by an embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a bandgap reference circuit provided by an embodiment of the present disclosure;

FIG. 4 is a voltage curve diagram provided by an embodiment of the present disclosure without compensating the bandgap reference voltage;

FIG. 5 is a voltage curve diagram for compensating a bandgap reference voltage provided by an embodiment of the present disclosure.

Explanation of reference signs

Operational amplifier Amp;

The first resistor-R6, the second resistor-R3, the third resistor-R5, the fourth resistor-R4, the fifth resistor-R1, the sixth resistor-R2;

The first triode-Q3, the second triode-Q1, the third triode-Q2;

The first PMOS transistor-MP1, the second PMOS transistor-MP2, the third PMOS transistor-MP3, the fourth PMOS transistor-MP4, the fifth PMOS transistor-MP5, the sixth PMOS transistor-MP6;

The first NMOS transistor-MN1, the second NMOS transistor-MN2, the third NMOS transistor-MN3, and the fourth NMOS transistor-MN4.

Detailed ways

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and in no way intended as any limitation of the disclosure, its application or uses.

Techniques and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques and devices should be considered part of the description.

In all examples shown and discussed herein, any specific values should be construed as exemplary only, and not as limitations. Therefore, other instances of the exemplary embodiment may have different values.

It should be noted that like numerals and letters denote like items in the following figures, therefore, once an item is defined in one figure, it does not require further discussion in subsequent figures.

Explanation of English abbreviations:

MOS tube: Metal Oxide Semiconductor, metal-oxide semiconductor field effect transistor. PMOS tube: Positive channel Metal-Oxide-Semiconductor, P-channel MOS tube. NMOS tube: Negativechannel Metal-Oxide-Semiconductor, N-channel MOS tube.

Referring to FIG. 1 , an embodiment of the present disclosure provides a bandgap reference circuit. The bandgap reference circuit includes a bandgap reference subcircuit 100 , a compensation current generating subcircuit 200 and a current mirroring subcircuit 300 . The current mirror subcircuit 300 is connected to the compensation current generation subcircuit 200 and the bandgap reference subcircuit 100 respectively. The bandgap reference subcircuit 100 is used to generate a bandgap reference voltage. The compensation current generation sub-circuit 200 is used to generate a compensation current with temperature characteristics. The current mirroring sub-circuit 300 is used to mirror the compensation current to generate a mirror current, and perform voltage compensation to the bandgap reference voltage through the mirror current.

In the embodiment of the present disclosure, the compensation current generation subcircuit 200 is used to generate a compensation current with high-order temperature characteristics, so as to provide high-order temperature compensation for the bandgap reference voltage output by the bandgap reference subcircuit 100 . In the embodiments of the present disclosure, the second-order and higher-order temperature characteristics are high-order temperature characteristics. The high-order temperature characteristics of the triode can be used to generate a compensation current with high-order temperature characteristics.

In one example, as shown in FIG. 2 , the compensation current generating sub-circuit 200 includes a first transistor Q3. The collector of the first transistor Q3 is connected to the working voltage terminal VCC of the bandgap reference circuit. The emitter of the first transistor Q3 is connected to the bandgap reference subcircuit 100 to provide an operating voltage to the bandgap reference subcircuit 100 . The base of the first transistor Q3 generates a compensation current I5.

In another example, the emitter of the first transistor Q3 is changed not to be connected to the bandgap reference sub-circuit 100, but to be connected to the first current source. The first current source is not shown in the figure, it only needs to be able to provide a current source for the first transistor Q3.

In one example, the first transistor Q3 is an NPN transistor.

Referring to FIG. 2 below, the bandgap reference circuit provided by the embodiment of the present disclosure will be described.

The compensation current generating sub-circuit 200 includes a first transistor Q3. The collector of the first transistor Q3 is connected to the working voltage terminal VCC of the bandgap reference circuit. The emitter of the first transistor Q3 is connected to the bandgap reference subcircuit 100 to provide an operating voltage to the bandgap reference subcircuit 100 . The base of the first transistor Q3 generates a compensation current I5.

The current mirror sub-circuit 300 includes a first current mirror, a second current mirror and a first resistor R6. The first mirror current port A1 of the first current mirror, the base of the first transistor Q3, and the first end of the first resistor R6 are respectively connected to the first circuit node C1. The first mirror current port B1 of the second current mirror is connected to the second end of the first resistor R6. The second mirror current port A2 of the first current mirror and the second mirror current port B2 of the second current mirror are respectively connected to the second circuit node C2. The current mirror subcircuit 300 is connected to the bandgap reference subcircuit 100 means that the second circuit node C2 is connected to the bandgap reference subcircuit 100 .

The first current mirror is connected to the current source, and mirrors the current output by the current source. The specific circuit of the first current mirror is designed so that the currents at the first mirror current port A1 of the first current mirror and the second mirror current port A2 of the first current mirror are the same, and the specific circuit of the second current mirror is designed such that The currents at the first mirror current port B1 of the second current mirror and the second mirror current port B2 of the second current mirror are the same.

In one example, the first current mirror is a cascode current mirror. In one example, the first current mirror includes first to sixth PMOS transistors. Gates of the first PMOS transistor MP1 , the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected together. The sources of the first PMOS transistor MP1 , the second PMOS transistor MP2 and the third PMOS transistor MP3 are respectively connected to the working voltage terminal VCC of the bandgap reference circuit. Gates of the fourth PMOS transistor MP4 , the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected together. The drain of the first PMOS transistor MP1 is connected to the source of the fourth PMOS transistor MP4, the drain of the second PMOS transistor MP2 is connected to the source of the fifth PMOS transistor MP5, and the drain of the third PMOS transistor MP3 is connected to the sixth PMOS transistor. Source connection of tube MP6. The drain of the fourth PMOS transistor MP4 is connected to the second current source Idc. The drain of the fifth PMOS transistor MP5 is connected to the first circuit node C1, that is, the drain of the fifth PMOS transistor MP5 is connected to the first end of the first resistor R6 and the base of the first transistor Q3 respectively. The drain of the sixth PMOS transistor MP6 is connected to the second circuit node C2, that is, the drain of the sixth PMOS transistor MP6 is connected to the second mirror current port B2 of the second current mirror. The drain and gate of the first PMOS transistor MP1 are connected together, and the drain and gate of the fourth PMOS transistor MP4 are connected together. The drain of the fifth PMOS transistor MP5 is the first mirror current port A1 of the first current mirror, and the drain of the sixth PMOS transistor MP6 is the second mirror current port A2 of the first current mirror.

In one example, the second current mirror is a cascode current mirror. In one example, the second current mirror includes first to fourth NMOS transistors. The gate of the first NMOS transistor MN1 is connected to the gate of the second NOMS transistor MN2. The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NOMS transistor. The drain of the first NMOS transistor MN1 is connected to the second end of the first resistor R6. The drain of the second NMOS transistor is connected to the second circuit node C2, that is, the drain of the second NMOS transistor is connected to the drain of the sixth PMOS transistor MP6. The source of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3, and the source of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4. The drain and gate of the first NMOS transistor MN1 are connected together, and the drain and gate of the third PMOS transistor MP3 are connected together. The source of the third NMOS transistor MN3 is grounded, and the source of the fourth NOMS transistor MN4 is grounded. The drain of the first NMOS transistor MN1 is the first mirror current port B1 of the second current mirror, and the drain of the second NMOS transistor MN2 is the second mirror current port B2 of the second current mirror.

The compensation current generating subcircuit 200 and the current mirroring subcircuit 300 in the above-mentioned embodiment can be applied to different bandgap reference subcircuits, the compensation current generating subcircuit 200 generates a compensation current with high-order temperature characteristics, and the current mirroring subcircuit 300 is The compensation current is mirrored to generate a mirror current, and the bandgap reference voltage is voltage compensated through the mirror current.

In the embodiment of the present disclosure, the bandgap reference circuit obtains the compensation current I5 with a high-order temperature coefficient, and makes the mirror current I0 of the compensation current I5 flow through the third resistor R5 to form a voltage with the same order to perform the bandgap reference voltage Higher order, more accurate temperature compensation.

In one example, as shown in FIG. 2 , the bandgap reference subcircuit 100 includes a second transistor Q1, a third transistor Q2, a second resistor R3, a third resistor R5, a fifth resistor R1, a sixth resistor R2, and operational amplifier Amp.

The two input terminals of the operational amplifier are IP and IN, and the output terminal is OUT. The output terminal OUT of the operational amplifier is the output terminal of the bandgap reference subcircuit 100 for outputting the bandgap reference voltage.

The resistance values of the fifth resistor R1 and the sixth resistor R2 are the same. The first terminal of the fifth resistor R1 is connected to the working voltage terminal of the bandgap reference subcircuit 100 , and the first terminal of the sixth resistor R2 is connected to the working voltage terminal of the bandgap reference subcircuit 100 . In this example, the first end of the fifth resistor R1 and the first end of the sixth resistor R2 are respectively connected to the emitter of the first transistor Q3, and the emitter of the first transistor Q3 is connected to the bandgap reference subcircuit 100 provides working voltage.

The second end of the fifth resistor R1 is connected to the collector of the second transistor Q1, and the second end of the sixth resistor R1 is connected to the collector of the third transistor Q2. The base of the second transistor Q1 is connected to the base of the third transistor Q2. The emitter of the third transistor Q2 is connected to the first end of the second resistor R3, and the emitter of the second transistor Q1 is connected to the second end of the second resistor R3. The second end of the second resistor R3 is connected to the first end of the third resistor R5, and the second end of the third resistor R5 is grounded.

The base-emitter voltage V _BE1 of the second transistor Q1 is different from the base-emitter voltage V _BE2 of the third transistor Q2. In an example, the second triode Q1 is realized by using a single triode device, and the third triode Q2 is formed by using multiple triode devices connected in parallel. In one example, the second transistor Q1 is an NPN transistor, and the third transistor Q2 is an NPN transistor.

The first input terminal IP of the operational amplifier AMP is connected to the collector of the second transistor Q1, and the second input terminal IN of the operational amplifier AMP is connected to the collector of the third transistor Q2. The output terminal OUT of the operational amplifier AMP is connected to the base of the second transistor Q1 to output the bandgap reference voltage.

In this example, the second circuit node C2 is connected to the bandgap reference sub-circuit 100 means that the second circuit node C2 is connected to the first end of the third resistor R5. The mirror current sub-circuit 300 converts the mirror current I0 into a compensation voltage with high-order temperature characteristics through the third resistor R5 to perform voltage compensation for the bandgap reference voltage.

The working principle of the bandgap reference circuit shown in Figure 2 is described below:

For the bandgap reference subcircuit 100 shown in FIG. 2, without setting the compensation current generation subcircuit 200 and the current mirror subcircuit 300, that is, without performing voltage compensation on the bandgap reference subcircuit 100:

The voltages of the first input terminal IP and the second input terminal IN of the operational amplifier Amp are approximately equal, and the resistance values of the fifth resistor R1 and the sixth resistor R2 are the same, so the current flowing through the second transistor Q1 is the same as the current flowing through the third transistor Q1 The currents of transistor Q2 are equal. The base-emitter voltage V _BE1 of the second transistor Q1 is different from the base-emitter voltage V BE2 _of the third transistor Q2, and the base-emitter voltage V _BE1 of the second transistor Q1 is different from that of the third transistor Q2. There is a voltage difference ΔV _BE between the base-emitter voltage V _BE2 of the triode Q2, and the voltage difference ΔV _BE is applied to the second resistor R3. Since the output terminal OUT of the operational amplifier AMP is connected to the base of the second transistor Q1, the output voltage of the operational amplifier AMP is equal to the base-emitter voltage V _BE1 of the second transistor Q1 plus the voltage of the third resistor R5 Voltage. The voltage on the third resistor R5 is ΔV _BE *R5/R3, and the final output voltage of the operational amplifier AMP is V _BE1 +ΔV _BE *R5/R3, that is, the bandgap reference voltage V _OUT output by the bandgap reference sub-circuit 100 is V _BE1 +ΔV _BE *R5/R3.

That is to say, in the case of no voltage compensation, the bandgap reference voltage V _OUT output by the bandgap reference subcircuit 100 is: V _OUT =V _BE1 +ΔV _BE *R5/R3. By adjusting the size of R5/R3, a bandgap reference voltage with approximately zero temperature coefficient can be obtained.

For the bandgap reference subcircuit 100 shown in FIG. 2 , when the compensation current generation subcircuit 200 and the current mirror subcircuit 300 are set to perform voltage compensation on it:

The first to sixth PMOS transistors MP1 - MP6 form a first current mirror of cascode, and the first to fourth NMOS transistors MN1 - MN4 form a second current mirror of common gate. The first PMOS transistor MP1 and the fourth PMOS transistor MP4 accurately copy the current of the second current source Idc to the branches of the second PMOS transistor MP2 and the fifth PMOS transistor MP5, and the branches of the third PMOS transistor MP3 and the sixth PMOS transistor MP6 road. Based on the working principle of the first current mirror, the current I1 flowing through the second PMOS transistor MP2 and the fifth PMOS transistor MP5 is equal to the current I2 flowing through the third PMOS transistor MP3 and the sixth PMOS transistor MP6. Based on the working principle of the second current mirror, the current I3 flowing through the first NOMS transistor MN1 and the third NOMS transistor MN3 is equal to the current I4 flowing through the second NOMS transistor MN2 and the fourth NOMS transistor MN4. The base of the first triode Q3 produces compensation current I5, because I1=I3+I5, I2=I4+I0, I1=I2, I3=I4, it can be seen that I0=I5, that is to say, the first triode The mirror image of the compensation current I5 output by the base of Q3 is the mirror current I0 in the embodiment of the present disclosure.

Due to the temperature characteristic of the base current of the first transistor Q3, the compensation current I5 is a current with a high-order temperature coefficient, so the voltage formed by the mirror current I0 flowing through the third resistor R5 is also a voltage with a high-order temperature coefficient. The voltage formed by the mirror current I0 flowing through the third resistor R5 is I0*R5, and this voltage is used to perform high-order temperature compensation for the bandgap reference voltage.

That is to say, in the case of voltage compensation, the bandgap reference voltage V _OUT output by the bandgap reference subcircuit 100 is: V _OUT =V _BE1 +ΔV _BE *R5/R3+I0*R5 . By adjusting the size of R5/R3 and I0*R5, a bandgap reference voltage with approximately zero temperature coefficient can be obtained.

In one example, referring to FIG. 3 , the bandgap reference subcircuit 100 includes a second transistor Q1, a third transistor Q2, a second resistor R3, a third resistor R5, a fourth resistor R4, a fifth resistor R1, the sixth resistor R2, and the operational amplifier Amp. In the embodiment shown in FIG. 3 , a fourth resistor R4 is connected in series between the second resistor R3 and the third resistor R5 . The emitter of the third transistor Q2 is connected to the first end of the second resistor R3, and the emitter of the second transistor Q1 is connected to the second end of the second resistor R3. The second end of the second resistor R3 is connected to the first end of the fourth resistor R5, the second end of the fourth resistor R5 is connected to the first end of the third resistor R5, and the second end of the third resistor R5 is grounded. Similar parts between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 2 will not be described repeatedly.

The working principle of the bandgap reference circuit shown in Figure 3 is described below:

For the bandgap reference subcircuit 100 shown in FIG. 3 , without setting the compensation current generation subcircuit 200 and the current mirror subcircuit 300, that is, without performing voltage compensation on the bandgap reference subcircuit 100:

There is a voltage difference ΔV _BE between the base-emitter voltage V _BE1 of the second transistor Q1 and the base-emitter voltage V _BE2 of the third transistor Q2, and the voltage difference ΔVBE is applied to the second resistor R3 superior. Since the output terminal OUT of the operational amplifier AMP is connected to the base of the second transistor Q1, the output voltage of the operational amplifier AMP is equal to the base-emitter voltage V _BE1 of the second transistor Q1 plus the voltage of the fourth resistor R4 , the voltage on the third resistor R5. The sum of the voltage of the fourth resistor R4 and the voltage of the third resistor R5 is ΔV _BE *(R4+R5)/R3, and the final output voltage of the operational amplifier AMP is V _BE1 +ΔV _BE *(R4+R5)/R3, That is, the bandgap reference voltage V _OUT output by the bandgap reference subcircuit 100 is V _BE1 +ΔV _BE *( R4 +R5 )/R3 .

That is to say, without voltage compensation, the bandgap reference voltage V _OUT output by the bandgap reference subcircuit 100 is: V _OUT =V _BE1 +ΔV _BE *( R4 +R5 )/R3 . By adjusting the size of (R4+R5)/R3, a bandgap reference voltage with approximately zero temperature coefficient can be obtained.

For the bandgap reference subcircuit 100 shown in Figure 3, in the case that the compensation current generation subcircuit 200 and the current mirror subcircuit 300 are set to perform voltage compensation: the bandgap reference voltage V _OUT of the bandgap reference subcircuit 100 output It is: V _OUT =V _BE1 +ΔV _BE *(R4+R5)/R3+I0*R5. By adjusting the size of (R4+R5)/R3 and I0*R5, a bandgap reference voltage with approximately zero temperature coefficient can be obtained.

In the example shown in Figure 3, the third resistor R5 and the fourth resistor R4 are provided. If you want to only adjust the result of ΔV _BE * (R4+R5)/R3, you can only adjust the resistance value of the fourth resistor R4, not Will affect the result of I0*R5. That is to say, by using the circuit shown in FIG. 3 , the bandgap reference voltage V _OUT output by the bandgap reference subcircuit 100 can be adjusted more conveniently and flexibly.

As shown in Figure 4, in the absence of voltage compensation, the bandgap reference subcircuit can partially offset the positive and negative temperature coefficients to form a symmetrical parabolic temperature-bandgap reference voltage curve, which reduces the temperature coefficient, the effect of improving the accuracy of the bandgap reference voltage. But because the two voltages with positive and negative temperature coefficients have different orders, the voltage difference ΔV _BE is a first-order function of temperature, and the function of base-emitter voltage V _BE1 to temperature contains high-order terms, so the positive The negative temperature coefficient is not completely offset compensation, but there are higher order components that cannot be offset compensated.

As shown in Figure 5, in the case of voltage compensation, the bandgap reference voltage output by the bandgap reference subcircuit is more gentle, and the amplitude of the bandgap reference voltage changes smaller under the same temperature change, so that the bandgap reference The voltage is more insensitive to changes in temperature, and the output of a high-precision bandgap reference voltage is realized.

Having described various embodiments of the present invention, the foregoing description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and alterations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principle of each embodiment, practical application or improvement of technology in the market, or to enable other ordinary skilled in the art to understand each embodiment disclosed herein. The scope of the invention is defined by the appended claims.

Claims (10)

1. A bandgap reference circuit, characterized in that, the bandgap reference circuit comprises a bandgap reference subcircuit, a compensation current generation subcircuit and a current mirror subcircuit; The current mirror subcircuit is respectively connected with the compensation current generation subcircuit and the bandgap reference subcircuit; The bandgap reference subcircuit is used to generate a bandgap reference voltage; The compensation current generating subcircuit is used to generate a compensation current (I5) with temperature characteristics; The current mirror sub-circuit is used to mirror the compensation current (I5) to generate a mirror current (I0), and perform voltage compensation to the bandgap reference voltage through the mirror current (I0). 2. The bandgap reference circuit according to claim 1, wherein the compensation current generating sub-circuit comprises a first triode (Q3); The collector of the first triode (Q3) is connected to the working voltage terminal (VCC) of the bandgap reference circuit; The emitter of the first triode (Q3) is connected to the bandgap reference subcircuit to provide an operating voltage to the bandgap reference subcircuit; The base of the first triode (Q3) generates the compensation current (I5). 3. The bandgap reference circuit according to claim 1, wherein the compensation current generating sub-circuit comprises a first triode (Q3); The collector of the first triode (Q3) is connected to the working voltage terminal (VCC) of the bandgap reference circuit; The emitter of the first triode (Q3) is connected to the first current source; The base of the first triode (Q3) generates the compensation current (I5). 4. The bandgap reference circuit according to any one of claims 1-3, wherein the current mirror subcircuit comprises a first current mirror, a second current mirror and a first resistor (R6); The first mirror current port (A1) of the first current mirror, the base of the first triode (Q3), and the first end of the first resistor (R6) are respectively connected to the first circuit node (C1); the second current The first mirror current port (B1) of the mirror is connected to the second end of the first resistor (R6); The second mirror current port (A2) of the first current mirror and the second mirror current port (B2) of the second current mirror are respectively connected to the second circuit node (C2); The current mirror subcircuit is connected to the bandgap reference subcircuit, including: the second circuit node (C2) is connected to the bandgap reference subcircuit. 5. The bandgap reference circuit according to claim 4, wherein the first current mirror is a cascode current mirror. 6. The bandgap reference circuit according to claim 5, wherein the first current mirror comprises first to sixth PMOS transistors; The gates of the first to third PMOS transistors are connected together, and the sources of the first to third PMOS transistors are respectively connected to the operating voltage terminal (VCC) of the bandgap reference circuit; The gates of the fourth to sixth PMOS transistors are connected together; The drain of the first PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the second PMOS transistor is connected to the source of the fifth PMOS transistor, and the drain of the third PMOS transistor is connected to the source of the sixth PMOS transistor. ; The drain of the fourth PMOS transistor is connected to the second current source (Idc), the drain of the fifth PMOS transistor is connected to the first circuit node (C1), and the drain of the sixth PMOS transistor is connected to the second circuit node (C2) ; The drain of the first PMOS transistor is connected to the gate, and the drain of the fourth PMOS transistor is connected to the gate; Wherein, the drain of the fifth PMOS transistor is the first mirror current port (A1) of the first current mirror, and the drain of the sixth PMOS transistor is the second mirror current port (A2) of the first current mirror. 7. The bandgap reference circuit according to claim 4, wherein the second current mirror comprises first to fourth NMOS transistors; The gate of the first NMOS transistor is connected to the gate of the second NOMS transistor; The gate of the third NMOS transistor is connected to the gate of the fourth NOMS transistor; The drain of the first NMOS transistor is connected to the second end of the first resistor (R6), and the drain of the second NMOS transistor is connected to the second circuit node (C2); The source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor; The drain of the first NMOS transistor is connected to the gate, and the drain of the third PMOS transistor is connected to the gate; The source of the third NMOS transistor and the source of the fourth NOMS transistor are respectively grounded; Wherein, the drain of the first NMOS transistor is the first mirror current port (B1) of the second current mirror, and the drain of the second NMOS transistor is the second mirror current port (B2) of the second current mirror. 8. The bandgap reference circuit according to any one of claims 4-7, characterized in that, the bandgap reference subcircuit comprises an operational amplifier (AMP), a second triode (Q1), a third triode Tube (Q2), second resistor (R3) and third resistor (R5); The first input of the operational amplifier (AMP) is connected to the collector of the second triode (Q1), and the second input is connected to the collector of the third triode (Q2); The base of the second transistor (Q1) is connected to the base of the third transistor (Q2), and the emitter of the third transistor (Q2) is connected to the first end of the second resistor (R3). The emitter of the bitransistor (Q1) is connected to the second end of the second resistor (R3); The second end of the second resistor (R3) is connected to the first end of the third resistor (R5), and the second end of the third resistor (R5) is grounded; The output terminal of the operational amplifier (AMP) is connected to the base of the third triode (Q2) to output the bandgap reference voltage; The second circuit node (C2) is connected to the bandgap reference subcircuit, comprising: the second circuit node (C2) is connected to a first end of a third resistor (R5). 9. The bandgap reference circuit according to any one of claims 4-7, characterized in that, the bandgap reference subcircuit comprises an operational amplifier (AMP), a second triode (Q1), a third triode Tube (Q2), second resistor (R3), third resistor (R5) and fourth resistor (R4); The first input of the operational amplifier (AMP) is connected to the collector of the second triode (Q1), and the second input is connected to the collector of the third triode (Q2); The base of the second transistor (Q1) is connected to the base of the third transistor (Q2), and the emitter of the third transistor (Q2) is connected to the first end of the second resistor (R3). The emitter of the bitransistor (Q1) is connected to the second end of the second resistor (R3); The second end of the second resistance (R3) is connected with the first end of the fourth resistance (R5), the second end of the fourth resistance (R5) is connected with the first end of the third resistance (R5), and the third resistance ( The second end of R5) is grounded; The output terminal of the operational amplifier (AMP) is connected to the base of the second triode (Q1) to output the bandgap reference voltage; The second circuit node (C2) is connected to the bandgap reference subcircuit, comprising: the second circuit node (C2) is connected to a first end of a third resistor (R5). 10. The bandgap reference circuit according to any one of claims 8-9, characterized in that, the first transistor (Q3) is an NPN transistor, and the second transistor (Q1) is an NPN type transistor, and the third transistor (Q2) is an NPN type transistor.

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