The document describes the design of several basic logic gates and arithmetic circuits using VHDL. It includes the definition of AND, OR, XOR gates and a half adder, full adder, multiplexer, ALU and 3-bit ALU. Each circuit is defined as a VHDL entity with inputs and outputs and an architecture that describes its functionality in terms of lower level components.
The document describes the design of several basic logic gates and arithmetic circuits using VHDL. It includes the definition of AND, OR, XOR gates and a half adder, full adder, multiplexer, ALU and 3-bit ALU. Each circuit is defined as a VHDL entity with inputs and outputs and an architecture that describes its functionality in terms of lower level components.
The document describes the design of several basic logic gates and arithmetic circuits using VHDL. It includes the definition of AND, OR, XOR gates and a half adder, full adder, multiplexer, ALU and 3-bit ALU. Each circuit is defined as a VHDL entity with inputs and outputs and an architecture that describes its functionality in terms of lower level components.
The document describes the design of several basic logic gates and arithmetic circuits using VHDL. It includes the definition of AND, OR, XOR gates and a half adder, full adder, multiplexer, ALU and 3-bit ALU. Each circuit is defined as a VHDL entity with inputs and outputs and an architecture that describes its functionality in terms of lower level components.
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
You are on page 1/ 6
COMPUERTA AND
library ieee; use ieee.std_logic_1164.all; entity GAND is port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end GAND; architecture BEH of GAND is begin X <= A AND B; end BEH;
COMPUERTA OR library ieee; use ieee.std_logic_1164.all; entity GOR is port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end GOR; architecture BEH of GXOR is begin X <= A OR B; end BEH;
COMPUERTA XOR library ieee; use ieee.std_logic_1164.all; entity GXOR is port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end GXOR; architecture BEH of GXOR is begin X <= A XOR B; end BEH;
MEDIO SUMADOR library ieee; use ieee.std_logic_1164.all; entity MEDS is port( A: in std_logic ; B: in std_logic ; S: out std_logic ; COUT: out std_logic ); end MEDS; architecture STRL of MEDS is component GAND port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component; component GXOR port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component; Begin U1:GXOR port map(A,B,S); U2:GAND port map(A,B,Cout); end Strl;
SUMADOR COMPLETO library ieee; use ieee.std_logic_1164.all; entity FULLS is port( A: in std_logic ; B,CIN: in std_logic ; S: out std_logic ; COUT: out std_logic ); end FULLS; architecture STRL of FULLS is component GOR port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component; component MEDS port( A: in std_logic ; B: in std_logic ; S: out std_logic ; COUT: out std_logic ); end component; Signal N,P,O: std_logic; Begin U1: MEDS port map(A,B,N,P); U2: MEDS port map(N,CIN,S,O); U3: GOR port map(P,O,X); end Strl; COMPUERTA NOT A library ieee; use ieee.std_logic_1164.all; entity GNA is port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end GNA; architecture BEH of GNA is begin X <= NOT B;
end BEH;
COMPUERTA NOT B library ieee; use ieee.std_logic_1164.all; entity GNB is port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end GNB; architecture BEH of GNB is begin X <= NOT B; end BEH; MULTIPLEXOR library ieee; use ieee.std_logic_1164.all; entity MUX4 is port( c: in std_logic_vector( 3 dowto 0); s: in std_logic_vector( 1 dowto 0); z: in std_logic); end mux4; architecture BEH of mux4 is begin process(s,c) begin case s is when 00 => z <= C(0); when 01 => z <= C(1); when 10 => z <= C(2); when 11 => z <= C(3); when others => z <= C(0); end case; end process; end BEH;
ALU library ieee; use ieee.std_logic_1164.all; entity ALU is port( A,B,C: in std_logic; S: in std_logic_vector( 1 dowto 0); X,COUT: OUT std_logic); end ALU; architecture STRL of ALU is
component GXOR port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component; component FULLS port( A: in std_logic ; B: in std_logic ; S: out std_logic ; COUT: out std_logic ); end component; component GNA port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component; component GNB port( A: in std_logic ; B: in std_logic ; X: out std_logic ); end component;
component MUX4 is
port( c: in std_logic_vector( 3 dowto 0);
s: in std_logic_vector( 1 dowto 0); z: in std_logic); end component;
Signal P: std_logic_vector (3dowto0);
Begin U1: GXOR port map(A,B,p(0)); U2: FULLS port map(A,B,C,p(1),COUT); U3: GNA port map(A,B, p(2),); U4: GNB port map(A,B, p(3)); U5: MUX4 port map(P,S,X); end Strl; library ieee; use ieee.std_logic_1164.all; entity ALU3 is port( A,B: std_logic_vector ( 2 dowto 0); S: in std_logic_vector( 1 dowto 0); CIN: in std_logic; X: OUT std_logic_vector( 1 dowto 0); COUT: STD_LOGIC; end ALU3; architecture STRL of ALU3 is COMPONENT ALU port( A,B,C: in std_logic; S: in std_logic_vector( 1 dowto 0); X,COUT: OUT std_logic); end COMPONENT; SIGNAL P: STD_LOGIC_VECTOR(2 DOWTO 0); UO: ALU-LOGIC PORT MAP (A(0), B(0),CIN, S,X(0),P(O)); UO: ALU-LOGIC PORT MAP (A(1), B(1), P(O), S,X(1),P(1)); UO: ALU-LOGIC PORT MAP (A(2), B(1), P(1), S,X(2),P(2)); END STRL;
