1.

VHDL Code for 4 to 2 Encoder

case statement

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity encoder is

port(

a : in STD_LOGIC_VECTOR(3 downto 0);

b : out STD_LOGIC_VECTOR(1 downto 0)

);

end encoder;

architecture bhv of encoder is

begin

process(a)

begin

case a is

when "1000" => b <= "00";

when "0100" => b <= "01";

when "0010" => b <= "10";

when "0001" => b <= "11";

when others => b <= "ZZ"; end case; end process; end bhv;
Usin if else statement

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder1 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder1;

architecture bhv of encoder1 is

begin

process(a)
begin
if (a="1000") then
b <= "00";
elsif (a="0100") then
b <= "01";
elsif (a="0010") then
b <= "10";
elsif (a="0001") then
b <= "11";
else
b <= "ZZ";
end if;
end process;

end bhv;

Using Logic Gates

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity encoder2 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder2;

architecture bhv of encoder2 is

begin

b(0) <= a(1) or a(2);

b(1) <= a(1) or a(3);

end bhv;

VHDL Code for 2 to 4 decoder

Usign case statement

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture bhv of decoder is
begin

process(a)
begin
case a is
when "00" => b <= "0001";
when "01" => b <= "0010";
when "10" => b <= "0100";
when "11" => b <= "1000";
end case;
end process;

end bhv;

Using if else statment

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder1;

architecture bhv of decoder1 is

begin

process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;

end bhv;
Using Logic gates

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder2 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder2;

architecture bhv of decoder2 is

begin

b(0) <= not a(0) and not a(1);

b(1) <= not a(0) and a(1);
b(2) <= a(0) and not a(1);
b(3) <= a(0) and a(1);

end bhv;

VHDL Code for logic gates

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
---------------------------------- Entity Declarations -------------------------
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end andgate;

architecture Behavioral of andgate is

begin
Y= A and B ;
end Behavioral;
OR Gate

architecture Behavioral of orgate is

begin
Y= A or B ;
end Behavioral;

NOT Gate

architecture Behavioral of notgate is

begin
Y= not A ;
end Behavioral;

NAND Gate

architecture Behavioral of nandgate is

begin

Y= A nand B ;

end Behavioral;

NOR Gate

architecture Behavioral of norgate is

begin
Y= A nor B ;
end Behavioral;

XOR Gate

architecture Behavioral of xorgate is

begin
Y= A xor B ;
end Behavioral;

XNOR Gate

architecture Behavioral of xnorgate is

begin
Y= A xnor B ;
end Behavioral;
VHDL 4 to 1 Mux (Multiplexer)

Multiplexer (MUX) select one input from the multiple inputs and forwarded to
output line through selection line. It consists of 2 power n input and 1 output. The
input data lines are controlled by n selection lines.

For Example, if n = 2 then the mux will be of 4 to 1 mux with 4 input, 2 selection
line and 1 output as shown below.

Truth Table for Multiplexer 4 to 1

Mux 4 to 1 design using Logic Gates

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is

port(

A,B,C,D : in STD_LOGIC;

S0,S1: in STD_LOGIC;

Z: out STD_LOGIC

);

end mux_4to1;

architecture bhv of mux_4to1 is

begin

process (A,B,C,D,S0,S1) is

begin

if (S0 ='0' and S1 = '0') then

Z <= A;

elsif (S0 ='1' and S1 = '0') then

Z <= B;

elsif (S0 ='0' and S1 = '1') then

Z <= C;

else

Z <= D;

end if;

end process;

end bhv;
VHDL TestBench Code for 4 to 1 Multiplexer

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS

END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux_4to1

PORT(

A : IN std_logic;

B : IN std_logic;

C : IN std_logic;

D : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

Z : OUT std_logic

);

END COMPONENT;

--Inputs

signal A : std_logic := '0';

signal B : std_logic := '0';

signal C : std_logic := '0';

signal D : std_logic := '0';

signal S0 : std_logic := '0';

signal S1 : std_logic := '0';

 --Outputs

signal Z : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux_4to1 PORT MAP (

A => A,

B => B,

C => C,

D => D,

S0 => S0,

S1 => S1,

Z => Z

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

A <= '1';

B <= '0';

C <= '1';

D <= '0';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

 S0 <= '0'; S1 <= '1';

wait for 100 ns;

end process;

END;

4 to 1 Mux Implementation using 2 to 1 Mux

Another Method of Constructing VHDL 4 to 1 mux is by using 2 to 1 Mux. For that

implementation first we have write VHDL Code for 2 to 1 Mux and Port map 3 times
2 to 1 mux to construct VHDL 4 to 1 Mux.

VHDL Code for 2 to 1 Mux

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux2_1 is

port(A,B : in STD_LOGIC;

S: in STD_LOGIC;

Z: out STD_LOGIC);

end mux2_1;

architecture Behavioral of mux2_1 is

begin

process (A,B,S) is

begin

if (S ='0') then
 Z <= A;

else

Z <= B;

end if;

end process;

end Behavioral;

VHDL 4 to 1 Mux using 2 to 1 Mux

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is

port( A,B,C,D : in STD_LOGIC; S0,S1: in STD_LOGIC; Z: out STD_LOGIC );

end mux4_1;

architecture Behavioral of mux4_1 is

component mux2_1

port( A,B : in STD_LOGIC;

S: in STD_LOGIC;

Z: out STD_LOGIC);

end component;

signal temp1, temp2: std_logic;

begin

m1: mux2_1 port map(A,B,S0,temp1);

m2: mux2_1 port map(C,D,S0,temp2);

m3: mux2_1 port map(temp1,temp2,S1,Z);

end Behavioral;

VHDL Testbench and Simulation Waveform for 4 to 1 mux using 2 to 1 mux is

same as the above implementation.
VHDL code for 1 to 4 Demux

Demultiplexer (DEMUX) select one output from the multiple output line and fetch
the single input through selection line. It consist of 1 input and 2 power n output.
The output data lines are controlled by n selection lines. For Example, if n = 2 then
the demux will be of 1 to 4 mux with 1 input, 2 selection line and 4 output as
shown below. Also VHDL Code for 1 to 4 Demux described below.

Truth table for Demux 1 to 4

1 to 4 Demux design using Logic Gates

VHDL Code for 1 to 4 Demux

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity demux_1to4 is

port(

F : in STD_LOGIC;

S0,S1: in STD_LOGIC;

A,B,C,D: out STD_LOGIC

);

end demux_1to4;

architecture bhv of demux_1to4 is

begin

process (F,S0,S1) is

begin

if (S0 ='0' and S1 = '0') then

A <= F;

elsif (S0 ='1' and S1 = '0') then

B <= F;

elsif (S0 ='0' and S1 = '1') then

C <= F;

else

D <= F;

end if;

end process;

end bhv;
VHDL Testbench Code for 1 to 4 Demux

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_demux IS

END tb_demux;

ARCHITECTURE behavior OF tb_demux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT demux_1to4

PORT(

F : IN std_logic;

S0 : IN std_logic;

S1 : IN std_logic;

A : OUT std_logic;

B : OUT std_logic;

C : OUT std_logic;

D : OUT std_logic

);

END COMPONENT;

--Inputs

signal F : std_logic := '0';

signal S0 : std_logic := '0';

signal S1 : std_logic := '0';

--Outputs

signal A : std_logic;

signal B : std_logic;

signal C : std_logic;

signal D : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: demux_1to4 PORT MAP (

F => F,

S0 => S0,

S1 => S1,

A => A,

B => B,

C => C,

D => D

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

wait for 100 ns;

F <= '1';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

S0 <= '1'; S1 <= '1';

wait for 100 ns;

-- insert stimulus here

wait; end process; END;

BCD Adder

-- This is the FULL ADDER

library ieee;
use ieee.std_logic_1164.all;
--
entity Full_Adder is
port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end Full_Adder;
--Dataflow architecture. See Full Adder on Teahlab.com
--for structural version
architecture func of Full_Adder is
begin
sum <= (X xor Y) xor Cin;
Cout <= (X and (Y or Cin)) or (Cin and Y);
end func;

--*============================
-- This is the AND gate
library ieee;
use ieee.std_logic_1164.all;
--
entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;
--
architecture func of andGate is
begin
F <= A and B;
end func;
--*============================

-- This is the OR gate

library ieee;
use ieee.std_logic_1164.all;
--
entity orGate is
port( A, B, C : in std_logic;
F : out std_logic);
end orGate;
--
architecture func of orGate is
begin
F <= A or B or C;
end func;
--*============================
-- This is the XOR gate
library ieee;
use ieee.std_logic_1164.all;
--
entity xorGate is
port( A, B : in std_logic;
F : out std_logic);
end xorGate;
--
architecture func of xorGate is
begin
F <= A xor B;
end func;
--*=====================*=================

--Now we build the four bit BCD_Adder

library ieee;
use ieee.std_logic_1164.all;
--
entity BCD_Adder is
port( X3, X2, X1, X0 : in std_logic;
Y3, Y2, Y1, Y0 : in std_logic;
S3, S2, S1, S0, Cout : out std_logic);
end BCD_Adder;
--Structural architecture
architecture struct of BCD_Adder is

component Full_Adder is --FULL ADDER component

port( X, Y, Cin : in std_logic;
sum, Cout : out std_logic);
end component;

component andGate is --AND component

port( A, B : in std_logic;
F : out std_logic);
end component;

component orGate is --OR component

 port( A, B, C : in std_logic;
F : out std_logic);
end component;

component xorGate is --XOR component

port( A, B : in std_logic;
F : out std_logic);
end component;

--REMINDER: WE ARE CONSTRUCTING THE CIRCUIT EXACTLY AS IT

--APPEARS ON TEAHLAB.COM. So use the interactive circuit
--to follow along.

--interconnecting wires
signal C1, C2, C3, C4, C5, C6: std_logic;--full adder carry
signal FA1, FA2, FA3 : std_logic;--inner full adder sums
signal andOut1, andOut2, orOut : std_logic;

begin

G_FA0: Full_Adder port map(X0, Y0, '0', S0, C1); -- S0

G_FA1: Full_Adder port map(X1, Y1, C1, FA1, C2);
G_FA2: Full_Adder port map(X2, Y2, C2, FA2, C3);
G_FA3: Full_Adder port map(X3, Y3, C3, FA3, C4);
G_A1: andGate port map(FA1, FA3, andOut1);
G_A2: andGate port map(FA2, FA3, andOut2);
G_O: orGate port map(andOut2, andOut1, C4, orOut);
G_FA4: Full_Adder port map(FA1, orOut, '0', S1, C5);-- S1
G_FA5: Full_Adder port map(FA2, orOut, C5, S2, C6); -- S2
G_X : xorGate port map(C6, FA3, S3); -- S3
Cout <= orOut; -- Cout

end struct;

4 Bit Adder using Structural Modeling Style.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
carry : out STD_LOGIC;
sum : out STD_LOGIC_VECTOR(3 downto 0)
);
end adder_4bit;
architecture adder_4bit_arc of adder_4bit is

Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end component;

signal s : std_logic_vector (2 downto 0);

begin

u0 : fa port map (a(0),b(0),'0',sum(0),s(0));

u1 : fa port map (a(1),b(1),s(0),sum(1),s(1));
u2 : fa port map (a(2),b(2),s(1),sum(2),s(2));
ue : fa port map (a(3),b(3),s(2),sum(3),carry);

end adder_4bit_arc;

---------------- Full Adder Design ----------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end fa;

architecture fa_arc of fa is
begin

sum <= a xor b xor c;

carry <= (a and b) or (b and c) or (c and a);

end fa_arc;
VHDL code for 4-bit binary comparator

Binary comparator compare two 4-bit binary number. It is also known as

magnitude comparator and digital comparator. Analog form comparator is voltage
comparator. The functionality of this comparator circuit is, It consist of 3 outputs
Greater, Equal and Smaller. If inp-A is greater then inp-B then greater output is
high, if both inp-A and inp-B are same then equal output is high, else smaller
output is high.

VHDL Code 4-bit Binary comparator

VHDL Code for 4-bit Binary Comparator

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity VHDL_Binary_Comparator is
port (
inp-A,inp-B : in std_logic_vector(3 downto 0);
greater, equal, smaller : out std_logic
);
end VHDL_Binary_Comparator ;

architecture bhv of VHDL_Binary_Comparator is

begin
greater <= '1' when (inp-A > inp-B)
else '0';
equal <= '1' when (inp-A = inp-B)
else '0';
smaller <= '1' when (inp-A < inp-B)
else '0';
end bhv;
VHDL code for 4-bit ALU

ALU’s comprise the combinational logic that implements logic operations such as
AND, OR, NOT gate and arithmetic operations, such as Adder, Subtractor.

Functionally, the operation of typical ALU is represented as shown in diagram

below,

Functional Description of 4-bit Arithmetic Logic Unit

Controlled by the three function select inputs (sel 2 to 0), ALU can perform all the
8 possible logic operations

VHDL Code for 4-bit ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity alu is
Port ( inp_a : in signed(3 downto 0);
inp_b : in signed(3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end alu;

architecture Behavioral of alu is

begin
process(inp_a, inp_b, sel)
begin
case sel is
when "000" =>
out_alu<= inp_a + inp_b; --addition
when "001" =>
out_alu<= inp_a - inp_b; --subtraction
 when "010" =>
out_alu<= inp_a - 1; --sub 1
when "011" =>
out_alu<= inp_a + 1; --add 1
when "100" =>
out_alu<= inp_a and inp_b; --AND gate
when "101" =>
out_alu<= inp_a or inp_b; --OR gate
when "110" =>
out_alu<= not inp_a ; --NOT gate
when "111" =>
out_alu<= inp_a xor inp_b; --XOR gate
when others =>
NULL;
end case;

end process;

end Behavioral;

VHDL CODE FOR SEQUENTIAL CIRCUITS

VHDL Code for an SR Latch

library ieee;
use ieee.std_logic_1164.all;
entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;
architecture virat of srl is
signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end virat;

Waveforms
VHDL Code for a D Latch

library ieee;
use ieee.std_logic_1164.all;
entity Dl is
port(d:in bit; q,qbar:buffer bit);
end Dl;
architecture virat of Dl is
signal s1,r1:bit;
begin
q<= d nand qbar;
qbar<= d nand q;
end virat;

Waveforms
VHDL Code for an SR Flip Flop

library ieee;
use ieee.std_logic_1164.all;
entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;
architecture virat of srflip is
signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;
VHDL code for a JK Flip Flop

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity jk is
port(
j : in STD_LOGIC;
k : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC;
qb : out STD_LOGIC
 );
end jk;
architecture virat of jk is
begin
jkff : process (j,k,clk,reset) is
variable m : std_logic := '0';
begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (j/ = k) then
m : = j;
elsif (j = '1' and k = '1') then
m : = not m;
end if;
end if;
q <= m;
qb <= not m;
end process jkff;
end virat;
VHDL Code for a D Flip Flop

Library ieee;
use ieee.std_logic_1164.all;
entity dflip is
port(d,clk:in bit; q,qbar:buffer bit);
end dflip;
architecture virat of dflip is
signal d1,d2:bit;
begin
d1<=d nand clk;
d2<=(not d) nand clk;
 q<= d1 nand qbar;
qbar<= d2 nand q;
end virat;

VHDL Code for a T Flip Flop

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Toggle_flip_flop is
port(
t : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end Toggle_flip_flop;
architecture virat of Toggle_flip_flop is
begin
tff : process (t,clk,reset) is
variable m : std_logic : = '0';

begin
if (reset = '1') then
m : = '0';
elsif (rising_edge (clk)) then
if (t = '1') then
m : = not m;
end if;
end if;
dout < = m;
end process tff;
end virat;

VHDL Code for a 4 - bit Up Counter

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end counter;
architecture virat of counter is
 signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp < = "0000";
elsif (Clock'event and Clock = '1') then
mp <= tmp + 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms

VHDL Code for a 4-bit Down Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
 port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end dcounter;
architecture virat of dcounter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)
begin
if (CLR = '1') then
tmp <= "1111";
elsif (Clock'event and Clock = '1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end virat;

Waveforms

Synchronous Reset :

A synchronous reset signal can be applied as shown below :

process(clk)
begin
if(rising_edge(clk)) then
if(reset = '0') then --reset is checked only at the rising edge of clock.
o <= i;
else
o <= '0';
end if;
end if;
end process;

The code is synthesised to the following block in FPGA: (truth table of FDR flip flop
is also given)
In the schematic diagram FDR is a single D-type flip-flop with data (D) and
synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input,
when High, overrides all other inputs and resets the Q output Low on the 0 to 1
clock (C) transition. The data on the D input is loaded into the flip-flop when R is
Low during the 0 to1 clock transition.If you analyze the above code you can see
that the value of reset changes the signal 'o' only at the rising edge of the clock.This
method has the following advantages:

1)The reset applied to all the flip-flops are fully synchronized with clock and
always meet the reset recovery time.
2)In some cases, synchronous reset will synthesis to smaller flip-flops.

Synchronous resets have some disadvantages also:

1)If the reset applied is for a small duration then the clock edge may not be able
to capture the reset signal.Thus if you are synchronous resets make sure that
your reset signal stays active for enough time so that it get captured by the clock.
2)Also the change in reset doesn't immediately reflect in the associated signals.

Asynchronous reset:

Now let us have a look at the asynchronous reset :

process(clk,reset)
begin
if(reset = '0') then --change in reset get immediately reflected on signal 'o'.
if(rising_edge(clk)) then
o <= i;
end if;
else
o <= '0';
end if;
end process;

The code is synthesised to the following in FPGA. (the truth table of the
particular flip-flop is also given)

In the schematic FDC is a single D-type flip-flop with data (D) and asynchronous
clear (CLR) inputs and data output (Q). The asynchronous CLR, when High,
overrides all other inputs and sets the Q output Low. The data on the D input is
loaded into the flip-flop when CLR is Low on the 0 to 1 clock transition.If you
analyse the code you can see that when the reset goes high , immediately signal 'o'
will become '0'.It doesn't wait for clock change. Now let us look at
the advantages of this method:

1)High speed can be achieved.

2)Data can be reset without waiting for the clock edge.

The disadvantages are:

1) Asynchronous resets have metastability problems. By metastability what I

mean is that,the clock and reset have no relationship.So if the reset changes from
1 to 0 at the rising edge of the clock, the output is not determinate. The reset input
has to follow the reset recovery time rule.This time is a kind of setup
time condition on a flip-flop that defines the minimum amount of time between the
change in reset signal and the next rising clock edge.If the signal doesn't follow this
set up time then it may create metastability problems.

Note :- As you can see both the methods have their own advantages and
disadvantages.And selecting one of the method depends upon your design
requirement.