LAB #1

Introduction to Basic Logic Gate ICs on

Digital Logic Trainer and Proteus
Simulation
AND Gate:
The AND gate is an electronic circuit that gives a high output (1)
only if all its inputs are high. A dot (.) is used to show the AND
operation i.e. A.B. Bear in mind that this dot is sometimes omitted
i.e. AB.

OR Gate:
The OR gate is an electronic circuit that gives a high output (1) if
one or more of its inputs are high. A plus (+) is used to show the
OR operation.
NOT Gate:
The NOT gate is an electronic circuit that produces an inverted
version of the input at its output. It is also known as an inverter.

NAND Gate:
This is a NOT-AND gate which is equal to an AND gate followed
by a NOT gate. The output of NAND gate is high if any of the
inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion.

NOR Gate:
This is a NOT-OR gate which is equal to an OR gate followed by a
NOT gate. The output of NOR gate is low if any of the inputs are
high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion.

XOR Gate:
The 'Exclusive-OR' gate is a circuit which will give a high output if
odd number of inputs are high. An encircled plus sign “ ” is used to
show the EOR operation.

XNOR Gate:
The XNOR gate is a digital logic gate whose function is the logical
complement of the Exclusive OR (XOR) gate.

In lab Task 1:
 Observation Table for different Gates
INPUT OUTPUT

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1
0 1 0 1 1 1 0 0
1 0 0 1 1 1 0 0
1 1 1 1 0 0 0 1

Observation Table for NOT Gate

INPUT OUTPUT
A B
0 1
1 0
Post Lab Task:
1.Make a list of logic gates ICs of TTL family
&CMOS family along with the ICs names.

7400 Series 4000 Series

1 7402 4001
2 7403 4011
3 7408 4030
 4 7409 4071
5 7432 4072
6 7486 4012
7 7404 4002
8 7427 4075
9 7420 4073
10 7421 4071
11 7412 4093
12 7411 4081
13 7410 4023
14 7405 4025
15 7412 4077

2.What is Fan-In and Fan-Out?

Ans:
Fan-In: Fan-in is the number of inputs a logic gate can handle.
Physical logic gates with a large fan-in tend to be slower than those
with a small fan-in. This is because the complexity of the input
circuitry increases the input capacitance of the device. Using logic
gates with higher fan-in will help reducing the depth of a logic
circuit.
For instance the fan-in for the AND gate shown in the figure.
Fan-Out: In digital electronics, the fan-out is the number of gate
inputs driven by the output of another single logic gate. The
maximum fan-out of an output measures its load-driving capability:
it is the greatest number of inputs of gates of the same type to
which the output can be safely connected.
Critical Analysis:
In this lab I am able to know about the basic logic gates, their truth
tables. Introduction to logic gate ICs, ICs pin configurations and
their uses. I am also able to use Proteus Software for simulation of
Digital Logic Circuit.

Lab #2

NOT FROM NAND

NOT FROM NOR

AN
D FROM NAND
 AN
D FROM NOR

OR
FROM NOR
 POST LAB

NOR TO NAND
 NOR TO XOR

Critical Analysis:
After performing this lab I have learnt how that these gates can be further used for
the making of logic gates.with the help of this lab I will be able to differentiate
between different gates like XOR and etc. I am also able how to construct their logic
function using nor gate and NAND.

Lab # 3:
 Introduction to Verilog using Xilinx ISE
Apparatus:
Xilinx
FPGA

Concept:
Verilog is a hardware description language used to write code to describe circuits and
gates. Its scope is from most simple circuits like AND gates to very complex output
circuits with thousands of inputs.
Xilinx is an IDE which gives us programming environment to code in Verilog and test
our code.
It provides drivers and connections to put our circuit on FPGA and test it too.

Part 1: Basic Gates outputs using verilog

Procedure:
 Create new project.
 Create a module and specify inputs and outputs.
 Implement all basic gates and give their output.

Verilog code:
module BasicFuncs(a,b,NOTa,AND,OR,NOR,NAND,XOR,XNOR
);
input a,b;
output NOTa,AND,OR,NOR,NAND,XOR,XNOR;
assign NOTa = ~a;
assign AND = a && b;
assign OR = a || b;
assign NOR = ~(a || b);
assign NAND = ~(a && b);
assign XOR = a^b;
assign XNOR = ~(a^b);
endmodule

TEST BENCH:

module FuncTest;

// Inputs
reg a;
reg b;

// Outputs
wire NOTa;
wire AND;
wire OR;
wire NOR;
wire NAND;
wire XOR;
wire XNOR;

// Instantiate the Unit Under Test (UUT)

BasicFuncs uut (
.a(a),
.b(b),
.NOTa(NOTa),
.AND(AND),
.OR(OR),
.NOR(NOR),
.NAND(NAND),
.XOR(XOR),
.XNOR(XNOR)
);
 initial begin
a = 0;
b = 0;
#100;
a = 0;
b = 1;
#100;
a = 1;
b = 0;
#100;
a = 1;
b = 1;
#100;

end

endmodule

BEHAVIOUR TEST:
 Part 2: Implement Boolean expression using Xilinx:

PROCEDURE:
 Create project in Xilinx.
 Specify inputs and outputs in main module.
 Implement the Boolean expression using gates.
 Give final output as output function variable
 Create test file.
 Test wave form.

module FuncDataFlow(x,y,z,F);
iSnput x,y,z;
output F;
assign F = x | (y&(~x)) | (y&(~z))
endmodule

module FuncGateLevel(x,y,z,F);
input x,y,z;
 output F;
wire not_x,not_z,f1,f2,f3;
not n1(not_x,x);
not n2(not_z,z);
and a1(f1,not_x,y);
and a2(f2,y,not_z);
or o1(f3,f1,f2);
or o2(F,f3,x);

endmodule

Test Bench: Part 2: Implement Boolean expression using Xilinx

module DataFlowTest;

// Inputs
reg x;
reg y;
reg z;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)

FuncDataFlow uut (
.x(x),
.y(y),
.z(z),
.F(F)
);

initial begin
x = 0;
y = 0;
z = 0;
#100;
x = 0;
y = 0;
z = 1;
#100;
x = 0;
y = 1;
z = 0;
#100;
x = 0;
y = 1;
z = 1;
#100;
x = 1;
y = 0;
z = 0;
#100;
x = 1;
y = 0;
z = 1;
#100;
x = 1;
y = 1;
 z = 0;
#100;
x = 1;
y = 1;
z = 1;
#100;

end

endmodule

Behavior Test:

CriticalAnalysis/Conclusion:
In this lab we learned the digital circuit or gate designinng, How to use XILINX
ISE software and how to create a project on it. We are able stimulate the
different gates.We heve learned how to design and verify the digital circuits.
Now we can easily compere the Gate Level, Data Flow Level, Function and The
Truth Table of the Function and verify results by comparing.

LAB #04
Design and Implementation of Boolean
Functions by Standard Forms using
ICs/Verilog

𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 �
�
̅
0 0 0 𝑚0 = 𝑥 ′ 𝑦 ′ 𝑧 ′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 1

0 0 1 𝑚1 = 𝑥 ′ 𝑦 ′ 𝑧 𝑀 1 = 𝑥 + 𝑦 + 𝑧′ 1 0
𝑚2 = 𝑥 ′𝑦𝑧 ′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
0 1 0 0 1

0 1 1 𝑚3 = 𝑥 ′ 𝑦𝑧 𝑀3 = 𝑥 + 𝑦 ′ + 𝑧 ′ 1 0
𝑚4 = 𝑥𝑦 ′ 𝑧 ′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧
1 0 0 1 0
𝑚5 = 𝑥𝑦 ′ 𝑧 𝑀5 = 𝑥 ′ + 𝑦 + 𝑧 ′
1 0 1 0 1
 𝑚6 = 𝑥𝑦𝑧 ′ 𝑀6 = 𝑥′+𝑦′ + 𝑧
1 1 0 0 1
𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥 ′ + 𝑦 ′ + 𝑧 ′
1 1 1 0 1

Pre-Lab Tasks:

QNO1:

Express the Boolean function 𝐹 = 𝑥 + 𝑦𝑧 as a sum of minterms by using truth table.

Answer:

𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 𝑥
+
𝑦z
0 0 0 𝑚0 = 𝑥 ′ 𝑦 ′ 𝑧 ′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 0

0 0 1 𝑚1 = 𝑥 ′ 𝑦 ′ 𝑧 𝑀 1 = 𝑥 + 𝑦 + 𝑧′ 1 0
𝑚2 = 𝑥 ′𝑦𝑧 ′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
0 1 0 0 0

0 1 1 𝑚3 = 𝑥 ′ 𝑦𝑧 𝑀3 = 𝑥 + 𝑦 ′ + 𝑧 ′ 1 1
𝑚4 = 𝑥𝑦 ′ 𝑧 ′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧
1 0 0 1 1
𝑚5 = 𝑥𝑦 ′ 𝑧 𝑀5 = 𝑥 ′ + 𝑦 + 𝑧 ′
1 0 1 0 1
𝑚6 = 𝑥𝑦𝑧 ′ 𝑀6 = 𝑥′+𝑦′ + 𝑧
1 1 0 0 1
𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥 ′ + 𝑦 ′ + 𝑧 ′
1 1 1 0 1

Sum of minterms:

F = ∑ (3, 4, 5, 6, 7)
F = A’BC + AB’C’ + AB’C + ABC’ + ABC

QNO2:

Express 𝐹′ = (𝑥 + 𝑦𝑧)′ as a product of maxterms.

Answer:

𝐹′
𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 (
= 𝑥+

𝑦𝑧) ′
0 0 0 𝑚0 = 𝑥 ′ 𝑦 ′ 𝑧 ′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 1

0 0 1 𝑚1 = 𝑥 ′ 𝑦 ′ 𝑧 𝑀 1 = 𝑥 + 𝑦 + 𝑧′ 1 1
𝑚2 = 𝑥 ′𝑦𝑧 ′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
0 1 0 0 1

0 1 1 𝑚3 = 𝑥 ′ 𝑦𝑧 𝑀3 = 𝑥 + 𝑦 ′ + 𝑧 ′ 1 0
𝑚4 = 𝑥𝑦 ′ 𝑧 ′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧
1 0 0 1 0
𝑚5 = 𝑥𝑦 ′ 𝑧 𝑀5 = 𝑥 ′ + 𝑦 + 𝑧 ′
1 0 1 0 0
𝑚6 = 𝑥𝑦𝑧 ′ 𝑀6 = 𝑥′+𝑦′ + 𝑧
1 1 0 0 0
𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥 ′ + 𝑦 ′ + 𝑧 ′
1 1 1 0 0

Product of maxterms:

F = π (3,4,5,6,7)
F = (x’+y+z)(x’+y+z’)(x’+y’+z)(x’+y’+z’)(x+y’+z’)
QNO3:

Given the function as defined in the truth table (Table), express 𝐹 using sum of
minterms and product of maxterms.
Answer:

𝒙 𝒚 𝒛 𝑴𝒊𝒏𝒕𝒆𝒓𝒎𝒔 𝑴𝒂𝒙𝒕𝒆𝒓𝒎𝒔 𝑭 �
�
̅
0 0 0 𝑚0 = 𝑥 ′ 𝑦 ′ 𝑧 ′ 𝑀0 = 𝑥 + 𝑦 + 𝑧 0 1

0 0 1 𝑚1 = 𝑥 ′ 𝑦 ′ 𝑧 𝑀 1 = 𝑥 + 𝑦 + 𝑧′ 1 0
𝑚2 = 𝑥 ′𝑦𝑧 ′ 𝑀2 = 𝑥 + 𝑦′ + 𝑧
0 1 0 0 1

0 1 1 𝑚3 = 𝑥 ′ 𝑦𝑧 𝑀3 = 𝑥 + 𝑦 ′ + 𝑧 ′ 1 0
𝑚4 = 𝑥𝑦 ′ 𝑧 ′ 𝑀4 = 𝑥′ + 𝑦 + 𝑧
1 0 0 1 0
𝑚5 = 𝑥𝑦 ′ 𝑧 𝑀5 = 𝑥 ′ + 𝑦 + 𝑧 ′
1 0 1 0 1
𝑚6 = 𝑥𝑦𝑧 ′ 𝑀6 = 𝑥′+𝑦′ + 𝑧
1 1 0 0 1
𝑚7 = 𝑥𝑦𝑧 𝑀7 = 𝑥 ′ + 𝑦 ′ + 𝑧 ′
1 1 1 0 1

Sum of minterms:
F= ∑ (1,3,4)
F=x’y’z+x’yz+xy’z’

Product of maxterms using f:

F= π (0,2,5,6,7)
F=(x+y+z)(x+y’+z)(x’+y+z’)(x’+y’+z)(x’+y’+z’)
In-Lab Tasks:

Circuit Implementation
1. First, make the circuit diagram of the given Task.
2. Select appropriate logic gate ICs which are needed.
3. Make connections according to the circuit diagram you made.
4. Connect the input to data switches and output to the logic indicator.
5. Follow the input sequence and record the output.

TASK: Implement the circuit for the given function “F”. Function’s output is given in
Table
4.5. Finds its Boolean expression in SoP and PoS forms.
Table 4.5: Truth Table for F (In-Lab)

𝑨 𝑩 𝑪 𝑫 𝑭

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1
 1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Boolean Equations:
Sum of Min-terms equation of F:
A’B’CD+ A’BCD+ AB’C’D’+ ABC’D+ ABCD’+ ABCD

Reduced SOP form equation of F:

A’CD+AC’+ABC

Product of Max-terms equation of F: (A+B+C+D)(A+B+C+D’)(A+B+C”+D)

(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)(A’+B+C+D’)(A’+B+C’+D)(A’+B+C’+D’)
(A+B+C+D)

Reduced POS form equation of F: (A+C)(A+D)(A+B’)(B’+C+D)(A’+B+D’)(B+C’+D)

CRITICAL ANALYSIS:
In this lab we figured out how to carry out and plan the Boolean capacity in
IC'S/Verilog. Through this lab we figured out how to utilize Verilog and likewise
figured out how to carry out the graphical portrayal of Boolean capacities, through
verilog we can carry out capacities without doing genuinely. it’s a product which
helps us a ton

Lab # 5
Consider,

F= your roll no +1024

=105+1024=1129

Conversion of this number in 16 bits binary numbers:

0000010001101001

Truth table:

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Part b and c:

Sum of min terms equation:

F= A’BC’D + AB’C’D+ AB’CD’+ ABC’D’+ ABCD

product of max term equation :

F'=(A+B'+C+D')*(A'+B+C+D’)*(A'+B+C'+D)*(A'+B'+C+D)*(A'+B'+C’+D’)
CRITICAL ANALYSIS:
In this lab, we learnt Karnaugh Map minimization and how to use
logic minimization automated tools for an excessive number of
variables in a function. Minimized logic function results are
verified by using Verilog Structural Level (Gate-Level) description
on Xilinx ISE Design tool.