LAB REPORT #01

NAME:
Ali Hamza
CLASS:
EEE-2

Roll NO:
FA23-EEE-009

COURSE:
DIGITAL LOGIC DESIGN (EEE241)

SUBMITTED TO:
Dr. Ghuffran Ahmed
 LAB REPORT#1:
“INTRODUCTION TO BASIC LOGIC GATES ICs ON
DIGITAL LOGIC TRAINER AND PROTEUS
SIMULATION”
PRE-LAB
Before Lab work we came to know that;
1. Digital logic circuits are represented in three forms;
• Boolean functions
• Logic diagram
• Truth table
2. Electronic gates are also available in the form of ICs (integrated circuits) by which we
performed our lab task.
3. We also studied two families of ICs in this lab ;
• TTL IC FAMILY ( 7400’s IC FAMILY)
• CMOS IC FAMILY (4000’s IC FAMILY)
4. Supply gates INPUTS are driven by voltages having two nominal values of 0 and ,
e.g. 0V,5V and 12V represent 0 and 1 logics respectively.
5. Truth tables are used to help show the functions of the logic gates in terms of
input value giving a desired output value.
6. Logic diagrams are used to represent the digital logic circuits in the form of symbols.
7. Digital logic circuits can be simulated in the virtual environment called
SIMULATION SOFTWARE.
8. There are 7 basic digital logic gates;
• AND
• OR
• NOT
• NAND
• NOR
• XOR
• XNOR

Logic diagrams, truth tables, and simulation of these digital logic gates o a virtual
simulation software are shown below:
 IN-LAB TASK # 1:
BASIC LOGIC GATE INTEGRATED CIRCUITS ON BREADBOARD
MODULE:

1. APPARATUS:

• KL-31001 Digital Logic lab trainer.

• AC-90001 Breadboard module
• Logic Gates Integrated Circuits
• 4001 quad 2-input NOR
• 4011 quad 2-input NAND
• 4070 quad 2-input XOR
• 4071 quad 2-input OR
• 4077 quad 2-input XNOR
• 4081 quad 2-input AND
• 4069 six inverting buffer NOT

2. OBSERVATIONS AND TRUTH TABLE:

• OR Gate using (4071 quad 2-input IC):

• DIAGRAM:

•
•
• TRUTH TABLE FOR OR GATE:
A B F=A+B
0 0 0
0 1 1
1 0 1
1 1 1

• XOR Gate using (4070 quad 2-input)IC:

• TRUTH TABLE FOR XOR LOGIC GATE:

A B F= A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
• NAND Gate using (4011 quad 2-input)IC:

• DIAGRAM:

• TRUTH TABLE FOR NAND GATE:

A B F=◻. ◻
0 0 1
0 1 1
1 0 1
1 1 0

• NOR Gate using (4001 quad 2-input)IC:

• TRUTH TABLE FOR NOR GATE:

A B F=◻ + ◻
0 0 1
0 1 0
1 0 0
1 1 0

• XNOR Gate using (4077 quad 2-input) IC:

• TRUTH TABLE FOR XNOR GATE:

A B F=◻ ⊕◻
0 0 1
0 1 0
1 0 0
1 1 1
• NOT Gate using (4069 six inverting buffer)

• TRUTH TABLE FOR NOT GATE:

INPUT OUTPUT
A B
0 1
1 0

IN-LAB TASK #2:

PROTEUS (SIMULATION

SOFTWARE)

• PROTEUS SIULATION OF AND GATE:

• DIAGRAM:
• TRUTH TABLE FOR AND GATE:
A B F= A.B
0 0 0
0 1 0
1 0 0
1 1 1

• PROTEUS SIMULATION OF OR GATE:

• TRUTH TABLE FOR OR GATE:
A B F=A+B
0 0 0
0 1 1
1 0 1
1 1 1

• PROTEUS SIMULATION OF XOR GATE:

• DIAGRAM:
• TRUTH TABLE FOR XOR GATE:
A B F= A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

• PROTEUS SIMULATION OF NAND GATE:

• TRUTH TABLE FOR NAND GATE:
A B F=◻. ◻
0 0 1
0 1 1
1 0 1
1 1 0

• PROTEUS SIMULATION FOR NOR :

• TRUTH TABLE FOR NOR GATE:
A B F=◻ + ◻
0 0 1
0 1 0
1 0 0
1 1 0

• PROTEUS SIMULATION FOR XNOR GATE:

• DIAGRAM:
• TRUTH TABLE FOR XNOR GATE:
A B F=◻ ⊕◻
0 0 1
0 1 0
1 0 0
1 1 1

• PROTEUS SIMULATION FOR NOT GATE:

DIAGRAM:
TRUTH TABLE FOR NOT GATE:
INPUT OUTPUT
A B
0 1
1 0
 POST LAB TASK:
MAKE LIST OF LOGIC GATES IC OF TTL AND CMOS FAMILY ALONG WITH
THE ICs NAMES:

S# 7400 IC FUNCTIONS
1 7400 Quad 2-input NAND gate
2 7402 Quad 2-input NOR gate
3 7404 Hex inverter
4 7408 Quad 2-input AND gate
5 7432 Quad 2-input OR gate
6 7447 BCD 7-segment display driver or
decoder
7 7474 Twin D-type +ve edge triggered FFs
8 7470 4-bit decode counter
9 7486 Quad 2-input XOR gate
10 7490 4-bit decode counter
11 74138 3-to-8 decode counter
12 74153 Twin 4 – 1 multiplexer
13 74157 Quad D-type FFs with opposite o/ps
14 74160 4-bit binary synchronous counter
15 74164 8-bit synchronous up and down binary
counter

S# 4000 IC FUNCTIONS
1 4001 Quad 2-input NOR gate
2 4008 4-bit binary full adder
3 4011 Quad 2-input NAND gate
4 4013 Dual type flip flop
5 4014 8-stage parallel- in shift register
6 4015 Dual 4-bit static shift register
7 4016 Quad bilateral switch
8 4017 5- stage Johnson decade counter
9 4023 Triple 3-input NAND gate
10 4025 Triple 3-input NOR gate
11 4070 Quad 2-input XOR gate
12 4071 Quad 2-input OR gate
13 4077 Quad 2-input XNOR gate
14 4081 Quad 2-input AND gate
15 4069 Six inverting buffer NOT

QUESTION NO. 2:

WHAT IS FAN-IN AND FAN-OUT?

ANSWER:

Fan-in :
Fan-in is defined as the number of input gate has. For example, a two input gate will
have a fan-in equal to 2.

Fan-out:
Fan-out is a term that defines the maximum number of digital inputs that the output of a
single logic gate can feed. Most transistor-transistor logic (TTL) gates can drive up to
10 other digital gates or devices.

CRITICAL ANALYSIS
After performing the lab tasks mentioned above we learnt;
1. The basic digital logic gates,
• AND
• OR
• NAND
• NOR
• NOT
• XOR
• XNOR
2. Truth tables of these logic gates
3. OUTPUT-INPUT characteristics
4. How to simulate the digital logic gates on virtual software
Or SIMULATION SOFTWARE, we used; Proteus
Software.