Lecture 7: Logical effort

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 1

Logical Effort

• Logical effort of a gate presents the ratio of its

input capacitance to the inverter capacitance when
sized to deliver the same current
• Inverter has the smallest logical effort and intrinsic
delay of all static CMOS gates
• Logical effort increases with the gate complexity

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Logical effort

Logical effort is the ratio of input capacitance of a gate to the

input capacitance of an inverter with the same output current
C g ,nand 4
= (2 input)
C g ,inv 3
N +2
= = g nand (N input)
3
Cint, nand 6
= = 2 (2 input)
Cint, inv 3
2N + N
= = N = pnand
3
(N input)

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Logical effort

C g ,nand 5
= (2 input)
C g ,inv 3
2N +1
= = g nor (N input)
3
Cint, nand 6
= = 2 (2 input)
Cint,inv 3
2N + N
= = N = pnor
3
Logical effort g: How much harder it (N input)
is to drive an equivalent gate
compared to an inverter
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Logical effort

t p 0,nand = pnand t p 0,inv

Output current is the same

ID,inv=ID,nand
Cint, nand Cint,inv
t p 0,nand µ ; t p 0,inv µ
I D ,nand I D ,inv
Equivalent inverter t p 0,nand = pnand t p 0,inv

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Inverter with Load

CP = 2Cunit Delay
2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

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Delay Formula

Delay ~ RW (Cint + CL )
t p = kRW Cint (1+ CL /Cint )
= t p 0 (1+ fCgin /gCgin )
= t p 0 (1+ f /g )
Cint = gCgin with g » 1
f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit

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Logical effort

Cint, nand pCint,inv p

g nand = = = g inv
C g ,nand gC g ,inv g
fg
t p ,nand = pt 0,inv [1 + ]
pg inv
fg Electrical effort
= t p 0,inv [ p + ]
g inv
Logical effort

Intrinsic delay

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Chain of gates

N f jgj
t p = t p 0,inv å ( Pj + )
j =1 g inv
tp is minimized when f i gi = f i +1 gi +1 = ... = h (const)
Note: compared to inverter chain, gi appears
If all gates were inverter à gi=1
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Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

æ Cgin, j +1 ö
t pj ~ RunitCunit ç1 + ÷
ç gC ÷
è gin , j ø
N N æ Cgin, j +1 ö
t p = å t p , j = t p 0 å ç1 + ÷, Cgin, N +1 = CL
ç gC
i =1 è
÷
j =1 gin, j ø

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Optimal tapering for given N

N Næ C gin, j +1 ö
t p = å t p , j = t p 0 å ç1 + ÷, C gin, N +1 = C L
ç gC
i =1 è
÷
j =1 gin, j ø

dt p t p0 1 C gin, j +1
= ( - )
dC gin, j g C gin, j -1 C gin, j 2

Optimum when
dt p C gin, j C gin, j +1
=0® = = f Scale factor
dC gin, j C gin, j -1 C gin, j
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay

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Chain of gates

CL
P fj = F =
j C g1
F: overall electrical effort

Pgj =G
j
G: path logical effort

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Chain of gates

P f j P g j = h N = H = FG
j j
Path logical effort

Gate effort path effort Path electrical effort

Gate effort: product of gate electrical and logical efforts

F: known
G: known
H=FG: known
h=H1/Nàfi=h/gi
fi contains information regarding scale factors
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Logical Effort of Gates

t pNAND
Normalized delay (d)

g= tpINV
p=
d=
g=
p=
d=

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

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Logical Effort of Gates

t pNAND
Normalized delay (d)

g = 4/3 tpINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

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Logical Effort of Gates

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Chain of gates

f1 f2 f3

1 2 3
Cg1
Cint1 Cg2 Cint2

Cg1 is known: S1=Cg1/Cg1,ref, f: known

Cg2=f1Cg1=S2Cg2,ref
f1g1S1=S2g2;Si+1gi+1=figiSi

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Example

S1=1 S2 S3

Cg1
Cint1 Cg2Cint2 Cg3 Cint3 CL

CL=10Cg1; ginv=1; tp0,inv=100ps

Reference inverter b ratio=2:1, S1=1

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Example

S=1
C g ,nand 5
= (2 input)
C g ,inv 3
2N +1
= = g nor (N input)
3
Cint, nand 6
= = 2 (2 input)
Cint,inv 3
2N + N
= = N = pnor
3
(N input)

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Example

S=1
C g ,nand 4
= (2 input)
C g ,inv 3
N +2
= = g nand (N input)
3
Cint, nand 6
= = 2 (2 input)
Cint, inv 3
2N + N
= = N = pnand
3
(N input)
For 3 input: g=5/3, p=3
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Example

• F=10Cg1/Cg1=10
• G=g1g2g3=5/3x5/3x1=25/9
• FG=H=250/9 àh=(250/9)1/3@3
• figi=h=3
• f1=3/5x3=9/5=1.8
• f2=3/5x3=9/5=1.8
• f3=3
• à Completes out designs à determine scale
factor (S1, S2, S3)
• à Determine overall delay

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Example

3
fi gi
t p 0,min = t p 0,inv å ( Pi + )
i =1 g inv
= 100 ps (2 + 3 + 3 + 3 + 1 + 3) = 1500 ps
t p1 = 100 ps ´ 5 = 500 ps
t p 2 = 100 ps ´ 6 = 600 ps
t p 3 = 100 ps ´ 4 = 400 ps

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Example

Cg 2
f1 = ® f1C g 1 = C g 2
Cg1
f1S1C g 1,ref = S 2C g 2,ref
f1S1g 2nor = S 2g 3nand
5 3
S 2 = 1.8 ´ 1´ ´ = 1.8
3 5
f2S 2g 3nand = S 3ginv
5
S 3 = 1.8 ´ 1.8 ´ = 5.4
3

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Example2

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Branching

• Fan-out in the logic chain leads to branching

Co2,1 Co4
1 2 3 4
Cg1 Cg3 Cg4 CL
Cg2

Co2,2

Con- path , j +1 + Coff - path , j +1 Con- path , j +1 + Coff - path , j +1

bj = ; fj =
Con- path , j +1 Cg , j
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Branching

C g 2 + Co 2
b1 = ; Co 2 = Co 2,1 + Co 2, 2
Cg 2
Cg 3 C g 4 + Co 4
b2 = = 1; b3 = , b4 = 1
Cg 3 Cg 4
CL f1 f 2 f 3 f 4
F= = àOn path cap ratio
C g1 b1 b2 b3 b4
C g 2 + Co 2 Cg 2 C g 3 C g 3 C g 4 + Co 4 Cg 4 CL
=[ ][ ][ ][ ]
C g1 C g 2 + Co 2 C g 2 C g 3 Cg 3 C g 4 + Co 4 C g 4
Pf i Pf i
F= = ® Pf i = FB
Pbi B
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Branching

GFB = H = Pf i g i
Same as unbranched case
f i g i = h ® h = H 1/ N
𝑐!"#,%&"𝑐!"#,%''
! 𝑓! 𝑔! = ! 𝑔!
𝑐!
!
𝑐!"#,%& 𝑐!"#,%& + 𝑐!"#,%''
= ! 𝑔! = 𝐺𝐹𝐵
𝑐! 𝑐!"#,%&
!
N
fi gi
t p min = t p 0,inv å ( Pj + )
j =1 g
N
NH 1/ N
= t p 0,inv (å Pj + )
j =1 g

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 Scale factor

2 Con- path , j +1 + Coff - path , j +1

fj =
Cg , j
f i C g ,i +1
1 2 = à On path cap ratio
Cg1 bi Cg , j
Cg2
Electrical effort after
factoring out the branching
2 effort

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Branching

𝑓! 𝐶(,!"# 𝑓!
= −→ 𝐶(,! = 𝐶(,!"# àElectrical effort
𝑏! 𝐶(,! 𝑏!
after factoring out
the branching effort
𝑓!
𝑆! 𝑔! 𝐶)*',!&+,𝑆!"#𝑔!"#𝐶)*',!&+
𝑏!

'! (!
𝑆!"# = 𝑆
-! ! (!"#

.# (# /0# '!
𝑆! = ∏/
(! -!

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Example

Cinv

1000Cinv

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Sideloads

Cinv
Cout

Cinv CA Cout

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Sideloads

3!"#
Delay=∑ 𝑇12(𝑝! + 𝑔! 𝑓! ) = ∑ 𝑇12(𝑝! + 𝑔! )
3!
𝑐! 𝑐!"#
𝑔!0# = 𝑔!
𝑐!0# 𝑐!
• Back to basics, constant gf results minimum delay,
• Concept of FO4 applies

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Example

"$!"

"$$!"
!"#à#

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Sideloads

w x y

1 A B

A=8, B=64

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Sideloads

𝑌 4 = 𝐵𝑋, 𝑌 = 16 à without side load

With side load:
𝑋 = 𝐴 + 𝑌, 𝑌 + 𝐴 𝑌 = 64𝑋
−→ 𝑋 = 4.9, 𝑌 = 14.15

• Alternative way of sizing with sideloads

(suboptimal)
– Solve without sideloads
– Add sideload. Remove gates beyond sideload by
including their loading effects. Solve subproblem
– Combine two solutions

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 35

Multistage Networks

Stage effort: hi = gifi --> Should be constant

Path electrical effort: F = Cout/Cin à not total fanout
Path logical effort: G = g1g2…gN à main path
Branching effort: B = b1b2…bN à FB to get total fanout
Path effort: H = GFB à total effort
Path delay D = Σdi = Σpi + Σhi

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Dynamic Power Dissipation in CMOS logic gates

2
Pdyn = CLVDD f 0®1
f 0®1 = a 0®1 f clk
a 0®1 Number of 0à1 transitions in Tclk: activity factor
0 < a 0®1 Can be greater than 1
Energy for 0à1 and 1à0 transitions and Pdyn do not
depend on NMOS and PMOS sizes
Pdyn can be reduced by reducing VDD, CL and a

• Small size transistors

• Careful placement to minimize interconnect capacitances
• Architecture to minimize activity factor
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Logic function

p0 : probability that the output is in the zero state

p1 : probability that the output is in the one state

a 0®1 = p0 p1 = p0 (1 - p0 )
N 0 N1 N 0 ( 2 N - N 0 )
a 0®1 = N N =
2 2 22 N

N0: the number of zero entries in the output column of the truth table
N1: the number of one entries in the output column of the truth table

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Signal statistics

Two input NOR gate

p A , pB Probability that Input A and B are one
p1 = (1 - p A )(1 - pB )
a 0®1 = p0 p1 = (1 - (1 - p A )(1 - pB ))(1 - p A )(1 - pB )

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Design for reduced switching activity

A O1
O2
B
C F
D

A O1
B
F
C O2
D

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Design for reduced switching activity

O1 O2 F
P1, chain ¼ 1/8 1/16
P0, chain ¾ 7/8 15/16
P(0à1), chain 3/16 7/64 15/256
P1, tree ¼ ¼ 1/16
P0, tree ¾ ¾ 15/16
P(0à1), tree 3/16 3/16 15/256

Activity factor at F should be identical

Lower switching activity in chain implementation
Glitching is an issue

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Input ordering

A B
B C
F F

C A
p ( A = 1) = 0.5
P( B = 1) = 0.2
P(C = 1) = 0.1

p1 = (1 - 0.5 ´ 0.2) ´ 0.5 ´ 0.2 = 0.09

p2 = (1 - 0.2 ´ 0.1) ´ 0.2 ´ 0.1 = 0.0196
Check the activity factor in the internal node
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