VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

VHDL EXAMPLES
AND- GATE
Library IEEE;
Use ieee.std_logic_1164.all;
Entity and1 is
Port (a, b: in std_logic;
Z: out std_logic);
End and1;
Architecture and_gate of and1 is
Begin
z<=a and b;
End and_gate;

OR- GATE

Library IEEE;
Use ieee.std_logic_1164.all;
Entity Or1 is
Port (a, b: in bit;
Y: out bit);
End Or1;
Architecture orgate of Or1 is
Begin
y <= a or b;
End orgate;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

NOT-GATE
Library IEEE;
Use ieee.std_logic_1164.all;
Entity not1 is
Port (a: in bit;
Y: out bit);
End not1;
Architecture not_gate of not1 is
Begin
Y <= not a;
End not_gate;

HALF ADDER
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity halfadder is
Port (a, b: in bit;
S, c: out bit);
End halfadder;
Architecture ha_arch of halfadder is
Begin
s<= a xor b;
c<= a and b;
End ha_arch;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

Structural model oh half adder

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity xor2 is
Port (a, b: in std_logic;
y :out std_logic);
End xor2;
Architecture xor1 of xor2 is
Begin
y<= a xor b;
End xor1;
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity and1 is
Port (c, d: in std_logic;
Z: out std_logic);
End and1;
Architecture and_gate of and1 is
Begin
z<=c and d;
End and_gate;
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity half_adder is
Port (m, n: in std_logic;
Sum, Cry: out std_logic);
End half_adder;
Architecture ha_add of half_adder is
Component xor2
Port (a, b: in std_logic;
Y: out std_logic);
End component;
Component and1
Port(c, d: in std_logic;
z:out std_logic);
End component;
Begin
X: xor2 port map (m, n, sum);
K: and1 port map (m, n, cry);
End ha_add;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

FULL ADDER
Library IEEE;
Use ieee.std_logic_1164.all;
Entity fulladder is
Port (a, b, c: in bit;
S, y: out bit);
End fulladder;
Architecture fa_arch of fulladder is
Begin
s<= (a xor b) xor c;
y<= (a and b) or (a and c) or (b and c);
End fa_arch;

HALF SUBTRACTOR
Library IEEE;
Use ieee.std_logic_1164.all;
Entity HSub is
Port (A, B: in bit;
O, Y: out bit);
End HSub;
Architecture half_sub of HSub is
Begin
O<= A xor B;
Y<= (NOT A) AND B;
END half_sub;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

FULL ADDER USING TWO HALF ADDER

Library IEEE;
Use IEEE.STD_Logic_1164.all;
Entity h_adder is
Port (HA, HB:in std_logic;
HS,HC:out std_logic);
end h_adder;
architecture half of h_adder is
begin
HS<= HA XOR HB;
HC<= HA AND HB;
end half;
Library IEEE;
Use IEEE.STD_Logic_1164.all;
Use IEEE.Numeric_STD.all;
Entity Full_adder is
Port (A, B, C: in std_logic;
Cout, Sum: out std_logic);
End Full_adder;
Architecture f_adder of Full_adder is
Component h_adder
port (HA, HB: in std_logic;
HS, HC: out std_logic);
End component;
Signal S1, C1, C2: std_logic;
Begin
HA1: h_adder port map (HA=> A, HB=> B, HS => S1, HC => C1);
HA2: h_adder port map (HA =>S1, HB=> C, HS => Sum, HC => C2);
Cout <= C1 or C2;
End f_adder

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

FULL SUBTRACTOR

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity f_sub is
Port (A, B, C: in bit;
D, Y: out bit);
End f_sub;
Architecture full_sub of f_sub is
Begin
Y<= a xor b xor c;
d<= ((not a) and b) or ((not a) and c) or (c and b);
End full_sub;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

MULTIPLEXOR IN DATAFLOW MODEL

Library IEEE;
Use ieee.std_logic_1164.all;
Entity mux1 is
Port (E, S0, S1: in bit;
I: in bit_vector (3 downto 0);
Z: out bit);
End mux1;
Architecture mux2 of mux1 is
Begin
Z<= ((not E) and (not S0) and (not S1) and (I (0))) or
((not E) and (not S0) and (S1) and (I (1))) or
((not E) and (S0) and (not S1) and (I (2))) or
((not E) and (S0) and (S1) and (I (3)));
End mux2;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

MULTIPLEXOR IN BEHAVIORAL MODELING

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity mux1 is
Port(s :in std_ulogic_vector (1 downto 0);
i :in std_ulogic_vector (3 downto 0);
Z: out std_logic);
End mux1;
Architecture mux2 of mux1 is
Begin
Process (s, i)
Begin
If ((not s(0) and not s(1)) ='1') then
z<= i(0);
Elsif ((not s(0) and s(1)) ='1') then
z <= i(1);
Elsif ((s(0) and not s(1)) ='1') then
z<= i(2);
Else TRUTH TABLE
z<=i(3);
End if;
End process;
End mux2;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

DE-MULTIPLEXER IN DATAFLOW MODEL

Library IEEE;
Use ieee.std_logic_1164.all;
Entity de_mux is
Port (E, S0,S1: in std_logic ;
D: in std_logic;
Y: out std_ulogic_vector (3 downto 0));
End de_mux;
Architecture de_mux1 of de_mux is
Begin
Y (0) <= ((not E) and (not S0) and (not S1) and D);
Y (1) <= ((not E) and (not S0) and (S1) and D);
Y (2) <= ((not E) and (S0) and (not S1) and D);
Y (3) <= ((not E) and (S0) and (S1) and D);
End de_mux1;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

DECODER IN DATAFLOW MODEL

Library IEEE;
Use ieee.std_logic_1164.all;
Entity decoder is
Port (E, S0, S1: in std_logic ;
D: out std_ulogic_vector (3 downto 0));
End decoder;
Architecture decoder1 of decoder is
Begin
D (0) <= ((not E) and (not S0) and (not S1));
D (1) <= ((not E) and (not S0) and (S1));
D (2) <= ((not E) and (S0) and (not S1));
D (3) <= ((not E) and (S0) and (S1));
End decoder1;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

DECODER IN BEHAVIORAL MODELING

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity decoder is
Port ( I : in std_ulogic_vector (1 downto 0);
E : in std_logic;
y : out std_ulogic_vector (3 downto 0));
End decoder;
Architecture de_c of decoder is
Begin TRUTH TABLE
Process (I)
Begin
If (E = '0') then
Case I is
When "00" => y <= "0001" ;
When "01" => y <= "0010" ;
When "10" => y <= "0100" ;
When "11" => y <= "1000" ;
When others => y <= "0000" ;
End case;
Else y<= "0000";
End if;
End process;
End de_c ;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

Structural model of binary adder

Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity fulladder is FULLADDER
Port (a, b, c: in std_logic;
S, y: out std_logic);
End fulladder;
Architecture fa_arch of fulladder is
Begin
s<= (a xor b) xor c;
y<= (a and b) or (a and c) or (b and c);
End fa_arch;
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity binary_adder is
Port (
m: in std_ulogic_vector (3 downto 0);
N: in std_ulogic_vector (3 downto 0);
O: out std_ulogic_vector (4 downto 0));
End binary_adder;
Architecture bi_add of binary_adder is
Component fulladder
Port (a, b, c: in std_logic; S, y: out std_logic);
End component;
Signal C: std_ulogic_vector (4 downto 0) ;
Begin
c (0)<='0';
FA1: fulladder port map (m (0), n(0), c(0), o(0), c(1));
FA2: fulladder port map (m (1), n(1), c(1), o(1), c(2));
FA3: fulladder port map (m(2), n(2), c(2), o(2), c(3));
FA4: fulladder port map (m(3), n(3), c(3), o(3), c(4));
o (4)<=c(4);
End bi_add;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

Library IEEE; 2-bit multiplier

Use ieee.std_logic_1164.all;
Entity and1 is
Port ( x, y : in std_logic; Z: out std_logic);
End and1;
Architecture and2 of and1 is
Begin
z<= x and y;
End and2;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity xor1 is
Port ( m, n : in std_logic; p: out std_logic);
End xor1;
Architecture xor2 of xor1 is
Begin
p<= m xor n;
End xor2;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity multi is
Port (a: in std_ulogic_vector (1 downto 0);
b: in std_ulogic_vector(1 downto 0);
o: out std_ulogic_vector(3 downto 0));
End multi; ---//to multiple a(1)a(0) with b(1)b(0)//
Architecture multi_1 of multi is
Component and1
Port (x,y :in std_logic; z: out std_logic);
End component;
Component xor1
Port ( m, n : in std_logic ; p: out std_logic);
End component;
Signal g: std_ulogic_vector (3 downto 0);
Begin
t1: and1 port map (a(0),b(0),o(0));
t2: and1 port map (a(1),b(0),g(0));
t3: and1 port map (b(1),a(0),g(1));
t5: xor1 port map (g(0),g(1),o(1));
t6: and1 port map (g(0),g(1),g(2));
t4: and1 port map (a(1),b(1),g(3));
t7: xor1 port map (g(2),g(3),o(2));
t8: and1 port map (g(2),g(3),o(3));
End multi_1;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

SR-LATCH USING NAND GATES

Library IEEE;
Use ieee.std_logic_1164.all;
Entity nand2 is
Port (a, b: in std_logic;
Y: out std_logic);
End nand2;
Architecture nand1 of nand2 is
Begin
y<= a nand b;
End nand1;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity sr_latch is
Port(s, r: in std_logic;
Q, qbar: inout std_logic);
End sr_latch;
Architecture sr_l of sr_latch is
Component nand2
Port (a, b: in std_logic; FUNCTION TABLE
Y: out std_logic);
End component;
Begin
n: nand2 port map (s, qbar, Q );
m: nand2 port map (r, Q, qbar );
End sr_l;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

D-latch using nand gates

Library IEEE;
Use ieee.std_logic_1164.all;
Entity nand2 is
Port (a, b: in std_logic;
Y: out std_logic);
End nand2;
Architecture nand1 of nand2 is
Begin
y<= a nand b;
End nand1;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity not1 is
Port (c: in std_logic;
o : out std_logic);
End not1;
Architecture not2 of not1 is FUNCTION TABLE
Begin
o<= not c;
End not2;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity d_latch is
Port (d: in std_logic;
Q, qbar: inout std_logic);
End d_latch;
Architecture d_lat of d_latch is
Signal dbar: std_logic;
Component nand2
Port (a, b: in std_logic;
Y: out std_logic);
End component;
Component not1
Port (c: in std_logic;
o: out std_logic);
End component;
Begin
k: not1 port map (d, dbar);
n: nand2 port map (d, qbar, Q);
m: nand2 port map ( dbar, Q, qbar);
End d_lat;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

D-FLIPFLOP

Library IEEE;
Use ieee.std_logic_1164.all;
Entity d_ff is
Port (d, clk: in std_logic;
q: out std_logic);
End d_ff;
Architecture d_flip of d_ff is
Begin
Process (clk)
Begin
if clk ='1' and clk'event then
q <= d;
End if;
End process;
End d_flip;

T-FLIPFLOP
Library IEEE;
Use ieee.std_logic_1164.all;
Entity tff is
Port (t, clk: in std_logic;
q: inout std_logic);
End tff;
Architecture tff1 of tff is
Begin
Process (t, clk)
Begin
q<='0';
If (clk='1' and clk'event) then
If (t='1') then
q<= not q;
Else
q<= q;
End if;
End if;
End process;
End tff1;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

SR-FLIPFLOP
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity nand2 is
Port (a, b: in std_logic;
Y: out std_logic);
End nand2;
Architecture nand1 of nand2 is
Begin
y<= a nand b;
End nand1;
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity sr_ff is
Port(s, r, clk: in std_logic;
Q, qbar: inout std_logic);
End sr_ff;
Architecture sr_f of sr_ff is
Component nand2
Port (a, b: in std_logic;
Y: out std_logic);
End component;
Signal o: std_ulogic_vector (1 downto 0);
Begin
l: nand2 port map (s, clk, o(0));
p: nand2 port map (r, clk, o(1));
n: nand2 port map (o(0), qbar, q);
m: nand2 port map (o(1), Q, qbar);
End sr_f ;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

JK FLIP-FLOP

Library IEEE;
Use ieee.std_logic_1164.all;
Entity jkf is
Port (j, k, clk: in std_logic;
Q, QBAR: inout std_logic);
End jkf;
Architecture jkff of jkf is
Begin
Process (clk, j, k)
Begin
If (clk='1' and clk'event) then
If (j='0' and k='0') then
Q <= Q;
QBAR <= QBAR;
Elsif (j='0' and k='1') then
Q <= '0';
QBAR <= '1';
Elsif (j='1' and k='0') then TRUTH TABLE
Q <= '1';
QBAR <= '0';
Elsif (j='1' and k='1') then
Q <= not q;
QBAR <= not qbar;
End if;
End if;
End process;
End jkff;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

JK FLIP-FLOP using CASE Statement

Library IEEE;
Use ieee.std_logic_1164.all;
Entity JK_FF is
Port (clk: in std_logic;
J, K: in std_logic;
Reset: in std_logic;
Q, Qbar: out std_logic);
End JK_FF;
Architecture behv of JK_FF is
Signal state: std_logic;
Signal input: std_ulogic_vector (1 downto 0);
Begin
Input <= J & K;
P: process (clock, reset) is
Begin
If (reset='1') then
State <= '0';
Elsif (rising_edge(clock)) then TRUTH TABLE
Case (input) is
When "11" =>
State <= not state;
When "10" =>
State <= '1';
When "01" =>
State <= '0';
When "00" =>
State <= state;
When others =>
null;
End case;
End if;

End process;
Q <= state;
Qbar <= not state;
End behv;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

SERIAL-IN-SERIAL-OUT SHIFT REGISTER

Library IEEE;
Use ieee.std_logic_1164.all;
Entity d_ff is
Port (d, clk: in std_logic;
q: out std_logic);
End d_ff;
Architecture d_flip of d_ff is
Begin
Process (clk)
Begin
if clk ='1' and clk'event then
q <= d;
End if;
End process;
End d_flip;
Library IEEE;
Use ieee.std_logic_1164.all;
Entity siso is
Port ( i, clk :in std_logic;
y: out std_logic);
End siso;
Architecture siso_r of siso is
Signal qa, qb, qc: std_logic;
Component d_ff is
Port (d, clk :in std_logic;
q: out std_logic);
End component;
Begin
a1: d_ff port map (i, clk, qa);
a2: d_ff port map (qa, clk, qb);
a3: d_ff port map (qb, clk, qc);
a4: d_ff port map (qc, clk ,y);
End siso_r;

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 VIGNAN INSTITUTE OF TECHONOLOGY AND MANAGEMENT

UP-COUNTER
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity up_counter is
Port (cout : out std_logic_vector (7 downto 0);
Enable: in std_logic;
Clk : in std_logic;
Reset: in std_logic);
End entity;
Architecture struct1 of up_counter is
Signal Count: std_logic_vector (7 downto 0);
Begin
Process (clk, reset) begin
If (reset = '1') then
Count <= (others=>'0');
Elsif (rising_edge (clk)) then
If (enable = '1') then
Count <= count + 1;
End if;
End if;
End process;
Cout <= count;
End sruuct1;

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