VHDL

Lab File
SUBMITTED BY
Giric Goyal

A2305208361

Roll No. 514

5CS3 (Y)

B.TECH (CSE)

SESSION: 2008-2012
 INDEX

S.No DESCRIPTION Date Signature

 EXPERIMENT NO 2

AIM: To implement HALF ADDER in VHDL using dataflow,

behavioral and structural style of modeling.

Theory:
Half adder is the most basic digital arithmetic circuit. It is a logical circuit that
performs an addition operation on two binary digits. It is a combinational circuit
which produces a sum and a carry value, which are both binary digits.
A half adder has two inputs, generally labeled A and B, and two outputs, the
“sum” S and “carry flag” C.

S is the two-bit “XOR gate” of A and B, and C is the “AND gate” of A and B.

S= A xor B
C=A and B

Following is the truth table for a half adder is –

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Dataflow code for Half Adder

CODE: library ieee;

use ieee.std_logic_1164.all;
entity half_adder is
port (a,b:in bit;
sum,carry:out bit);
end half_adder;
architecture E of half_adder is
begin
sum<= a xor b;
carry<=a and b;
end E;

OUTPUT WAVEFORM:
Behavioral code for Half Adder

CODE: library ieee;

use ieee.std_logic_1164.all;
entity half_adder is
port (a,b: in bit;
sum,carry:out bit);
end half_adder;
architecture E of half_adder is
begin
process(a,b)
variable q: bit_vector(0 to 1);
begin
q :=a & b;
case q is
when "00"=> sum<='0';
carry<='0';
when "01"=> sum<='1';
carry<='0';
when "10"=> sum<='1';
carry<='0';
when "11"=> sum<='0';
carry<='1';
end case;
end process ;
end E;

OUTPUT WAVEFORM:
Structural code for Half Adder

CODE: library ieee;

use ieee.std_logic_1164.all;
entity xorg is
port (a,b: in bit;
z:out bit);
end xorg;
architecture E of xorg is
begin
z<= a xor b;
end E;
entity andg is
port (a,b: in bit;
z: out bit);
end andg;
architecture E1 of andg is
begin
z<= a and b;
end E1;
entity half_adderg is
port (a1,b:in bit;
sum,carry:out bit);
end half_adderg;
architecture E2 of half_adderg is
component xorg
port (a,b:in bit;
z:out bit);
end component;
component andg
port (a,b: in bit;
z: out bit);
end component;
begin
A3: xorg port map (a1,b,sum);
A2: andg port map (a1,b,carry);
end E2;

OUTPUT WAVEFORM:
 EXPERIMENT NO 3

AIM: To implement FULL ADDER in VHDL using dataflow,

behavioral and structural style of modeling.

Theory:
Full adder is a combinational circuit that performs an addition operation on three
binary digits. It produces a sum and a carry value, which are both binary digits.
A half adder has three inputs, generally labelled A, B, and Cin, and two outputs,
the “sum” S and “carry flag” Cout.

S is the two-bit “XOR gate” of A, B, and Cin.

S= A xor B xor Cin
Cout=A.B+ (A xor B) Cin

Following is the truth table for a full adder is-

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Dataflow code for Full Adder

CODE
library ieee;
use ieee.std_logic_1164.all;
entity full_adder1 is
port (a,b,c:in bit;
sum,carry:out bit);
end full_adder1;
architecture e1 of full_adder1 is
begin
carry<=(a and b) or (b and c) or (c and a);
sum<=a xor b xor c;
end e1;

OUTPUT WAVEFORM:
Behavioral code for full adder

CODE:
library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(a:in bit_vector(0 to 2);
sum,carry:out bit);
end fulladder;
architecture e1 of fulladder is
begin
P1:process(a)
begin
case a is
when "000"=>sum<='0';carry<='0';
when "001"=>sum<='1';carry<='0';
when "010"=>sum<='1';carry<='0';
when "011"=>sum<='0';carry<='1';
when "100"=>sum<='1';carry<='0';
when "101"=>sum<='0';carry<='1';
when "110"=>sum<='0';carry<='1';
when "111"=>sum<='1';carry<='1';
end case;
end process p1;

OUTPUT WAVEFORM:
Structural code for full adder
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port (a,b:in bit;
z:out bit);
end andg;
architecture E of andg is
begin
z<= a and b;
end E;
entity org is
port (a,b,c: in bit;
z: out bit);
end org;
architecture E1 of org is
begin
z<=a or b or c;
end E1;
entity xorg is
port(a,b,c:in bit;
z:out bit);
end xorg;
architecture E2 of xorg is
begin
z<=a xor b xor c;
end E2;
entity full_adderg is
port (a1,b,c:in bit;
sum,carry:out bit);
end full_adderg;
architecture E3 of full_adderg is
component andg
port (a,b:in bit;
z:out bit);
end component;
component org
port (a,b,c: in bit;
z: out bit);
end component;
component xorg
port(a,b,c:in bit;
z:out bit);
end component;
signal x1,x2,x3:bit;
begin
A4: andg port map (a1,b,x1);
A2: andg port map (b,c,x2);
A3: andg port map (a1,c,x3);
OR1: org port map (x1,x2,x3,sum);
XOR1: xorg port map (a1,b,c,carry);
end E3;

OUTPUT WAVEFORM:
 EXPERIMENT NO 4

AIM: To implement a 4X1 multiplexer in VHDL using dataflow,

behavioral and structural style of modeling.

Datafllow code for 4 to 1 multiplexer:

FUNCTION:Y=((d0 and (not s0) and (not s1)) or

(d1 and (not s1) and s0) or
(d2 and s1 and (not s0)) or
(d3 and s0 and s1))

CODE:
library ieee;
use ieee.std_logic_1164.all;
entity mux41 is
port (a,b,c,d,s1,s2:in bit;
z:out bit);
end mux41;
architecture e1 of mux41 is
begin
z<=(((not s1) and (not s2) and a) or ((not s1) and (s2) and b) or ((s1) and (not s2) and c) or
((s1) and (s2) and d));
end e1;

OUTPUT WAVEFORM
Behavioral code for 4 to 1 multiplexer
TRUTH TABLE:

I/P O/P
S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
CODE:
library ieee;
use ieee.std_logic_1164.all;
entity mux4 is
port(a,b,c,d,s1,s2:in bit;
z:out bit);
end mux4;
architecture e1 of mux4 is
begin
process(a,b,c,d,s1,s2)
begin
if s1&s2="00"
then z<=a;
elsif s1&s2="01"
then z<=b;
elsif s1&s2="10"
then z<=c;
else z<=d;
end if;
end process;
end e1;

OUTPUT WAVEFORM:

Structural code for 4X1 multiplexer:

CODE: library ieee;

use ieee.std_logic_1164.all;
entity mux4str is
port(d0,d1,d2,d3,s0,s1:in std_logic;y:out std_logic);
end mux4str;
architecture gate of mux4str is
component not1
port(a:in std_logic;y:out std_logic);
end component;
component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;
component or4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;
signal x1,x2,x3,x4,x5,x6:std_logic;
begin
u0:not1 port map(s0,x1);
u1:not1 port map(s1,x2);
u2:and3 port map(x1,x2,d0,x3);
u3:and3 port map(x1,s1,d1,x4);
u4:and3 port map(x2,s0,d2,x5);
u5:and3 port map(s0,s1,d3,x6);
 u6:or4 port map(x3,x4,x5,x6,y);
end gate;

OUTPUT WAVEFORM:

EXPERIMENT NO 5

AIM: To implement a 3X8 decoder in VHDL using dataflow,

behavioral and structural style of modeling.

Theory:
A decoder is a device which does the reverse of an encoder, undoing the
encoding so that the original information can be retrieved. The same method
used to encode is usually just reversed in order to decode.
In digital electronics, a decoder can take the form of a multiple-input, multiple-
output logic circuit that converts coded inputs into coded outputs, where the
input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs
assume a single "disabled" output code word. Decoding is necessary in
applications such as data multiplexing, 7 segment display and memory address
decoding.
Dataflow code for 3:8 decoder:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(x,y,z,enable:in bit;a,b,c,d,e,f,g,h:out bit);
end decoder;
architecture deco1 of decoder is
begin
a<=((not x)and (not y)and (not z));
b<=((not x)and (not y)and z);
c<=((not x)and y and (not z));
d<=((not x)and y and z);
e<=(x and (not y)and (not z));
f<=(x and (not y)and z);
g<=(x and y and (not z));
h<=(x and y and z);
end deco1;
OUTPUT WAVEFORM

Structural code for 3:8 decoder:

CODE: library ieee;

use ieee.std_logic_1164.all;
entity notg is
port(a:in bit;
b: out bit);
end notg;
architecture e1 of notg is
begin
b<= not a;
end architecture;
entity andg is
port(a,b,c:in bit;
d: out bit);
end andg;
architecture e2 of andg is
begin
d<= a and b and c;
 end architecture;
entity main is
port( a: in bit_vector(0 to 2);
d: out bit_vector(0 to 7));
end main;
architecture main of main is
component notg is
port(a:in bit;
b: out bit);
end component;
component andg is
port(a,b,c:in bit;
d: out bit);
end component;
signal x,y,z:bit;
begin
x1:notg port map(a(0),x);
x2:notg port map(a(1),y);
x3:notg port map(a(2),z);
x4:andg port map(x,y,z,d(0));
x5:andg port map(x,y,a(2),d(1));
x6:andg port map(x,a(1),z,d(2));
x7:andg port map(x,a(1),a(2),d(3));
x8:andg port map(a(0),y,z,d(4));
x9:andg port map(a(0),y,a(2),d(5));
x10:andg port map(a(0),a(1),z,d(6));
x11:andg port map(a(0),a(1),a(2),d(7));
end architecture;

OUTPUT WAVEFORM
Behavioral code for 3:8 decoder:

CODE: library ieee;

use ieee.std_logic_1164.all;
entity decoder is
port (s:out bit_vector(0 to 7);
a:in bit_vector(0 to 2));
end decoder;
architecture behaviour of decoder is
begin
process(a)
begin
case a is
when "000" => s<="10000000";
when "001" => s<="01000000";
 when "010" => s<="00100000";
when "011" => s<="00010000";
when "100" => s<="00001000";
when "101" => s<="00000100";
when "110" => s<="00000010";
when "111" => s<="00000001";
end case;
end process;
end behaviour;

OUTPUT WAVEFORM

EXPERIMENT NO 6

AIM: To implement a D, T, S-R, J-K Flip Flop using behavioural style

of modeling.

Theory:

D FLIP FLOP : The Q output always takes on the state of the D input at the
moment of a rising clock edge (or falling edge if the clock input is active low).
[7]
It is called the D flip-flop for this reason, since the output takes the value of
the D input or Data input, and Delays it by one clock count. The D flip-flop can
be interpreted as a primitive memory cell, zero-order hold, or delay line.
Truth table:

Clock D Q Qprev

Rising
0 0 X
edge

Rising
1 1 X
edge

Non-Rising X Qprev

Behavioral code for D flip flop:

CODE: library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
entity diff is
port(d,clk:in bit;
q,qbar:inout bit);
end diff;
 architecture behav of diff is
begin
process(d,clk)
begin
if clk='1' and clk' event
then
q<= d;
qbar<= not d;
end if;
end process;
end behav;
OUTPUT WAVEFORM

T FLIP FLOP :
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock
input is strobed. If the T input is low, the flip-flop holds the previous value. This
behavior is described by the characteristic equation:
(or, without benefit of the XOR operator, the
equivalent: )
 and can be described in a truth table:

T Flip-Flop operation [6]

Characteristic table Excitation table

T Q Qnext Comment Q Qnext T Comment

0 0 0 hold state (no clk) 0 0 0 No change

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement

Behavioral code for T flip flop:

CODE: library ieee;
use ieee.std_logic_1164.all;
 entity tiff is
port(t,clk:in bit;
q,qbar:inout bit);
end tiff;
architecture behav of tiff is
begin
process(t,clk)
begin
if clk='1' and clk' event
then
q<=not t;
qbar<=t;
end if;
end process;
end behav;

OUTPUT WAVEFORM

SR FLIP FLOP :
The fundamental latch is the simple SR flip-flop, where S and R stand
for set and reset, respectively. It can be constructed from a pair of cross-
coupled NAND or NORlogic gates. The stored bit is present on the output
marked Q.
Normally, in storage mode, the S and R inputs are both low,
and feedback maintains the Q and Q outputs in a constant state, with Q the
complement of Q. If S is pulsed high while R is held low, then the Q output is
forced high, and stays high even after S returns low; similarly, if R is pulsed high
while S is held low, then the Q output is forced low, and stays low even after R
returns low.

SR Flip-Flop operation (BUILT WITH NOR GATES) [6]

Characteristic table Excitation table

SR Action Q(t) Q(t+1) S R Action

0 0 Keep state 0 0 0 X No change

0 1 Q=0 0 1 1 0 reset

1 0 Q=1 1 0 0 1 set

1 1 Unstable combination 1 1 X 0 race condition

('X' denotes a Don't care condition; meaning the signal is irrelevant)

Behavioral code for SR flip flop:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity srff is
port(s,r,clk:in bit;
q,qbar:inout bit);
end srff;
architecture behav of srff is
begin
process(s,r,clk)
variable g: bit_vector(0 to 1);
begin
g:= s&r;
if clk='1' and clk' event
then
case g is
when "00"=> null;
when "01"=> q<='0'; qbar<='1';
when "10"=> q<='1'; qbar<='0';
when "11"=> assert r/='1' and s/='1'report "invalid condition" severity error;
end case;
end if;
end process;
end behav;

OUTPUT WAVEFORM
JK FLIP FLOP :
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by
interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically,
the combination J = 1, K = 0 is a command to set the flip-flop; the combination J
= 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a
command to toggle the flip-flop, i.e., change its output to the logical complement
of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather,
will hold the current state. To synthesize a D flip-flop, simply set K equal to the
complement of J. The JK flip-flop is therefore a universal flip-flop, because it
can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

JK Flip Flop operation

Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment

0 0 Qprev hold state 0 0 0 X No change

0 1 0 reset 0 1 1 X Set

1 0 1 set 1 0 X 1 Reset

1 1 Qprev toggle 1 1 X 0 No change

Behavioral code for JK flip flop:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity jkff is
port(j,k,clk:in bit;
q,qbar:inout bit);
end jkff;
architecture behav of jkff is
begin
process(j,k,clk)
variable s: bit_vector(0 to 1);
begin
s:= j&k;
if clk='1' and clk' event
then
case s is
when "00"=> null;
when "01"=> q<='0'; qbar<='1';
when "10"=> q<='1'; qbar<='0';
when "11"=> q<=not q; qbar<=q;
end case;
end if;
end process;
end behav;

OUTPUT WAVEFORM
 EXPERIMENT NO 7

AIM: To design shift registers in VHDL using structural.

Theory:
These are the simplest kind of shift registers. The data string is presented at 'Data
In', and is shifted right one stage each time 'Data Advance' is brought high. At
each advance, the bit on the far left (i.e. 'Data In') is shifted into the
0 0 0 0
first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted
out and lost. 1 0 0 0
0 1 0 0
The data are stored after each flip-flop on the 'Q' output, so there are
four storage 'slots' available in this arrangement, hence it is a 4-Bit 1 0 1 0
Register. To give an idea of the shifting pattern, imagine that the 1 1 0 1
register holds 0000 (so all storage slots are empty). As 'Data In' 0 1 1 0
presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' 0 0 1 1
each time. This is called clocking or strobing) to the register, this is the
0 0 0 1
result. The left hand column corresponds to the left-most flip-flop's
output pin, and so on. 0 0 0 0

So the serial output of the entire register is 10110000 (). As you can see if we
were to continue to input data, we would get exactly what was put in, but offset
by four 'Data Advance' cycles. This arrangement is the hardware equivalent of
a queue. Also, at any time, the whole register can be set to zero by bringing the
reset (R) pins high.
This arrangement performs destructive readout - each datum is lost once it been
shifted out of the right-most bit.
Structural code for SISO:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(d,clk:in bit;
q:out bit);
end dff;
architecture e1 of dff is
begin
process(d, clk)
begin
if clk='1' and clk'event then
q<=d;
end if;
end process;
end e1;
entity siso is
port( input,clk:in bit;
qout:out bit);
end siso;
architecture e1 of siso is
component dff
port(d,clk:in bit;
q:out bit);
end component;
signal q0,q1,q2:bit;
begin
n1:dff port map(input,clk,q0);
n2:dff port map(q0,clk,q1);
n3:dff port map(q1,clk,q2);
n4:dff port map(q2,clk,qout);
end e1;

OUTPUT WAVEFORM
PIPO:

The PARALLEL IN/PARALLEL OUT shift register is loaded with four bits
simultaneously, in parallel.They are also clocked out simultaneously, in parallel.

Structural code for PIPO:

CODE: library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (d,clk:in bit;
q,qbar:out bit);
end dff;
architecture behav of dff is
begin
process (d,clk)
begin
if clk = '1' and clk'event then
q<=d;
qbar<=not d;
end if;
end process;
end behav;
entity pipo is
port (a,b,c,d,clk:in bit;
q0,q1,q2,q3:out bit);
end pipo;
architecture e1 of pipo is
component dff
port (d,clk:in bit;
q,qbar:out bit);
end component;
begin
N1: dff port map (a,clk,q0);
N2: dff port map (b,clk,q1);
N3: dff port map (c,clk,q2);
N4: dff port map (d,clk,q3);
end e1;
OUTPUT WAVEFORM

PISO:
This configuration has the data input on lines D1 through D4 in parallel format.
To write the data to the register, the Write/Shift control line must be held LOW.
To shift the data, the W/S control line is brought HIGH and the registers are
clocked. The arrangement now acts as a SISO shift register, with D1 as the Data
Input. However, as long as the number of clock cycles is not more than the
length of the data-string, the Data Output, Q, will be the parallel data read off in
order.
Structural code for PIPO:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity ctrl is
port(outf1,x,control:in bit;
inpf2:out bit);
end ctrl;
architecture e1 of ctrl is
begin
process(x,control,outf1)
begin
if control='1' then
inpf2<=x;
else
inpf2<=outf1;
end if;
end process;
end e1;
entity dff is
port (d,clk:in bit;
q,qbar:out bit);
end dff;
architecture behav of dff is
begin
process (d,clk)
 begin
if clk = '1' and clk'event then
q<=d;
qbar<=not d;
end if;
end process;
end behav;
entity piso is
port(a,b,c,d,d0,d1,d2,d3:inout bit;
q0,q1,q2,q3:inout bit;
control,clk:in bit);
end piso;
architecture e2 of piso is
component dff
port (d,clk:in bit;
q,qbar:out bit);
end component;
component ctrl
port(outf1,x,control:in bit;
inpf2:out bit);
end component;
begin
d0<=a;
N1: dff port map (a,clk,q0);
N2: ctrl port map (q0,b,control,d1);
N3: dff port map (d1,clk,q1);
N4: ctrl port map (q1,c,control,d2);
N5: dff port map (d2,clk,q2);
N6: ctrl port map (q2,c,control,d3);
N7: dff port map (d3,clk,q3);
end e2;

OUTPUT WAVEFORM
SIPO:
This configuration allows conversion from serial to parallel format. Data is input
serially, as described in the SISO section above. Once the data has been input, it
may be either read off at each output simultaneously, or it can be shifted out and
replaced.

Structural code for PIPO:

CODE: library ieee;
use ieee.std_logic_1164.all;
entity dff is
port (d,clk:in bit;
q,qbar:out bit);
end dff;
architecture behav of dff is
begin
process (d,clk)
begin
if clk = '1' and clk'event then
q<=d;
qbar<=not d;
end if;
end process;
end behav;
entity sipo is
port (input,clk:in bit;
q0,q1,q2,q3:inout bit);
end sipo;
architecture e1 of sipo is
 component dff
port (d,clk:in bit;
q,qbar:out bit);
end component;
begin
N1: dff port map (input,clk,q0);
N2: dff port map (q0,clk,q1);
N3: dff port map (q1,clk,q2);
N4: dff port map (q2,clk,q3);
end e1;

OUTPUT WAVEFORM

EXPERIMENT NO 9

AIM: Design a mod 5 counter

Theory:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. In practice, there are two types
of counters:

• Up counters, which increase (increment) in value

• Down counters, which decrease (decrement) in value

A mod 5 counter counts till binary four and in fifth clock pulse it counts back to
zero.

Behavioral code for mod 5 counter:

CODE: library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY binary_counter IS
port( clk, reset:in bit; count:out std_logic_vector( 0 to 2));
 END ENTITY binary_counter;
ARCHITECTURE binary OF binary_counter IS
signal temp: std_logic_vector( 0 to 2):="000";
BEGIN
process ( clk, reset)
begin
if reset='1' then temp<="000";
else if clk='1' and clk'event then
temp<= temp+ 1;
end if;
end if;
end process;
count<= temp;
END ARCHITECTURE binary;

OUTPUT WAVEFORM
 EXPERIMENT NO 8

AIM: Design a binary counter

Theory:
In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. In practice, there are two types
of counters:

• Up counters, which increase (increment) in value

• Down counters, which decrease (decrement) in value

binary counter is a machine (like a computer) which counts in binary.

Behavioral code for binary counter:

CODE: library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY binary_counter IS
port( clk, reset:in bit; count:out std_logic_vector( 0 to 2));
END ENTITY binary_counter;
ARCHITECTURE binary OF binary_counter IS
signal temp: std_logic_vector( 0 to 2):="000";
BEGIN
process ( clk, reset)
begin
if reset='1' then temp<="000";
else if clk='1' and clk'event then
temp<= temp+ 1;
end if;
end if;
end process;
count<= temp;
END ARCHITECTURE binary;

OUTPUT WAVEFORM
 EXPERIMENT NO 10

AIM: Design simple ALU

Theory:
An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and
logical operations. The ALU is a fundamental building block of the central
processing unit (CPU) of a computer, and even the simplest microprocessors
contain one for purposes such as maintaining timers. The processors found inside
modern CPUs and graphics processing units accommodate very powerful and
very complex ALUs; a single component may contain a number of ALUs.
Behavioral code forALU:
CODE: library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY alu IS
port( a,b:in std_logic_vector(2 downto 0);
sel: in std_logic_vector(3 downto 0);
cin: in std_logic;
y:out std_logic_vector( 2 downto 0));
END ENTITY alu;
ARCHITECTURE alu OF alu IS
BEGIN
process( a,b,sel)
begin
case sel is
--arithmetic unit
when"0000"=> y<=a;
when"0001"=> y<=a+1;
when"0010"=> y<=a-1;
when"0011"=> y<=b;
when"0100"=> y<=b+1;
when"0101"=> y<=b-1;
when"0110"=> y<=a+b;
when"0111"=> y<=a+b+cin;
-- logic unit
when"1000"=> y<= not a;
when"1001"=> y<= not b;
when"1010"=> y<= a and b;
when"1011"=> y<= a or b;
when"1100"=> y<= a nand b;
when"1101"=> y<= a nor b;
when"1110"=> y<= a xor b;
when"1111"=> y<= not ( a xor b);
when others=> null;
end case;
end process;
END ARCHITECTURE alu;

OUTPUT WAVEFORM
 EXPERIMENT NO 1

AIM: To implement logic gates

Theory:
OR GATE
The OR gate is a digital logic gate that implements logical disjunction - it
behaves according to the truth table to the right. A HIGH output (1) results if one
or both the inputs to the gate are HIGH (1). If neither input is HIGH, a LOW
output (0) results.

INPUT OUTPUT
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

Behavioral code for OR gate:

CODE: library ieee;
use ieee.std_logic_1164.all;
entity orgate is
port(a,b:in bit;
x:out bit);
end orgate;
 architecture behav of orgate is
begin
p1:process(a,b)
begin
if a='0' and b='0'
then x<='0';
elsif a='0' and b='1'
then x<='1';
elsif a='1' and b='0'
then x<='1';
else x<='1';
end if;
end process p1;
end behav;

OUTPUT WAVEFORM

NOR GATE:

The NOR gate is a digital logic gate that implements logical NOR - it behaves
according to the truth table to the right. A HIGH output (1) results if both the
inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW output
(0) results. NOR is the result of the negation of the OR operator. NOR is a
functionally complete operation -- combinations of NOR gates can be combined
to generate any other logical function. By contrast, the OR operator is monotonic
as it can only change LOW to HIGH but not vice versa.

INPUT OUTPUT
A B A NOR B
0 0 1
0 1 0
1 0 0
1 1 0

Behavioral code for NOR gate:

CODE: library ieee;
use ieee.std_logic_1164.all;
 entity norgate is
port(a,b:in bit;
x:out bit);
end norgate;
architecture behav of norgate is
begin
p1:process(a,b)
begin
if a='0' and b='0'
then x<='1';
elsif a='0' and b='1'
then x<='0';
elsif a='1' and b='0'
then x<='0';
else x<='0';
end if;
end process p1;
end behav;

OUTPUT WAVEFORM

XOR GATE:
The XOR gate (sometimes EOR gate) is a digital logic gate that implements
exclusive disjunction - it behaves according to the truth table above. A HIGH
output (1) results if one, and only one, of the inputs to the gate is HIGH (1). If
both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results.

XOR gate is short for exclusive OR. This means that precisely one input must be
1 (true) for the output to be 1 (true). A way to remember XOR is "one or the
other but not both."

INPUT OUTPUT
A B A XOR B
0 0 0
0 1 1
1 0 1
1 1 0

Behavioral code for XOR gate:

CODE: library ieee;
use ieee.std_logic_1164.all;
entity exor is
port( a,b: in bit;
z: out bit);
end exor;
architecture x1 of exor is
begin
process(a,b)
variable c: bit_vector(0 to 1);
begin
c:= a&b;
case c is
when "00" => z<='0';
when "01" => z<='1';
when "10" => z<='1';
when "11" => z<='0';
end case;
end process;
end x1;
OUTPUT WAVEFORM
XNOR GATE:

The XNOR gate (sometimes spelled "exnor" or "enor") is a digital logic gate
whose function is the inverse of the exclusive OR (XOR) gate. The two-input
version implements logical equality, behaving according to the truth table to the
right. A HIGH output (1) results if both of the inputs to the gate are the same. If
one but not both inputs are HIGH (1), a LOW output (0) results.
Behavioral code for XOR gate:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity norgate is
port(a,b:in bit;
x:out bit);
end norgate;
architecture behav of norgate is
begin
p1:process(a,b)
begin
if a='0' and b='0'
then x<='1';
elsif a='0' and b='1'
then x<='0';
elsif a='1' and b='0'
then x<='0';
else x<='0';
end if;
end process p1;
end behav;

OUTPUT WAVEFORM
NAND GATE:

NAND gates are one of the two basic logic gates (along with NOR gates) from
which any other logic gates can be built. Due to this property, NAND and NOR
gates are sometimes called "universal gates". However, contrary to popular
belief, modern integrated circuits are not constructed exclusively from a single
type of gate. Instead, EDA tools are used to convert the description of a logical
circuit to a netlist of complex gates (standard cells).
Behavioral code for XOR gate:
CODE: library ieee;
use ieee.std_logic_1164.all;
entity nandg is
port(a,b:in bit;z:out bit);
end nandg;
architecture a1 of nandg is
constant nandg_delay: time := 10 ns;
begin
process(a,b)
variable t:bit_vector(0 to 1);
begin
t:=a & b;
case t is
when "00"=>z<='1';
when "01"=>z<='1';
when "10"=>z<='1';
when "11"=>z<='0';
end case;
end process;
end a1;

OUTPUT WAVEFORM