[go: up one dir, main page]
Scribd
Upload
57 views11 pages

Half Adder: Ieee Ieee STD - LOGIC - 1164 Ieee STD - Logic - Arith Ieee STD - Logic - Unsigned

Uploaded by

Uma Shankar

The document describes the design and implementation of several basic digital logic components in VHDL including a half adder, full adder, multiplexer, demultiplexer, decoder, encoder, and multiplier. Each component is defined as an entity with inputs and outputs and the logic is described in the architecture using processes, if statements, and basic logic gates like AND and XOR.

Copyright:

Attribution Non-Commercial (BY-NC)
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt

Half Adder: Ieee Ieee STD - LOGIC - 1164 Ieee STD - Logic - Arith Ieee STD - Logic - Unsigned

Uploaded by

Uma Shankar
57 views11 pages
The document describes the design and implementation of several basic digital logic components in VHDL including a half adder, full adder, multiplexer, demultiplexer, decoder, encoder, and multiplier. Each component is defined as an entity with inputs and outputs and the logic is described in the architecture using processes, if statements, and basic logic gates like AND and XOR.

Original Description:

how to work on vlsi simulation with code and output

Original Title

vlsi rec

Copyright

© Attribution Non-Commercial (BY-NC)

Available Formats

DOCX, PDF, TXT or read online from Scribd

Did you find this document useful?

Is this content inappropriate?

The document describes the design and implementation of several basic digital logic components in VHDL including a half adder, full adder, multiplexer, demultiplexer, decoder, encoder, and multiplier. Each component is defined as an entity with inputs and outputs and the logic is described in the architecture using processes, if statements, and basic logic gates like AND and XOR.

Copyright:

Attribution Non-Commercial (BY-NC)
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
57 views11 pages

Half Adder: Ieee Ieee STD - LOGIC - 1164 Ieee STD - Logic - Arith Ieee STD - Logic - Unsigned

Uploaded by

Uma Shankar
The document describes the design and implementation of several basic digital logic components in VHDL including a half adder, full adder, multiplexer, demultiplexer, decoder, encoder, and multiplier. Each component is defined as an entity with inputs and outputs and the logic is described in the architecture using processes, if statements, and basic logic gates like AND and XOR.

Copyright:

Attribution Non-Commercial (BY-NC)
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
You are on page 1/ 11

HALF ADDER

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ha is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end ha; architecture Behavioral of ha is begin sum<= a xor b; carry<= a and b; end Behavioral;

full adder
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end MUL; architecture Behavioral of FA is begin sum<=a xor b xor cin; carry<=(a and b) or (a and cin) or (b and cin); end Behavioral;

Mux
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX is Port ( a : b : c : d : se1 z : end MUX;

in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; : in STD_LOGIC_VECTOR (1 downto 0); out STD_LOGIC);

architecture Behavioral of MUX is begin process(a,b,c,d,se1) begin if (se1="00") then z<=a; elsif (se1="01") then z<=b; elsif (se1="10") then z<=c; elsif (se1="11") then z<=d; end if; end process;

end Behavioral;

Demux
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DEMUX is Port ( a : in STD_LOGIC; se1 : in STD_LOGIC_vector( 1 downto 0); z : out STD_LOGIC_vector(3 downto 0)); end DEMUX; architecture Behavioral of signal x:std_logic; begin process(a,se1) begin if(se1= "00") then z(0)<=a; z(1)<=x; z(2)<=x; elsif (se1= "01") then z(0)<=x; z(1)<=a; z(2)<=x; elsif (se1= "10") then z(0)<=x; z(1)<=x; z(2)<=a; elsif (se1= "11") then z(0)<=x; z(1)<=x; z(2)<=x; end if; DEMUX is

z(3)<=x; z(3)<=x; z(3)<=x; z(3)<=a;

end process; end Behavioral;

Decoder
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODE is Port ( a : in STD_LOGIC_vector( 2 downto 0); z : out STD_LOGIC_vector( 7 downto 0)); end DECODE; architecture Behavioral of DECODE is begin process(a) begin if(a="000") then z<="00000001"; elsif(a="001") then z<="00000010"; elsif(a="010") then z<="00000100"; elsif(a="011") then z<="00001000"; elsif(a="100") then z<="00010000"; elsif(a="101") then z<="00100000"; elsif(a="110") then z<="01000000"; elsif(a="111") then z<="10000000"; end if; end process; end Behavioral;

Encoder
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODE is

Port ( a : in STD_LOGIC_VECTOR( 7 DOWNTO 0); z : out STD_LOGIC_VECTOR( 2 DOWNTO 0)); end ENCODE; architecture Behavioral of ENCODE is begin process(a) begin if(a="00000001") then z<="000"; elsif(a="00000010") then z<="001"; elsif(a="00000100") then z<="010"; elsif(a="00001000") then z<="011"; elsif(a="00010000") then z<="100"; elsif(a="00100000") then z<="101"; elsif(a="01000000") then z<="110"; elsif(a="10000000") then z<="111"; end if; end process; end Behavioral;

Ouput of multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUL is Port ( x0 : x1 : y0 : y1 :

in in in in

STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;

p0 p1 p2 p3 end MUL;

: : : :

out out out out

STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC);

architecture Behavioral of MUL is component ha port( a :in STD_LOGIC; b :in STD_LOGIC; sum :out STD_LOGIC; carry :out STD_LOGIC); end component ha; component and1 port( a :in STD_LOGIC; b:in STD_LOGIC; c:out STD_LOGIC); end component and1; signal s0,s1,s2,c1:STD_LOGIC; begin h1 :ha port map (s0,s1,p1,c1); h2 :ha port map (c1,s2,p2,p3); g1 :and1 port map (x0,y0,p0); g2 :and1 port map (x1,y0,s0); g3 :and1 port map (x0,y1,s1); g4 :and1 port map (x1,y1,s2); end Behavioral;

You might also like