This document contains VHDL code for several basic digital logic components:
1. An ALU entity that performs arithmetic and logical operations on 4-bit inputs based on a 3-bit control signal.
2. A comparator entity that compares two 2-bit inputs and outputs signals indicating equality, greater than, and less than relations.
3. Asynchronous and synchronous D flip-flop entities.
4. A J-K flip-flop entity.
5. Ripple counter and synchronous counter entities for counting up or down on a clock signal.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
This document contains VHDL code for several basic digital logic components:
1. An ALU entity that performs arithmetic and logical operations on 4-bit inputs based on a 3-bit control signal.
2. A comparator entity that compares two 2-bit inputs and outputs signals indicating equality, greater than, and less than relations.
3. Asynchronous and synchronous D flip-flop entities.
4. A J-K flip-flop entity.
5. Ripple counter and synchronous counter entities for counting up or down on a clock signal.
This document contains VHDL code for several basic digital logic components:
1. An ALU entity that performs arithmetic and logical operations on 4-bit inputs based on a 3-bit control signal.
2. A comparator entity that compares two 2-bit inputs and outputs signals indicating equality, greater than, and less than relations.
3. Asynchronous and synchronous D flip-flop entities.
4. A J-K flip-flop entity.
5. Ripple counter and synchronous counter entities for counting up or down on a clock signal.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
This document contains VHDL code for several basic digital logic components:
1. An ALU entity that performs arithmetic and logical operations on 4-bit inputs based on a 3-bit control signal.
2. A comparator entity that compares two 2-bit inputs and outputs signals indicating equality, greater than, and less than relations.
3. Asynchronous and synchronous D flip-flop entities.
4. A J-K flip-flop entity.
5. Ripple counter and synchronous counter entities for counting up or down on a clock signal.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online from Scribd
Download as doc, pdf, or txt
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1) ALU:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ALU is Port ( S : in std_logic_vector(2 downto 0); A,B : in std_logic_vector(3 downto 0); F : out std_logic_vector(3 downto 0)); end ALU; architecture Behavioral of ALU is begin PROCESS(S,A,B) BEGIN CASE S IS WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN
"000"=> F <="0000"; "001"=> F <=B-A; "010"=> F <=A-B; "011"=> F <=A+B; "100"=> F <=A XOR B; "101"=> F <=A OR B; "110"=> F <=A AND B; OTHERS=> F <="1111";
END CASE; END PROCESS; end Behavioral;
2) Comp :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity comp is Port ( A : in STD_LOGIC_VECTOR(1 downto 0); B : in STD_LOGIC_VECTOR(1 downto 0); AequalB : out STD_LOGIC; AgreaterB : out STD_LOGIC; AlessB : out STD_LOGIC); end comp; architecture Behavioral of comp is begin AequalB<='1' when A=B else '0'; AgreaterB<='1' when A>B else '0'; AlessB<='1' when A<B else '0'; end Behavioral; 3) Dff async :
Port ( data : in STD_LOGIC;
clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end dff_async; architecture Behavioral of dff_async is begin
process(clk,rst) begin if(rst='0')then q<='0'; elsif(clk'event and clk='1')then q<=data; end if; end process; end Behavioral; 4) Dff sync : entity dff_sync is Port ( data : in STD_LOGIC; clk : in STD_LOGIC; rst : in STD_LOGIC; q : out STD_LOGIC); end dff_sync; architecture Behavioral of dff_sync is begin process(clk) begin if(clk'event and clk='1')then if(rst='0')then q<='0'; else q<=data; end if; end if; end process; end Behavioral; 5) Jk ff :
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkflipflop is Port ( CLOCK : in std_logic;
J : in std_logic; K : in std_logic; RESET : in std_logic; Q : out std_logic; QBAR : out std_logic); end jkflipflop; architecture Behavioral of jkflipflop is SIGNAL STATE:STD_LOGIC; SIGNAL INPUT:STD_LOGIC_VECTOR(1 DOWNTO 0); begin INPUT <= J & K; P:PROCESS(CLOCK,RESET)IS BEGIN IF (RESET='1')THEN STATE <='0'; ELSIF(RISING_EDGE(CLOCK))THEN CASE(INPUT) IS WHEN"11" => STATE <= NOT STATE; WHEN"10" => STATE <= '1'; WHEN"01" => STATE <= '0'; WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; Q <=STATE; QBAR <= NOT STATE; end Behavioral; 6) Ripple ounter : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rpp is Port ( clk,reset,set,ud : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end rpp; architecture Behavioral of rpp is begin process(clk,reset,set,ud,q(0),q(1),q(2)) begin
if ud='0' then if reset='0' then q<="0000"; elsif set='0' then q<="1111"; elsif clk='1' and clk'event then q(0) <= not q(0); end if; if q(0)='0' and q(0)'event then q(1) <= not q(1); end if; if q(1)='0' and q(1)'event then q(2) <= not q(2); end if; if q(2)='0' and q(2)'event then q(3) <=not q(3); end if; else if reset='0' then q<="0000";
elsif set='0' then
q<="1111"; elsif clk='1'and clk'event then q(0) <= not q(0); end if; if q(0)='1' and q(0)'event then q(1) <= not q(1); end if; if q(1)='1' and q(1)'event then q(2) <= not q(2); end if; if q(2)='1' and q(2)'event then q(3) <=not q(3); end if; end if; end process; end Behavioral; 7) Sync ounter :
entity sync_counter is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; en : in STD_LOGIC; q : out STD_LOGIC_VECTOR(3 downto 0)); end sync_counter; architecture Behavioral of sync_counter is signal value:STD_LOGIC_VECTOR(3 downto 0); begin process(clk,clr) begin if(clr='1')then value <=(others=>'0'); elsif(clk'event and clk='1')then if en='1' then value<= value + 1 ;
end if; end if; end process; q<=value; end Behavioral;
