The document contains VHDL and Verilog code for several digital logic components including an 8-to-3 encoder, 2-to-4 decoder, 8-to-1 multiplexer, priority encoder, binary to gray converter, 1-to-8 demultiplexer, comparator, and full adder. The full adder is modeled using three styles: dataflow, behavioral, and structural. The last section provides a model for a 32-bit ALU using a schematic diagram for mixed logic operations.
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The document contains VHDL and Verilog code for several digital logic components including an 8-to-3 encoder, 2-to-4 decoder, 8-to-1 multiplexer, priority encoder, binary to gray converter, 1-to-8 demultiplexer, comparator, and full adder. The full adder is modeled using three styles: dataflow, behavioral, and structural. The last section provides a model for a 32-bit ALU using a schematic diagram for mixed logic operations.
The document contains VHDL and Verilog code for several digital logic components including an 8-to-3 encoder, 2-to-4 decoder, 8-to-1 multiplexer, priority encoder, binary to gray converter, 1-to-8 demultiplexer, comparator, and full adder. The full adder is modeled using three styles: dataflow, behavioral, and structural. The last section provides a model for a 32-bit ALU using a schematic diagram for mixed logic operations.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online from Scribd
The document contains VHDL and Verilog code for several digital logic components including an 8-to-3 encoder, 2-to-4 decoder, 8-to-1 multiplexer, priority encoder, binary to gray converter, 1-to-8 demultiplexer, comparator, and full adder. The full adder is modeled using three styles: dataflow, behavioral, and structural. The last section provides a model for a 32-bit ALU using a schematic diagram for mixed logic operations.
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8 to 3 Encoder VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.
ALL; entity encoder8_3 is Port ( reset : in STD_LOGIC; din : in STD_LOGIC_VECTOR (7 downto 0); dout : out STD_LOGIC_VECTOR (2 downto 0)); end encoder8_3; architecture Behavioral of encoder8_3 is begin process(reset,din) begin if (reset='0') then dout<="000"; else case din is when "00000001"=> dout<="000"; when "00000010"=> dout<="001"; when "00000100"=> dout<="010"; when "00001000"=> dout<="011"; when "00010000"=> dout<="100"; when "00100000"=> dout<="101"; when "01000000"=> dout<="110"; when "10000000"=> dout<="111"; when others => dout<="000"; end case; end if; end process; end Behavioral; 2 to 4 Decoder VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder2_4 is Port ( a,b,en : in STD_LOGIC; y0,y1,y2,y3 : out STD_LOGIC); end decoder2_4; architecture Dataflow of decoder2_4 is begin y0<= (not a) and (not b) and en; y1<= (not a) and b and en; y2<= a and (not b) and en; y3<= a and b and en; end Dataflow;
VERILOG CODE module encoder8_3v(din,reset,dout); input [7:0] din; input reset; output [2:0] dout; reg [2:0] dout; always @(din,reset) begin if (reset == 1'b1) dout = 3'b000; else begin case (din) 8'b00000001 : dout=3'b000; 8'b00000010 : dout=3'b001; 8'b00000100 : dout=3'b010; 8'b00001000 : dout=3'b011; 8'b00010000 : dout=3'b100; 8'b00100000 : dout=3'b101; 8'b01000000 : dout=3'b110; 8'b10000000 : dout=3'b111; default : dout=3'b000; endcase end end endmodule
VERILOG CODE module decoder2_4v(reset,din,dout); input reset; input [1:0] din; output [3:0] dout; reg [3:0] dout; always @(reset,din) begin if (reset==1'b1) begin dout=4'b0000; end else begin case(din) 2'b00 : dout=4'b0001; 2'b01 : dout=4'b0010; 2'b10 : dout=4'b0100; 2'b11 : dout=4'b1000; endcase end end endmodule
8 to 1 Mux VHDL Code library IEEE;
VERILOG CODE module mux8_1v(d,reset,sel,y);
use IEEE.STD_LOGIC_1164.ALL; entity mux8_1 is Port ( d : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); reset : in STD_LOGIC; y : out STD_LOGIC); end mux8_1; architecture Behavioral of mux8_1 is begin process (sel,reset,d) is begin if (reset='1')then y <= '0'; else case sel is when "000" => y <= d(0); when "001" => y <= d(1); when "010" => y <= d(2); when "011" => y <= d(3); when "100" => y <= d(4); when "101" => y <= d(5); when "110" => y <= d(6); when "111" => y <= d(7); when others => null; end case; end if; end process; end Behavioral; Priority encoder VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pri_enc is Port ( reset : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end pri_enc; architecture Behavioral of pri_enc is begin process(reset,din) begin if(reset='1')then dout<=(others=>'0'); else if(din(0)='1')then dout<="000"; elsif(din(1)='1')then dout<="001"; elsif(din(2)='1')then dout<="010"; elsif(din(3)='1')then dout<="011"; elsif(din(4)='1')then dout<="100"; elsif(din(5)='1')then dout<="101"; elsif(din(6)='1')then dout<="110";
input [7:0] d; input reset; input [2:0] sel; output y; reg y; always@(reset,sel,d) begin if(reset==1) y = 1'b0; else begin case(sel) 3'd0 : y = d[0]; 3'd1 : y = d[1]; 3'd2 : y = d[2]; 3'd3 : y = d[3]; 3'd4 : y = d[4]; 3'd5 : y = d[5]; 3'd6 : y = d[6]; 3'd7 : y = d[7]; endcase end end endmodule
elsif(din(7)='1')then dout<="111"; else dout<="000"; end if; end if; end process; end Behavioral;
4 bit binary to gray converter VHDL Code
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binarytogray is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end binarytogray; architecture Behavioral of binarytogray is begin process(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process; end Behavioral;
1:8 DEMULTIPLEXER VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux1X8 is Port ( y : in std_logic; reset : in std_logic; sel : in std_logic_vector(2 downto 0); d : out std_logic_vector(7 downto 0)); end demux1X8; architecture Behavioral of demux1X8 is begin process(reset,y,sel) begin if(reset=1)then d<=(others=>0); else case sel is when "000" => d(0) <= y ; when "001" => d(1) <= y ; when "010" => d(2) <= y ; when "011" => d(3) <= y ; when "100" => d(4) <= y ; when "101" => d(5) <= y ; when "110" => d(6) <= y ; when "111" => d(7) <= y ; when others => null; end case; end if; end process; end Behavioral; COMPARATOR VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( reset : in std_logic; a : in std_logic_vector(1 downto 0); b : in std_logic_vector(1 downto 0); aeqb,agtb,altb : out std_logic); end comp; architecture Behavioral of comp is begin process(reset,a,b) variable t1,t2,t3:std_logic; begin if(reset='1')then t1:='0'; t2:='0'; t3:='0'; else if(a=b)then t1:='1'; t2:='0'; t3:='0'; elsif(a>b)then t1:='0';
VERILOG module demux1_8(reset,y,sel,d); input y; input reset; input [2:0] sel; output [7:0] d; reg [7:0] d; always@(sel,y,reset) begin if(reset==1b1) d=8b00000000; else begin case (sel) 3'b000 : d[0] = y ; 3'b001 : d[1] = y ; 3'b010 : d[2] = y ; 3'b011 : d[3] = y ; 3'b100 : d[4] = y ; 3'b101 : d[5] = y ; 3'b110 : d[6] = y ; 3'b111 : d[7] = y ; default :begin end endcase end end endmodule
VERILOG module comparator(a,b,en,aeqb,agtb,altb); input [1:0] a; input [1:0] b; input en; output aeqb; output agtb; output altb; reg aeqb,agtb,altb; always @(a,b,en) begin if (en==1) if(a==b) begin aeqb=1; agtb=0; altb=0; end else if(a>b) begin aeqb=0; agtb=1; altb=0; end else begin aeqb=0;
t2:='1'; t3:='0'; else t1:='0'; t2:='0'; t3:='1'; end if; end if; aeqb<=t1; agtb<=t2; altb<=t3; end process; end Behavioral;
agtb=0; altb=1; end else begin aeqb=0; agtb=0; altb=0; end end endmodule
3. Write a HDL code to describe the functions of a Full Adder Using three modeling styles. DATA FLOW DESCRIPTION VHDL VERILOG library IEEE; module FullAdder(a,b,cin,sum,cout); use IEEE.STD_LOGIC_1164.ALL; input a,b,cin; use IEEE.STD_LOGIC_ARITH.ALL; output sum,cout; use IEEE.STD_LOGIC_UNSIGNED.ALL; assign sum = a ^ b ^ cin ; entity FullAdder is assign cout = (a & b) | (b & cin) | (cin & a); Port ( a,b,cin : in std_logic; endmodule sum,cout : out std_logic); end FullAdder; architecture dtfl of FullAdder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (cin and a); end dtfl; BEHAVIORAL DESCRIPTION VHDL VERILOG module fulladd(a,b,cin,sum,cout); library IEEE; input a,b,cin; use IEEE.STD_LOGIC_1164.ALL; output sum,cout; use IEEE.STD_LOGIC_ARITH.ALL; reg sum,cout; use IEEE.STD_LOGIC_UNSIGNED.ALL; always@(a,b,cin) entity Seq_Full is begin Port ( A : in std_logic; if(a==1'b0 & b==1'b0 & cin==1'b0) B : in std_logic; begin Cin : in std_logic; sum=1'b0; Sum : out std_logic; cout=1'b0; Cout : out std_logic); end else if(a==1'b0 & b==1'b0 & cin==1'b1) end Seq_Full; begin architecture Behavioral of Seq_Full is sum=1'b1; begin cout=1'b0; process(A,B,Cin) end begin else if(a==1'b0 & b==1'b1 & cin==1'b0) if(A='0' and B='0' and Cin='0')then begin Sum<='0'; sum=1'b1; Cout<='0'; cout=1'b0; elsif(A='0' and B='0' and Cin='1')then end Sum<='1'; else if(a==1'b0 & b==1'b1 & cin==1'b1) begin Cout<='0'; sum=1'b0; elsif(A='0' and B='1' and Cin='0')then cout=1'b1; Sum<='1'; end Cout<='0'; else if(a==1'b1 & b==1'b0 & cin==1'b0) elsif(A='0' and B='1' and Cin='1')then begin Sum<='0'; sum=1'b1; Cout<='1'; cout=1'b0; elsif(A='1' and B='0' and Cin='0')then end Sum<='1'; else if(a==1'b1 & b==1'b0 & cin==1'b1)
Cout<='0'; elsif(A='1' and B='0' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='0')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='1')then Sum<='1'; Cout<='1'; end if; end process; end Behavioral; STRUCTURAL DESCRIPTION
begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b0) begin sum=1'b0; cout=1'b1; end else if(a==1'b1 & b==1'b1 & cin==1'b1) begin sum=1'b1; cout=1'b1; end end endmodule
4. Write a model for 32 bit ALU using the schematic diagram shown below VHDL VERILOG library IEEE; module ALU_MIXED(a,b,opcode,enable,y); use IEEE.STD_LOGIC_1164.ALL; input [3:0] a,b; use IEEE.STD_LOGIC_ARITH.ALL; input [3:0] opcode; use IEEE.STD_LOGIC_UNSIGNED.ALL; input enable; entity ALU is output [7:0] y; Port ( a,b : in std_logic_vector(3 downto 0); reg [7:0] y; opcode : in std_logic_vector(3 downto 0); always@(a,b,enable,opcode) enable : in std_logic; begin y : out std_logic_vector(7 downto 0)); if(enable==1'b1) end ALU; begin architecture Behavioral of ALU is case (opcode) begin 4'b0001 : y = a + b; process(enable,a,b,opcode) 4'b0010 : y = a - b; begin 4'b0011 : y = ~ a; if(enable='1')then 4'b0100 : y = a * b; case opcode is 4'b0101 : y = a & b; when "0001" => y <= "000" & (('0'& a) + ('0' & b)); 4'b0110 : y = a | b; when "0010" => y <= "000" & (('0' & a)-('0' & b)); 4'b0111 : y = ~(a & b); when "0011" => y <= "0000" & (not a); 4'b1000 : y = a ^ b; when "0100" => y <= a * b; default: y=8'd0; when "0101" => y <= "0000" & (a and b); endcase when "0110" => y <= "0000" & (a or b); end when "0111" => y <= "0000" & (a nand b); else when "1000" => y <= "0000" & (a xor b); begin when others => y <= (others=>'0'); y=8'd0; end case; end else end y <= (others=>'0'); endmodule end if; end process; end Behavioral;
