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WO2008114508A1 - データ受信回路それを利用した試験装置ならびにストローブ信号のタイミング調節回路、方法 - Google Patents

データ受信回路それを利用した試験装置ならびにストローブ信号のタイミング調節回路、方法 Download PDF

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Publication number
WO2008114508A1
WO2008114508A1 PCT/JP2008/000633 JP2008000633W WO2008114508A1 WO 2008114508 A1 WO2008114508 A1 WO 2008114508A1 JP 2008000633 W JP2008000633 W JP 2008000633W WO 2008114508 A1 WO2008114508 A1 WO 2008114508A1
Authority
WO
WIPO (PCT)
Prior art keywords
strobe signal
circuit
delay
tester
same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/000633
Other languages
English (en)
French (fr)
Inventor
Daisuke Watanabe
Toshiyuki Okayasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to US12/532,134 priority Critical patent/US8270225B2/en
Priority to JP2009505080A priority patent/JP5153766B2/ja
Priority to EP08720518A priority patent/EP2136218A1/en
Publication of WO2008114508A1 publication Critical patent/WO2008114508A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

　可変遅延回路４２は、ストローブ信号Ｓ５に調節可能な遅延を与える。入力ラッチ回路１４は、可変遅延回路４２により遅延されたストローブ信号Ｓ６により、内部シリアルデータＳ２に含まれる各ビットデータをラッチする。遅延設定部４０は、可変遅延回路４２によりストローブ信号Ｓ５に与える遅延量τ１を調節する。遅延設定部４０は、シリアルデータとして既知のキャリブレーションパターンを入力するキャリブレーション動作時に、入力ラッチ回路１４の出力ラッチデータＳ３を統計的に取得し、１と０の出現確率が所定の割合となるように、遅延量τ１を調節する。
PCT/JP2008/000633 2007-03-22 2008-03-18 データ受信回路それを利用した試験装置ならびにストローブ信号のタイミング調節回路、方法 Ceased WO2008114508A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/532,134 US8270225B2 (en) 2007-03-22 2008-03-18 Data receiving circuit
JP2009505080A JP5153766B2 (ja) 2007-03-22 2008-03-18 データ受信回路それを利用した試験装置
EP08720518A EP2136218A1 (en) 2007-03-22 2008-03-18 Data receiving circuit, tester using same, and timing adjusting circuit for strobe signal and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007074731 2007-03-22
JP2007-074731 2007-03-22

Publications (1)

Publication Number Publication Date
WO2008114508A1 true WO2008114508A1 (ja) 2008-09-25

Family

ID=39765626

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000633 Ceased WO2008114508A1 (ja) 2007-03-22 2008-03-18 データ受信回路それを利用した試験装置ならびにストローブ信号のタイミング調節回路、方法

Country Status (7)

Country Link
US (1) US8270225B2 (ja)
EP (1) EP2136218A1 (ja)
JP (1) JP5153766B2 (ja)
KR (1) KR101265915B1 (ja)
CN (1) CN101641605A (ja)
TW (1) TWI365299B (ja)
WO (1) WO2008114508A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010137058A1 (ja) * 2009-05-25 2010-12-02 株式会社アドバンテスト 受信装置、試験装置、受信方法および試験方法
JP2010286413A (ja) * 2009-06-12 2010-12-24 Advantest Corp 試験装置およびストローブ信号のタイミング調整方法
WO2011061796A1 (ja) * 2009-11-18 2011-05-26 株式会社アドバンテスト 受信装置、試験装置、受信方法、および試験方法
WO2012152251A1 (de) 2011-05-11 2012-11-15 Fachhochschule Kiel Beschichtung für polymere

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014109453A (ja) * 2012-11-30 2014-06-12 Renesas Electronics Corp 半導体装置
US20150033062A1 (en) * 2013-07-26 2015-01-29 Mediatek Inc. Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition
KR20150090486A (ko) * 2014-01-29 2015-08-06 에스케이하이닉스 주식회사 반도체 테스트 장치
US9583160B1 (en) 2015-09-04 2017-02-28 Micron Technology, Inc. Apparatuses including multiple read modes and methods for same
CN106026992B (zh) * 2016-05-06 2018-11-06 武汉航空仪表有限责任公司 一种可变延时脉冲序列输出电路
CN113820612B (zh) * 2020-06-19 2022-12-27 大唐恩智浦半导体有限公司 误差补偿电路和测量电池阻抗的集成电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0262983A (ja) 1988-08-29 1990-03-02 Advantest Corp 位相補正装置
JPH10319089A (ja) * 1997-05-21 1998-12-04 Advantest Corp 半導体試験装置
JP2001133485A (ja) * 1999-09-10 2001-05-18 Agilent Technol Inc 高データ伝送速度の信号内のビットパターンのための等価時間捕捉機構
JP2003057320A (ja) * 2001-08-10 2003-02-26 Advantest Corp タイミング測定方法及び半導体試験装置
JP2006333489A (ja) * 2005-05-25 2006-12-07 Toshiba Corp 位相同期ループ回路のロック検出のためのシステム及び方法
JP2007017257A (ja) 2005-07-07 2007-01-25 Advantest Corp 半導体試験装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3574728B2 (ja) * 1996-06-14 2004-10-06 株式会社アドバンテスト 半導体デバイス試験装置
US7401272B1 (en) * 2001-03-09 2008-07-15 Pmc-Sierra, Inc. Apparatus and method for high speed sampling or testing of data signals using automated testing equipment
EP1880504B1 (en) * 2005-05-02 2012-12-12 Partners for Corporate Research International Receiver with adaptive strobe offset adjustment
US7743304B2 (en) * 2006-02-17 2010-06-22 Verigy (Singapore) Pte. Ltd. Test system and method for testing electronic devices using a pipelined testing architecture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0262983A (ja) 1988-08-29 1990-03-02 Advantest Corp 位相補正装置
JPH10319089A (ja) * 1997-05-21 1998-12-04 Advantest Corp 半導体試験装置
JP2001133485A (ja) * 1999-09-10 2001-05-18 Agilent Technol Inc 高データ伝送速度の信号内のビットパターンのための等価時間捕捉機構
JP2003057320A (ja) * 2001-08-10 2003-02-26 Advantest Corp タイミング測定方法及び半導体試験装置
JP2006333489A (ja) * 2005-05-25 2006-12-07 Toshiba Corp 位相同期ループ回路のロック検出のためのシステム及び方法
JP2007017257A (ja) 2005-07-07 2007-01-25 Advantest Corp 半導体試験装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010137058A1 (ja) * 2009-05-25 2010-12-02 株式会社アドバンテスト 受信装置、試験装置、受信方法および試験方法
CN102422173A (zh) * 2009-05-25 2012-04-18 爱德万测试株式会社 接收装置、测试装置、接收方法及测试方法
JP5314755B2 (ja) * 2009-05-25 2013-10-16 株式会社アドバンテスト 受信装置、試験装置、受信方法および試験方法
JP2010286413A (ja) * 2009-06-12 2010-12-24 Advantest Corp 試験装置およびストローブ信号のタイミング調整方法
WO2011061796A1 (ja) * 2009-11-18 2011-05-26 株式会社アドバンテスト 受信装置、試験装置、受信方法、および試験方法
JP4714306B1 (ja) * 2009-11-18 2011-06-29 株式会社アドバンテスト 受信装置、試験装置、受信方法、および試験方法
US8604773B2 (en) 2009-11-18 2013-12-10 Advantest Corporation Receiving apparatus, test apparatus, receiving method, and test method
WO2012152251A1 (de) 2011-05-11 2012-11-15 Fachhochschule Kiel Beschichtung für polymere

Also Published As

Publication number Publication date
JPWO2008114508A1 (ja) 2010-07-01
US20100128538A1 (en) 2010-05-27
CN101641605A (zh) 2010-02-03
EP2136218A1 (en) 2009-12-23
KR20090130391A (ko) 2009-12-23
JP5153766B2 (ja) 2013-02-27
KR101265915B1 (ko) 2013-05-20
US8270225B2 (en) 2012-09-18
TW200900716A (en) 2009-01-01
TWI365299B (en) 2012-06-01

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