TWI754478B - Pixel circuit - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit includes a first and second light emitting diodes, a first and second switches, a first and second transistors, a reset compensation circuit, a first and second pulse-width modulation circuits. The first and second switches receive an emitting signal to drive the first and second light emitting diodes, respectively. The first transistor is serially connected to the first light emitting diode and the first switch. The second transistor is serially connected to the second light emitting diode and the second switch. The reset compensation circuit is coupled to gates of the first and second transistors. The first and second pulse-width modulation circuits are respectively coupled to gates of the first and second transistors. The first and second pulse-width modulation circuits respectively adjust display time lengths of the first and second light emitting diodes according to the first and second data signals.

Description

pixel circuit

The present invention relates to a circuit, and more particularly, to a pixel circuit.

In a traditional pixel circuit, the light-emitting diode is driven to emit light by a current provided by a series-connected transistor, and the transistor can be controlled by a data signal to adjust the current, thereby adjusting the display brightness of the light-emitting diode. However, the swing of the data signal often causes one or more transistors in the pixel circuit to deviate from the preset operating voltage level, which leads to a difference between the display brightness of the light-emitting diode and the display brightness corresponding to the data signal. deviation.

In order to improve the pixel circuit, a common practice is to increase the voltage difference between the operating voltage of the pixel circuit and the ground voltage, thereby improving the voltage headroom of the pixel circuit. However, the increased operating voltage will increase the power consumption of the pixel circuit, which is not conducive to the application of the pixel circuit.

The present invention provides a pixel circuit which utilizes data signals to adjust pixels The length of time the circuit is displayed.

The pixel circuit of the present invention includes a first light-emitting diode and a second light-emitting diode, a first switch and a second switch, a first transistor and a second transistor, a reset compensation circuit, a first pulse width modulation circuit and a second pulse width modulation circuit. The first switch and the second switch receive the light-emitting signal to drive the first and second light-emitting diodes, respectively. The first transistor is connected in series with the first light emitting diode and the first switch. The second transistor is connected in series with the second light emitting diode and the second switch. The reset compensation circuit is coupled to the control terminal of the first transistor and the control terminal of the second transistor. The first and second pulse width modulation circuits are respectively coupled to the control terminals of the first and second transistors. The first and second pulse width modulation circuits adjust the display time lengths of the first and second light emitting diodes according to the first and second data signals, respectively.

Based on the above, the pixel circuit can effectively avoid the increase in power consumption of the pixel circuit 1 without increasing the voltage range of the pixel circuit. On the other hand, the pixel circuit can reduce the number of circuit elements and signal lines by sharing the reset circuit, thereby reducing the manufacturing cost of the pixel circuit.

1, 2: pixel circuit

3: Display device

10, 11, 20, 21: PWM circuit

12, 22: Reset compensation circuit

C1~C5: Capacitor

D1, D2: light-emitting diodes

dV: voltage difference

EM, EM[n]~EM[n+3]: Lighting signal

N1~N5: Node

S10~S13, S1[n]~S1[n+3], S2, S2[n]~S2[n+3]: Control signal

SW1, SW2: switch

T1, T2, T1~T16: Transistor

TP1~TP5: time interval

V1, V2: Voltage level

Vdata1, Vdata2: data signal

VDD: drive high voltage

Vref1, Vref2: reference voltage

VSS: drive low voltage

Vsweep, Vsweep[n], Vsweep[n+3]: Ramp signal

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

FIG. 2A is a schematic diagram of a pixel circuit of the present invention.

FIG. 2B is a schematic diagram of an operation waveform of a pixel circuit according to an embodiment of the present invention.

FIG. 3 is a partial schematic diagram of a display device according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a pixel circuit 1 according to an embodiment of the present invention. The pixel circuit 1 includes light emitting diodes (LEDs) D1 and D2 , switches SW1 and SW2 , transistors T1 and T2 , pulse width modulation circuits 10 and 11 and a reset compensation circuit 12 . The LED D1, the switch SW1 and the transistor T1 are connected in series between the driving high voltage VDD and the driving low voltage VSS, and the LED D2, the switch SW2 and the transistor T2 are connected in series between the driving high voltage VDD and the driving low voltage VSS. between low voltage VSS. The switches SW1 and SW2 can receive the light-emitting signal EM to drive the light-emitting diodes D1 and D2 respectively. The PWM circuit 10 can control the enabling or disabling of the transistor T1 according to the data signal Vdata1, and the PWM circuit 20 can control the enabling or disabling of the transistor T2 according to the data signal Vdata2. Therefore, the pixel circuit 1 can adjust the display time length of the light emitting diodes through the pulse width modulation circuits 10 and 11 respectively, so as to adjust the gray scale value displayed by the pixel circuit 1 .

In detail, the first end of the light-emitting diode D1 receives the driving high voltage VDD, the first end of the switch SW1 is coupled to the second end of the light-emitting diode D1, and the second end of the switch SW1 is coupled to the first end of the transistor T1 At one end, the second end of the transistor T1 receives the driving low voltage VSS, and the switch SW1 receives the control of the light-emitting signal EM to turn on or off the connection between its first end and the second end. The first end of the light-emitting diode D2 receives the driving high voltage VDD, the first end of the switch SW2 is coupled to the second end of the light-emitting diode D2, the second end of the switch SW2 is coupled to the first end of the transistor T2, and the electrical The second terminal of the transistor T2 receives the driving low voltage VSS, and the switch SW2 receives the control of the light-emitting signal EM to turn on or off the connection between the first terminal and the second terminal. The switches SW1 and SW2 can be based on the luminous signal EM to provide current to drive the light emitting diodes D1 and D2. The transistors T1 and T2 can adjust the display time lengths of the light-emitting diodes D1 and D2 according to the control of the pulse width modulation circuits 10 and 11 .

The light-emitting diodes D1 and D2 can be, for example, but not limited to, organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dots Light emitting diodes (quantum dot, QD, such as QLED, QDLED), fluorescence, phosphor and other suitable materials, and any combination of the above materials.

The pulse width modulation circuit 10 is coupled to the control terminal of the transistor T1 through the reset compensation circuit 12. The pulse width modulation circuit 10 can receive the data signal Vdata1 and perform pulse width modulation according to the voltage value of the data signal Vdata1 ( pulse width modulation), the pulse width modulation circuit 10 controls the on or off of the transistor T1 with the data signal Vdata1 after the pulse width modulation. The pulse width modulation circuit 11 is coupled to the control terminal of the transistor T2. The pulse width modulation circuit 11 can receive the data signal Vdata2 and perform pulse width modulation according to the voltage value of the data signal Vdata2. The pulse width modulation circuit 11 and use the pulse width modulated data signal Vdata2 to control the turn-on or turn-off of the transistor T2. In this way, the PWM circuits 10 and 11 can control the on-times of the transistors T1 and T2 according to the data signals Vdata1 and Vdata2 respectively, and adjust the display time lengths of the light-emitting diodes D1 and D2 accordingly.

Further, the reset compensation circuit 12 is coupled to the control terminals of the transistors T1 and T2 and the pulse width modulation circuit 10 . The reset compensation circuit 12 can reset the voltages of the control terminals of the transistors T1 and T2. In addition, the reset compensation circuit 12 can be used to equalize the transistors T1, The voltage on the control terminal T2 enables the PWM circuits 10 and 11 to be enabled when the transistors T1 and T2 receive the same or similar voltage levels when the control transistors T1 and T2 are enabled. In this way, the currents received by the light-emitting diodes D1 and D2 can be controlled to be the same or similar by the transistors T1 and T2, thereby excluding the voltage deviations received by the transistors T1 and T2 at the control terminals. This results in a brightness error of the light-emitting diodes D1 and D2.

In short, the pixel circuit 1 can respectively control the display time lengths of the light emitting diodes D1 and D2 according to the data signals Vdata1 and Vdata2, so as to adjust the display gray scale value. Therefore, the pixel circuit 1 can effectively avoid the increase in power consumption of the pixel circuit 1 without increasing the voltage headroom of the pixel circuit 1 . On the other hand, the pixel circuit 1 can share the reset circuit 12 , so the number of circuit elements and signal lines in the pixel circuit 1 can be effectively reduced, thereby reducing the manufacturing cost of the pixel circuit 1 .

FIG. 2A is a schematic diagram of a pixel circuit 2 of the present invention. The pixel circuit 2 includes light-emitting diodes D1 and D2 , switches SW1 and SW2 , transistors T1 and T2 , pulse width modulation circuits 20 and 21 and a reset compensation circuit 22 . The LED D1, the switch SW1 and the transistor T1 are connected in series between the driving high voltage VDD and the driving low voltage VSS, and the LED D2, the switch SW2 and the transistor T2 are connected in series between the driving high voltage VDD and the driving low voltage VSS. between low voltage VSS. The pulse width modulation circuit 20 is coupled to the control terminal of the transistor T1 through the reset compensation circuit 22, and the pulse width modulation circuit 21 is coupled to the control terminal of the transistor T2. The reset compensation circuit 22 is coupled to the control terminals of the transistors T1 and T2. Roughly speaking, the PWM circuit 20 can control the transistor according to the data signal Vdata1 The body T1 is turned on or off to adjust the display time length of the light-emitting diode D1. The pulse width modulation circuit 21 can control the turn-on or turn-off of the transistor T2 according to the data signal Vdata2 to adjust the display of the light-emitting diode D2. length of time.

In detail, the switch SW1 may include, for example, a transistor T15, the first end of the transistor T15 is coupled to the second end of the light emitting diode D1, and the second end of the transistor T15 is coupled to the first end of the transistor T1 terminal, the control terminal of the transistor T15 receives the light-emitting signal EM. The switch SW2 may include, for example, a transistor T16, the first end of the transistor T16 is coupled to the second end of the light emitting diode D2, the second end of the transistor T16 is coupled to the first end of the transistor T2, the transistor The control terminal of T16 receives the light-emitting signal EM. In this way, the switches SW1 and SW2 can turn on or off the connection between the first end and the second end of the switches according to the light-emitting signal, so as to provide current to drive the light-emitting diodes D1 and D2.

The pulse width modulation circuit 20 is indirectly coupled to the control terminal of the transistor T1 , and the pulse width modulation circuit 20 is coupled to the control terminal of the transistor T1 through the reset compensation circuit 22 . The PWM circuit 20 can receive the ramp signal Vsweep and the data signal Vdata1, and the PWM circuit 20 can control the transistor T1 to be enabled or disabled according to the ramp signal Vsweep and the data signal Vdata1. The PWM circuit 20 can control the transistor T1 according to the sum of the ramp signal Vsweep and the data signal Vdata1. Therefore, the pulse width modulation circuit 20 can perform pulse width modulation on the data signal Vdata1, control the enabling time of the transistor T1 according to the voltage value of the data signal Vdata1, and then adjust the display time length of the light emitting diode D1.

The pulse width modulation circuit 21 is coupled to the control terminal of the transistor T2. The pulse width modulation circuit 21 receives the ramp signal Vsweep and the data signal Vdata2, and the pulse width modulation circuit 21 The transistor T2 can be controlled to be enabled or disabled according to the ramp signal Vsweep and the data signal Vdata2. The PWM circuit 21 can control the transistor T2 according to the sum of the ramp signal Vsweep and the data signal Vdata2. Therefore, the pulse width modulation circuit 21 can perform pulse width modulation on the data signal Vdata2, control the enabling time of the transistor T2 according to the voltage value of the data signal Vdata2, and then adjust the display time length of the light emitting diode D2.

The reset compensation circuit 22 is coupled to the control terminals of the transistors T1 and T2 and the pulse width modulation circuits 20 and 21 . The reset compensation circuit 22 can reset the voltages of the control terminals of the transistors T1 and T2. In addition, the reset compensation circuit 22 can provide the same or similar voltage value to enable the transistors T1 and T2 when the transistors T1 and T2 are enabled, so that the driving current received by the light-emitting diodes D1 and D2 is The same or similar, thereby eliminating the brightness deviation caused by the voltage difference between the control terminals. Further, the reset compensation circuit 22 can also compensate the voltages provided to the control terminals of the transistors T1 and T2 according to the threshold voltage of the transistor T1, so that the current provided by the compensation transistors T1 and T2 can be avoided from the process of the transistors T1 and T2. affected by variation.

More specifically, the PWM circuit 20 includes transistors T3, T5-T7 and a capacitor C1. The first end of the transistor T3 is coupled to the node N2, the first end of the transistor T3 is indirectly coupled to the control end of the transistor T1 through the node N2, the control end of the transistor T3 is coupled to the node N3, and the second end of the transistor T3 The reference voltage Vref2 is received. The first end of the transistor T5 receives the ramp signal Vsweep, the control end of the transistor T5 receives the control signal S10, and the second end of the transistor T5 is coupled to the node N3 and the control end of the transistor T3. The first end of the transistor T6 is coupled to the node N3, the second end of the transistor T5 and the transistor The control terminal of T3, the control terminal of transistor T6 receives the control signal S11, the first terminal of transistor T7 is coupled to the second terminal of transistor T6, the control terminal of transistor T7 is coupled to the first terminal of transistor T7, The second end of the crystal T7 receives the data signal Vdata1. The first end of the capacitor C1 receives the ramp signal Vsweep, and the second end of the capacitor C1 is coupled to the node N3 and the control end of the transistor T3.

The pulse width modulation circuit 21 includes transistors T4, T8-T10 and a capacitor C2. The first end of the transistor T4 is coupled to the control end of the transistor T2, the control end of the transistor T4 is coupled to the node N5, and the second end of the transistor T4 receives the control signal S2. The first terminal of the transistor T8 receives the ramp signal Vsweep, the control terminal of the transistor T8 receives the control signal S11, and the second terminal of the transistor T8 is coupled to the node N5 and the control terminal of the transistor T4. The first end of the transistor T9 is coupled to the node N5, the second end of the transistor T8 and the control end of the transistor T4, the control end of the transistor T9 receives the control signal S12, and the first end of the transistor T10 is coupled to the transistor T9 The second end of the transistor T10 is coupled to the first end of the transistor T10, and the second end of the transistor T10 receives the data signal Vdata2. The first end of the capacitor C2 receives the ramp signal Vsweep, and the second end of the capacitor C1 is coupled to the node N5 and the control end of the transistor T4.

The reset compensation circuit 22 includes transistors T11 ˜ T14 and capacitors C3 ˜ C5 . The first end of the capacitor C3 receives the driving low voltage VSS, and the second end of the capacitor C3 is coupled to the node N2. The first end of the capacitor C4 is coupled to the second end of the capacitor C3, and the second end of the capacitor C4 is coupled to the control end of the transistor T1. The first terminal of the capacitor C5 is coupled to the control terminal of the transistor T2, and the second terminal of the capacitor C5 is coupled to the second terminal of the transistor T2. The transistor T11 is coupled to the node N2 between the capacitor C3 and the capacitor C4. First Termination of Transistor T11 The reference voltage Vref1 is received, the second terminal of the transistor T11 is coupled to the node N2, and the control terminal of the transistor T11 receives the control signal S13. The first end of the transistor T12 receives the ramp signal Vsweep, the second end of the transistor T12 is coupled to the node N1 and the control end of the transistor T1, and the control end of the transistor T12 receives the control signal S11. The first end of the transistor T13 is coupled to the node N1 and the control end of the transistor T1, the second end of the transistor T13 is coupled to the first end of the transistor T1, and the control end of the transistor T13 receives the control signal S12. The first end of the transistor T14 is coupled to the control end of the transistor T1, the second end of the transistor T14 is coupled to the control end of the transistor T2, and the control end of the transistor T14 receives the control signal S2.

FIG. 2B is a schematic diagram of an operation waveform of the pixel circuit 2 according to an embodiment of the present invention. FIG. 2B shows the voltage waveforms of the control signals S10 ˜ S13 , S2 , the lighting signal EM and the ramp signal Vsweep in the time interval TP1 ˜TP5 . Next, please refer to FIGS. 2A and 2B to understand the following about the pixel circuit 2 operating instructions.

In the time interval TP1, the control signal S10 is a first logic voltage level (eg, a high voltage level), the control signals S11-S13, S2 are a second logic voltage level (eg, a low voltage level), and the light-emitting signal EM is the second logic voltage level (eg, a low voltage level), and the ramp signal Vsweep is the voltage level V1. The voltage levels VN2 and VN3 of the nodes N2 and N3 can be: VN2=Vref2

VN3=V1

The transistor T5 controlled by the control signal S10 can be enabled to be turned on and provide the voltage level V1 to the node N3. Further, the transistor T3 is turned on by being enabled by the voltage level VN3 of the node N3, and provides the reference voltage Vref2 to the node N2.

In the time interval TP2, the control signal S11 is a first logic voltage level (eg, a high voltage level), and the control signals S10, S12, S13, and S2 are a second logic voltage level (eg, a low voltage level), The light-emitting signal EM is a second logic voltage level (eg, a low voltage level), and the ramp signal Vsweep is a voltage level V1. The transistors T6, T9 and T12 controlled by the control signal S11 can be enabled and turned on. The voltage levels VN1, VN2, VN3, VN4, and VN5 of nodes N1, N2, N3, N4, and N5 can be: VN1=VN5=V1

VN2=Vref2

VN3=Vdata1+Vth7

VN4=V2, where V2 is the low voltage level of the control signal S2, and Vth7 is the threshold voltage of the transistor T7. For the node N1, the transistor T12 is enabled and turned on by the control signal S11, so that the ramp signal Vsweep at the voltage level V1 can be provided to the node N1. For the node N3, the transistor T6 can be turned on by the control signal S11, so that the second end of the capacitor C1 is discharged through the transistors T6 and T7 until the voltage difference between the control end and the second end of the transistor T7 is reached The value is equal to the threshold voltage of the transistor T7 itself, so the voltage level VN3 of the node N3 can be equal to the sum of the data signal Vdata1 and the threshold voltage Vth7. Further, the transistor T3 can be turned on by being enabled by the voltage level VN3 of the node N3, and the reference voltage Vref2 is thus provided to the node N2. For the node N5, the transistor T10 is enabled and turned on by the control signal S11, and the voltage level V1 of the ramp signal Vsweep is provided to the node N5. The transistor T4 can be leveled by the voltage level of the node N5 VN5 is enabled and turned on, so that the voltage level V2 of the control signal S2 is supplied to the node N4 through the transistor T4.

Therefore, after the time intervals TP1 and TP2, the terminal voltages of the capacitors C1-C5 can be reset. In addition, the PWM circuit 20 in the PWM circuit 20 can store the voltage information of the data signal Vdata1 and the threshold voltage Vth7 of the transistor T7 at the node N3.

In the time interval TP3, the control signals S12, S2 are the first logic voltage level (eg, the high voltage level), the control signals S10, S11, S13 are the second logic voltage level (eg, the low voltage level), The light-emitting signal EM is a second logic voltage level (eg, a low voltage level), and the ramp signal Vsweep is a voltage level V1. The voltage levels VN1, VN2, VN3, VN4 and VN5 of the nodes N1, N2, N3, N4 and N5 can be: VN1=VN4=VSS+Vth1

VN2=Vref2

VN3=Vdata1+Vth7

VN5=Vdata2+Vth10 wherein Vth1 and Vth10 are the threshold voltages of transistors T1 and T10 respectively. In detail, the voltage levels VN2 and VN3 of the nodes N2 and N3 remain unchanged. For the voltage level VN1 of the node N1, the transistor T13 is enabled by the control signal S12 to be turned on. Since at the beginning of the time interval TP3, the voltage level VN1 of the node N1 is still maintained at the voltage level V1 of the ramp signal Vsweep, and as the transistor T13 is turned on, the voltage level VN1 of the node N1 can also control the transistor T1. is enabled and turned on, so that the node N1 discharges the driving low voltage VSS through the enabled transistors T13 and T1 until the voltage difference between the control terminal and the second terminal of the transistor T1 is equal to the threshold voltage Vth1 of the transistor T1 itself. For the node N4, the transistor T14 of the reset compensation circuit can be turned on by being enabled by the control signal S2, so that the voltage levels VN1 and VN4 of the nodes N1 and N4 are the same or similar voltage levels. For the node N5, the transistor T9 can be turned on by the control signal S12, so that the second end of the capacitor C2 is discharged through the transistors T9 and T10 until the voltage between the control end and the second end of the transistor T10 is reached The difference is equal to the threshold voltage of transistor T10 itself.

Therefore, in the time interval TP3, the pulse modulation circuit 21 can store the voltage data of the data signal Vdata2 and the threshold voltage Vth10 of the transistor T10 at the node N5. On the other hand, the reset compensation circuit 22 can equalize the control terminal voltages of the transistors T1 and T2, and store the threshold voltage Vth1 of the transistor T1 at the nodes N1 and N2.

In the time interval TP4, the control signals S13 and S2 are at the first logic voltage level (for example, a high voltage level), the control signals S10-S12 are at a second logic voltage level (for example, a low voltage level), and the light-emitting signal EM is a second logic voltage level (eg, a low voltage level). After the ramp signal Vsweep can be pulled down by the voltage level V1 by the voltage difference dV, the ramp signal Vsweep gradually increases with a preset slope. The voltage levels VN1, VN2, VN3, VN4, and VN5 of the nodes N1, N2, N3, N4, and N5 may be:

VN2=Vref1

VN3=Vdata1+Vth7-dV

VN5=Vdata2+Vth10-dV where CV4 and CV5 are the capacitance values of capacitors C4 and C5 respectively. For the nodes N1, N2, N4, at the beginning of the time interval TP4, the transistor T14 of the reset compensation circuit 22 remains on. In addition, since the transistors T4, T11 and T12 connecting the nodes N1 and N4 are all disabled and turned off, the capacitors C4 and C5 are connected in series between the reference voltage Vref1 and the driving low voltage VSS, and the capacitors C4 and C5 are connected in series. The nodes N1 and N4 in between are floating. As the control signal S13 enables the transistor T11, the voltage level VN2 of the node N2 changes from the reference voltage Vref2 to the reference voltage Vref1. In this way, the voltage variation of the voltage level VN2 (ie, Vref1 - Vref2 ) also causes charge redistribution at the nodes N1 and N4 coupled between the series capacitors C4 and C5 . For the voltage levels VN3 and VN5 of the nodes N3 and N5, as the ramp signal Vsweep is pulled down by the voltage difference dV, the voltage levels VN3 and VN5 of the nodes N3 and N5 are also pulled down by the same voltage difference dV.

In the time interval TP5, the control signals S10-S13, S2 are the second logic voltage level (eg, the low voltage level), the light-emitting signal EM is the first logic voltage level (eg, the high voltage level), and the ramp signal Vsweep increases with a preset slope.

When the time interval TP5 starts, the switches SW1 and SW2 can be controlled by the light-emitting signal EM to be turned on, and the transistors T1 and T2 can be turned on by the voltage levels VN1 and VN4 respectively. Therefore, the light-emitting diodes D1 and D2 can receive current and display.

Specifically, when the transistor T1 is enabled by the voltage level VN1, the transistor T1 can supply current to emit light by subtracting the threshold voltage Vth1 of the transistor T1 according to the voltage difference between the control terminal voltage and the second terminal. Diode D1. Since node N1 The voltage level VN1 includes the voltage information of the driving low voltage VSS and the threshold voltage Vth1. Therefore, the voltage difference generated by the subtraction of the control terminal voltage of the transistor T1 and the second terminal voltage of the transistor T1 can preferably be After eliminating the voltage information about the driving low voltage VSS, and then subtracting the threshold voltage Vth1 of the transistor T1 from the voltage difference between the control terminal and the second terminal of the transistor T1, the current provided by the transistor T1 can be independent of the driving The low voltage VSS and the threshold voltage Vth1 of the transistor T1 itself. Similarly, the voltage level VN4 of the node N4 also includes the voltage information of the driving low voltage VSS and the threshold voltage Vth1. Therefore, the current provided by the transistor T2 can be independent of the driving low voltage VSS and the threshold voltage Vth2 of the transistor T2 itself, as long as the transistors T1 and T2 are matched transistors. More specifically, the reset compensation circuit 22 can provide compensated voltages to the control terminals of the transistors T1 and T2 to compensate for the voltage drop caused by driving the low voltage VSS against the trace impedance, and to compensate for the process variation. The variation of the threshold voltage Vth2 brought by the crystals T1 and T2 is compensated to eliminate the non-ideal factors when the light-emitting diodes D1 and D2 are displayed.

Then, after the time interval TP5 starts, since the transistor T14 of the reset compensation circuit 22 is disabled and turned off by the control signal S2, the pulse width modulation circuits 20 and 21 control the operation of the control terminal voltages of the transistors T1 and T2. can be independent of each other. The PWM circuit 20 can control when the transistor T1 is disabled and turned off according to the ramp signal Vsweep and the data signal Vdata1. The PWM circuit 21 can control when the transistor T2 is disabled and turned off according to the ramp signal Vsweep and the data signal Vdata2.

For the pulse width modulation circuit 20, the transistor in the pulse width modulation circuit 20 The body T3 is disabled by the voltage level VN3 (that is, VN3=Vdata1+Vth7-dV) at the beginning of the time interval TP5 and is turned off. As the ramp signal Vsweep gradually increases, after the start of the time interval TP5, when the voltage difference between the control terminal and the second terminal of the transistor T3 is greater than or equal to the threshold voltage Vth3 of the transistor T3 itself, the transistor T3 can be switched off. The voltage level VN3 is enabled and turned on, the reference signal Vref2 can be supplied to the node N2 through the transistor T3, so that the first end of the capacitor C4 is changed from the reference voltage Vref1 to the reference voltage Vref2, and the second end of the capacitor C4 generates and The same voltage difference at the first end of the capacitor C4. In this way, corresponding to the conduction of the transistor T3, the transistor T1 can be disabled and turned off by the voltage level VN1, and the display of the light emitting diode D1 is stopped.

Similarly, for the pulse width modulation circuit 21, the transistor T4 in the pulse width modulation circuit 21 is driven by the voltage level VN5 at the beginning of the time interval TP5 (that is, VN5=Vdata2+Vth10-dV) Disabled and terminated. As the ramp signal Vsweep increases, after the start of the time interval TP5, when the voltage difference between the control terminal and the second terminal of the transistor T4 is greater than or equal to the threshold voltage Vth4 of the transistor T4 itself, the transistor T4 can be turned on , the voltage level V2 of the control signal S2 can be supplied to the node N4 through the transistor T4. In this way, corresponding to the conduction of the transistor T4, the transistor T2 can be disabled and turned off by the voltage level VN4, and the display of the light emitting diode D2 is stopped.

More specifically, when the voltage values of the data signals Vdata1 and Vdata2 are relatively high, as the ramp signal Vsweep increases gradually, the transistors T3 and T4 are quickly turned on by the voltage levels VN3 and VN5 to disable the transistor T1. , T2, so that the light-emitting diodes D1 and D2 can respectively have a relatively short display time length. Vice versa, when data When the voltage values of the numbers Vdata1 and Vdata2 are relatively low, the light-emitting diodes D1 and D2 can respectively have a relatively long display time length. In this way, the pulse width modulation circuit 20 can adjust when the transistor T1 is turned on or off according to the voltage value of the data signal Vdata1, thereby adjusting the display time length of the light emitting diode D1. The pulse width modulation circuit 21 can adjust when the transistor T2 is turned on or off according to the voltage value of the data signal Vdata2, thereby adjusting the display time length of the light emitting diode D2. Therefore, the pixel circuit 2 can adjust the grayscale values displayed by the light emitting diodes D1 and D2 by performing pulse width modulation on the data signals Vdata1 and Vdata2.

Overall, the pixel circuit 2 can save the manufacturing cost of the pixel circuit 2 by sharing the reset compensation circuit 22 . The overall structure of the pixel circuit 2 can improve the voltage deviation caused by the wiring impedance, compensate for the threshold voltage of the driving transistor, and avoid the variation of the current or brightness generated by the pixel circuit due to process variation. On the other hand, the pixel circuit 2 can equalize the voltages at the control terminals of the transistors T1 and T2, and the light-emitting diodes D1 and D2 are driven by the same or similar currents, thereby eliminating brightness errors caused by control voltage deviations.

FIG. 3 is a partial schematic diagram of a display device 3 according to an embodiment of the present invention. The display device 3 includes, for example, the pixel circuits 1/2 shown in FIGS. 1 and 2A , and the pixel circuits 1/2 can be arranged in an array in the display device 3 . The display device 3 can provide the control signals S1[n], S2[n], the light-emitting signal EM[n], the ramp signal Vsweep[n] to the pixel circuit 1/2 of the nth row, and the pixel circuit 1/2 can be based on Need to set up the wiring to obtain the required control signals. For details of the operation of the pixel circuit 1/2, please refer to the relevant paragraphs above, and will not be repeated here.

To sum up, each pixel circuit of the present invention may include at least two light-emitting diodes, and the light-emitting diodes may share the reset compensation circuit, thereby reducing the manufacturing cost of the pixel circuit. Through the overall structure of the pixel circuit, the voltage deviation caused by the trace impedance can be improved, and the threshold voltage of the driving transistor can be compensated, so as to avoid the variation of the current or brightness generated by the pixel circuit due to process variation. On the other hand, the pixel circuit can provide an equalized voltage so that the light-emitting diodes are driven by the same or similar current, thereby eliminating the brightness error caused by the deviation of the control voltage.

1: Pixel circuit 10, 11: PWM circuit 12: Reset compensation circuit D1, D2: light-emitting diodes EM: luminous signal SW1, SW2: switch T1, T2: Transistor Vdata1, Vdata2: data signal VDD: drive high voltage VSS: drive low voltage

Claims (9)

A pixel circuit includes: a first light-emitting diode; a first switch receiving a light-emitting signal to drive the first light-emitting diode; a first transistor connected in series with the first light-emitting diode and the first switch; a second light-emitting diode, the first transistor and the second transistor are transistors matched with each other, and the pixel circuit compensates the second transistor with the threshold voltage of the first transistor a threshold voltage of the crystal; a second switch, receiving the light-emitting signal to drive the second light-emitting diode; a second transistor, connected in series with the second light-emitting diode and the second switch; a reset compensation a circuit coupled to the control end of the first transistor and the control end of the second transistor; a first pulse width modulation circuit coupled to the control end of the first transistor through the reset compensation circuit, the A first pulse width modulation circuit adjusts the display time length of the first light emitting diode according to a first data signal; a second pulse width modulation circuit is coupled to the control terminal of the second transistor, the The second pulse width modulation circuit adjusts the display time length of the second light emitting diode according to a second data signal. The pixel circuit of claim 1, wherein the reset compensation circuit conducts between the control terminal of the first transistor and the control terminal of the second transistor to equalize the control terminal of the first transistor and the voltage of the control terminal of the second transistor. The pixel circuit of claim 1, wherein the first PWM circuit controls enabling or disabling of the first transistor according to a sum of a ramp signal and the first data signal, the second The pulse width modulation circuit controls the enabling or disabling of the second transistor according to the sum of the ramp signal and the second data signal. The pixel circuit of claim 1, wherein the first pulse width modulation circuit comprises a third transistor, the first end of which is coupled to the control end of the first transistor through the reset compensation circuit, wherein The second pulse width modulation circuit includes a fourth transistor, the first end of which is coupled to the control end of the second transistor. The pixel circuit of claim 4, wherein the first PWM modulation circuit comprises: a fifth transistor, the first end of which receives a ramp signal, and the second end of the fifth transistor is coupled to The control terminal of the third transistor; a sixth transistor, the first terminal of which is coupled to the control terminal of the third transistor; a seventh transistor, the first terminal of which is coupled to the second terminal of the sixth transistor terminal, the control terminal of the seventh transistor is coupled to the first terminal of the seventh transistor; and a first capacitor, the first terminal of which receives a ramp signal, and the second terminal of the first capacitor is coupled to the third terminal control terminal of the transistor. The pixel circuit of claim 5, wherein the third transistor and the seventh transistor are transistors that match each other, and the first pulse width modulation circuit compensates the seventh transistor with a threshold voltage of the seventh transistor Threshold voltage of the third transistor. The pixel circuit of claim 4, wherein the second PWM modulation circuit comprises: an eighth transistor, the first end of which receives a ramp signal, and the second end of the eighth transistor is coupled to the control terminal of the fourth transistor; a ninth transistor, the first terminal of which is coupled to the control terminal of the fourth transistor; a tenth transistor, the first terminal of which is coupled to the second terminal of the ninth transistor terminal, the control terminal of the tenth transistor is coupled to the first terminal of the tenth transistor; and a second capacitor, the first terminal of which receives a ramp signal, and the second terminal of the second capacitor is coupled to the fourth terminal control terminal of the transistor. The pixel circuit of claim 7, wherein the fourth transistor and the tenth transistor are transistors that match each other, and the second pulse width modulation circuit uses a threshold voltage of the tenth transistor to compensate the Threshold voltage of the fourth transistor. The pixel circuit of claim 1, wherein the reset compensation circuit comprises: a third capacitor, the first end of which receives a driving low voltage; and a fourth capacitor, the first end of which is coupled to the third capacitor The second end, the second end of the fourth capacitor is coupled to the control end of the first transistor; a fifth capacitor, the first end of which is coupled to the control end of the second transistor, the first end of the fifth capacitor Two terminals are coupled to the second terminal of the second transistor; an eleventh transistor is coupled to a node between the third capacitor and the fourth capacitor; a twelfth transistor, the first terminal of which is receiving a ramp signal, the twelfth transistor The second end of the body is coupled to the control end of the first transistor; a thirteenth transistor, the first end of which is coupled to the control end of the first transistor, and the second end of the thirteenth transistor is coupled to a first end of the first transistor; and a fourteenth transistor, the first end of which is coupled to the control end of the first transistor, and the second end of the fourteenth transistor is coupled to the second transistor the control terminal.

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