CN112927651B - A pixel driving circuit, active electroluminescence display and driving method - Google Patents

Abstract

The invention discloses a pixel driving circuit, an active electroluminescent display and a driving method, comprising a light-emitting element; a current source including a driving transistor connected to the light emitting element, the current source supplying a driving current having different amplitudes to the light emitting element according to a voltage applied to a gate terminal of the driving transistor; the current control circuit is connected with the current source and is used for supplying voltages with different levels to the grid terminal of the driving transistor; a PWM generating circuit for generating a PWM pulse signal for controlling the on-time of the light emitting element; the shaping circuit is used for shaping the PWM pulse signal; and a PWM control circuit for obtaining the duration time for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit. The invention inputs the ramp signal after the scanning control signal of each row is input, and can realize larger PWM pulse width.

Description

A pixel driving circuit, active electroluminescence display and driving method

technical field

The invention relates to the field of optoelectronic display, in particular to a pixel driving circuit, an active electroluminescence display and a driving method.

Background technique

Compared with traditional liquid crystal display (LCD) and organic light emitting diode display (OLED), micro light emitting diode (MicroLED) display technology is known for its display advantages of high brightness, high contrast, wide color gamut, long life, and nanosecond response speed. for the ultimate display technology. However, the current Micro LED display technology has encountered some technical challenges, including chip manufacturing, mass transfer, monolithic integration technology, color realization scheme, driver circuit design, etc. Compared with OLED, Micro LED has very steep I-V characteristics, and the luminous efficiency decreases at low current density, and it will cause the problem of color shift of Micro LED under different current driving, so its driving circuit cannot be copied. The drive circuit of OLED needs to be specially designed.

At present, many research teams and companies have published Micro LED display driving solutions, which can be roughly divided into the following categories: passive driving solutions, CMOS active driving solutions and TFT active driving solutions. Passive driving means that the Micro LED does not emit light continuously during the display period of one frame, and its brightness is related to the duty cycle of the column gating during the line scanning period. With the improvement of the display screen resolution, the light-emitting time is getting shorter and shorter. , in order to improve the luminous brightness, the driving current can only be increased, which will increase the power consumption. Therefore, passive driving schemes can only be used on small-sized displays. In contrast, the active driving scheme can make the Micro LED emit light continuously, and CMOS or TFT can control the light emission of each pixel individually, which is suitable for high-resolution and large-scale displays.

Although some people in the prior art have proposed an active drive scheme for Micro LEDs based on PWM (Pulse Width Modulation), for an active digital PWM drive scheme, since the grayscale is represented by the molecular frame method, the The number of shades of gray is limited, and produces false contour problems. For the active analog PWM drive scheme, due to the relatively small slope setting of the ramp control signal, the rise time or fall time of the generated PWM signal is relatively long, which makes the Micro LED display at low gray levels produce color shift, uneven brightness, etc.

Therefore, it is necessary to shape the PWM signal generated by the active analog PWM drive to improve the color and brightness uniformity in the case of low grayscale display.

SUMMARY OF THE INVENTION

In order to overcome the shortcomings and deficiencies of the prior art, the first object of the present invention is to provide a pixel driving circuit for an active electroluminescent display, which can shape the analog PWM pulse signal and ensure the display quality under low gray scale.

The second object of the present invention is to provide a driving method of a pixel driving circuit of an active electroluminescent display.

A third object of the present invention is to provide an active electroluminescent display.

The first purpose of the present invention adopts following technical scheme:

A pixel driving circuit of an active electroluminescent display, comprising:

light-emitting element;

a current source, comprising a drive transistor connected to the light-emitting element, providing drive currents having different amplitudes to the light-emitting element according to a voltage applied to a gate terminal of the drive transistor;

a current control circuit, connected with the current source, for supplying voltages of different levels to the gate terminals of the drive transistors;

A PWM generating circuit is used to generate a PWM pulse signal that controls the on-time of the light-emitting element;

The shaping circuit is used to shape the PWM pulse signal;

The PWM control circuit obtains the duration for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.

Further, the light-emitting element is a light-emitting diode or an organic light-emitting diode.

Further, the PWM generating circuit includes a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor; the drain of the first transistor is connected to the first data signal line, and the source of the first transistor is connected to The first plate of the first capacitor, the gate of the first transistor is connected to the first scan control line; the drain of the second transistor is connected to the high-potential power supply, and the source of the second transistor is connected to the first electrode of the second capacitor plate and the drain of the third transistor, the gate of the second transistor is connected to the first scan control line; the source of the third transistor is connected to the low-potential power supply, and the gate of the third transistor is connected to the first plate of the first capacitor ; The second plate of the first capacitor is connected to the ramp signal data line; the second plate of the second capacitor is connected to the low-potential power supply.

Further, the on-time of the first transistor is set according to the scanning signal of the gate of the first transistor, so as to control the voltage amplitude of the PWM pulse to charge the first capacitor;

The on-time of the second transistor is set according to the scanning signal of the gate of the second transistor, so as to control the voltage amplitude of the PWM pulse to charge the second capacitor;

After the first and second capacitors of all pixels have received data, the second data signal line starts to output a linear rising voltage signal, and loads it to the second plate of the first capacitor. Through the coupling effect of the first capacitor, The voltage of the second plate of the first capacitor rises linearly. When the voltage reaches the threshold voltage V _TH of the third transistor, the voltage of the first plate of the second capacitor will be discharged through the third transistor, thereby generating a PWM pulse signal. .

Further, the PWM shaping circuit includes an inverter and a positive feedback circuit, one end of the positive feedback circuit is connected to the first plate of the second capacitor, the other end is connected to the input end of the inverter, and the output of the inverter is connected The terminal is connected to the PWM control circuit.

Further, the inverter is an N-type transistor, a P-type transistor, or a mixed-integrated transistor of N-type and P-type.

Further, the first transistor, the second transistor and the third transistor are all switching transistors.

Further, the PWM control circuit includes a switching transistor, the gate of the switching transistor is connected to the output part of the inverter of the PWM shaping circuit, the drain is connected to the cathode part of the light-emitting element, and the source is connected to the drain part of the driving transistor.

The invention adopts a pre-charge and re-discharge type PWM generating circuit and a shaping circuit with a positive feedback circuit structure to realize microsecond level PWM rise and fall time control.

The PWM generation circuit pre-charges the storage capacitor to a high level through the upper transistor in the scan programming stage, then the ramp signal voltage rises slowly, and the lower transistor is gradually turned on to gradually discharge to a low level, thereby forming a PWM signal. Since the upper transistor is turned off when the capacitor discharges, the discharge speed is faster than that of the CMOS inverter structure. The shaping circuit shapes the PWM signal through the structure of the inverter and the positive feedback circuit, connects the output part of the inverter to the input part of the positive feedback circuit, accelerates the discharge speed of the capacitor of the PWM generating circuit, and realizes the rise and fall of the microsecond level. time, so as to achieve precise constant current PWM control of the light-emitting element.

The second purpose of the present invention adopts following technical scheme:

A driving method for a pixel driving circuit of an active electroluminescent display, comprising the following stages:

(1) Initialization: The transistor on the PWM generation circuit is turned on by the scan signal, the capacitor is charged, and then turned off to store a high potential on the capacitor.

(2) Data loading stage: the scanning signal controls the transistor to store the data voltage on the capacitor, and then the transistor is turned off to realize the storage of the data voltage. At this stage, the threshold voltage compensation of the drive transistor and the lower transistor of the PWM generation circuit can also be realized through the design of the drive signal. After the data is loaded, the ramp data line sweep begins to input and rises linearly.

(3) The light-emitting element emits light: the second data signal line starts to input a fixed voltage to the gate of the driving transistor, thereby controlling the current flowing in the light-emitting element; the PWM control circuit accepted by the PWM signal controls the duration of the current in the light-emitting element to realize the light-emitting element. of constant current PWM control.

The 3rd purpose of the present invention is to adopt following technical scheme:

An active light-emitting display includes pixel driving circuits arranged in an array.

Beneficial effects of the present invention:

1. The present invention utilizes pure N-type transistors or pure P-type transistors to achieve better PWM generation circuit effects than CMOS structures.

2. The pixel driving circuit of the present invention can realize us-level PWM pulse width control, and can realize the display control under the low gray scale of the light-emitting element.

3. The driving method of the pixel circuit of the active electroluminescence display device of the present invention can adopt the scheme of scanning ramp, that is, the ramp signal is input after the scanning control signal of each row is input, which can realize a larger PWM pulse. width.

Description of drawings

1 is a structural block diagram of a pixel driving circuit of an active electroluminescent display of the present invention;

Fig. 2 is the circuit diagram of Fig. 1;

3 is a schematic diagram of an active electroluminescent display according to Embodiment 1 of the present invention;

4 is a schematic diagram of a pixel driving circuit according to Embodiment 1 of the present invention;

Fig. 5 is the driving timing chart of the circuit of Fig. 4 of the embodiment 1 of the present invention;

6 is a schematic diagram of a pixel driving circuit according to Embodiment 2 of the present invention;

Fig. 7 is the drive timing chart of Fig. 7 of the present invention;

8 is a schematic diagram of an active electroluminescent display according to Embodiment 3 of the present invention;

9 is a schematic diagram of a pixel driving circuit according to Embodiment 3 of the present invention;

Fig. 10 is the driving timing diagram of Fig. 10 of the present invention;

11 is a schematic diagram of an active electroluminescent display according to Embodiment 4 of the present invention;

12 is a schematic diagram of a pixel driving circuit according to Embodiment 4 of the present invention;

FIG. 13 is a driving timing chart of Embodiment 4 of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to the embodiments and the accompanying drawings, but the embodiments of the present invention are not limited thereto.

Example 1

As shown in FIG. 3 , the structure of an active electroluminescent display is basically composed of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba. The pixel array components are connected to the scan lines SCAN arranged in rows, the first data signal lines and the second data signal lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation. Low-potential power supply VSS and high-potential power supply VDD. The first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal, the second data signal line is used to control the output current of the current source, the low-potential power supply VSS is also used for grounding, and the high-potential power supply VDD is used to supply the The pixel provides power supply, the first data signal line is the output of the data input driver DATA, the second data signal line is the output of the data input driver ba, the scan control line is output by the scan driver Scan, and the ramp signal data line sweep generates the ramp data signal.

As shown in FIG. 1 and FIG. 2 , the pixel array component is composed of N×M pixel driving circuits, and the pixel driving circuits include

Light-emitting elements, specifically light-emitting diodes or organic light-emitting diodes

a current source, comprising a drive transistor connected to the light-emitting element, providing drive currents having different amplitudes to the light-emitting element according to a voltage applied to a gate terminal of the drive transistor;

a current control circuit, connected with the current source, for supplying voltages of different levels to the gate terminals of the drive transistors;

A PWM generating circuit is used to generate a PWM pulse signal that controls the on-time of the light-emitting element;

The shaping circuit is used to shape the PWM pulse signal;

The PWM control circuit obtains the duration for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.

In this example 1:

The PWM generating circuit includes a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2 and a third transistor T3; the drain of the first transistor T1 is connected to the first data signal line, and the first transistor The source of T1 is connected to the first plate of the first capacitor C1, the gate of the first transistor T1 is connected to the first scan control line SCAN(N); the drain of the second transistor T2 is connected to the high-potential power supply VDD, the first The source of the second transistor T2 is connected to the first plate of the second capacitor C2 and the drain of the third transistor T3, and the gate of the second transistor T2 is connected to the first scan control line SCAN(N); The source is connected to the low-potential power supply VSS, the gate of the third transistor T3 is connected to the first plate of the first capacitor; the second plate of the first capacitor C2 is connected to the signal data line sweep; the second plate of the second capacitor The plate is connected to the low-potential power supply VSS.

Its working process is:

The on-time of the first transistor is set according to the scanning signal of the gate of the first transistor, so as to control the voltage amplitude of the PWM pulse to charge the first capacitor;

The on-time of the second transistor is set according to the scanning signal of the gate of the second transistor, so as to control the voltage amplitude of the PWM pulse to charge the second capacitor;

After the first and second capacitors of all pixels have received data, the second data signal line starts to output a linear rising voltage signal, and loads it to the second plate of the first capacitor. Through the coupling effect of the first capacitor, The voltage of the second plate of the first capacitor rises linearly. When the voltage reaches the threshold voltage V _TH of the third transistor, the voltage of the first plate of the second capacitor will be discharged through the third transistor, thereby generating a PWM pulse signal. .

The shaping circuit includes an inverter and a positive feedback circuit, and specifically includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9 and a third capacitor C3. The drain of the fourth transistor is connected to the high voltage. The potential power supply VDD is connected, and its source is connected to the gate of the fifth transistor T5 and the first plate of the third capacitor C3 to form point C, and its gate is connected to the second scan control line SCAN(N+1).

The drain of the fifth transistor is connected to the high-potential power supply VDD, and the source of the fifth transistor is connected to the second plate of the third capacitor C3 to form point D, which is connected to the PWM control circuit.

The drain of the sixth transistor is connected to point D, the source of the sixth transistor is connected to the low-potential power supply VSS, the gate of the sixth transistor is connected to the drain of the ninth transistor and is connected to point B, and the source of the second transistor is connected to the third point. The drain of the transistor is connected, and the source of the sixth transistor is connected to the second plate of the second power supply.

The source of the ninth transistor is connected to the low-potential power supply VSS.

The positive feedback circuit is the ninth transistor, and the inverter is the fourth, fifth and sixth transistors and the third capacitor. The main function is to shape the PWM signal to reduce the rise and fall time of the PWM signal.

The shaping circuit may be further configured to, during the period when the second scan control line SCAN(N+1) of the gate terminal of the fourth switching transistor is turned on, use the power supply voltage to adjust the third capacitance of the third capacitor. One terminal charging.

The PWM control circuit only includes a seventh transistor T7, which is used to control the on-off of the current in the light-emitting element, the gate of which is connected to point D, the source is connected to the drain of the eighth transistor, and the drain is connected to the cathode of the light-emitting element. . The current source includes an eighth driving transistor T8, the eighth driving transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.

The current source is an eighth transistor, the current source is a driving transistor, and the other transistors are switching transistors.

The current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the second capacitor first plate and the drain of the ninth transistor, the PWM generation circuit, the shaping circuit Co-acting at the gate terminal of the seventh transistor, the voltage of the first plate of the first capacitor controls the duration of the current of the light-emitting element.

FIG. 5 is a timing chart illustrating a detailed operation of the pixel circuit according to Example Embodiment 1. FIG. Specifically, FIG. 5 shows the scan control lines Scan(n) and Scan(n+1), the data signal V _DATA and the ramp signal data Vsweep applied to the pixel circuit, and the voltage at the gate of the third transistor T3 (point A) , the voltage at the first plate of the second capacitor C2 (point B), the voltage at the gate of the fifth transistor T5 (point C), the voltage at the gate of the seventh transistor T7 (point D), and the driving current Id according to time Variety. Under the control of these control signals and data signals, the pixel circuit has completed four stages of initialization, inverter initialization, data loading and light-emitting element lighting. The detailed operations of the pixel circuit in each stage are as follows:

(1) Initialization: The scan control line Scan(N) of the pixel in the nth row is set to a high level, the scan control line Scan(N+1) is set to a low level, the first transistor T1 and the second transistor T2 are turned on accordingly, and the first transistor T1 and the second transistor T2 are turned on accordingly. The four transistors T4 are turned off; at this time, the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage V _DATA , and the first plate of the second capacitor C2 is configured to the high-level power supply voltage VDD; at this time , the sixth transistor T6 is turned on, the potential of point D is configured as VSS, and the level setting of these points is completed.

(2) Inverter initialization: the scan control line Scan(N+1) of the pixel in the nth row is given a high level, the scan control line Scan(N) is given a low level, the first transistor T1 and the second transistor T2 are turned off, The fourth transistor is turned on accordingly; at this time, the point C of the pixel circuit is configured as the high-level power supply voltage VDD. Since the sixth transistor is always on, the point D is configured as VSS at this stage, so that the third capacitor C3 is two The voltage difference between VDD and VSS is formed at the terminal, and the initialization of the inverter is completed.

(3) Data loading: the scan control lines Scan(N) and Scan(N+1) of the nth row of pixels are both at low level, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off; the Vsweep voltage starts It increases linearly from low level to high level. Due to the capacitive coupling effect of the first capacitor C1, the voltage at point A of the first plate of the first capacitor C1 is V _A =V _DATA +V _sweep -VSS, at point A When the voltage has not reached the threshold voltage VTH of the third transistor T3, the third transistor T3 is partially turned on, so that the potential of point B decreases slowly; at this time, when the potential of point B decreases to the stage of the threshold voltage VTH of the sixth transistor T6, the first The six transistors T6 are gradually turned off, and the voltage at point D is gradually increased. Due to the capacitive coupling effect of the third capacitor C3, the potential at point C rises with the potential at point D, and the fifth transistor T5 is in a better conduction state, thereby accelerating the potential at point D. due to the rise of the potential at point D, the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop to accelerate the rising process of the potential at point D.

(4) The light-emitting element emits light: in the data loading stage, the second data signal line changes from a low potential to a constant input voltage, and the potential at point D changes from a low potential to a high potential to load the gate of the seventh transistor T7, thereby making the first The seven transistors are turned on, so that the light-emitting element, the seventh transistor T7 and the driving eighth transistor T8 form a path, and the second data signal line controls the driving of the eighth transistor T8 to form a constant current in the driving loop.

Example 2

As shown in FIG. 3 , the structure of the active electroluminescent display of the second embodiment basically consists of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba. The pixel array components are all connected to the scan lines SCAN arranged in rows, the first data signal lines and the second signal data lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation. Low-potential power supply VSS and high-potential power supply VDD. The first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal, the second data signal line is used to control the output current of the current source, the low-potential power supply VSS is also used for grounding, and the high-potential power supply VDD is used to supply the The pixel provides the power supply.

The display device of the active electroluminescence display is different from the first embodiment in that the CMOS structure is used as the design of the inverter, which reduces the power consumption of the pixel circuit during operation and achieves the effect of saving energy.

6 is a circuit diagram of the pixel circuit of this example, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 (P-type transistor), a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 , a first capacitor C1, a second capacitor C2, a high-potential power supply line VDD, a second data signal line ba, a low-potential power supply line VSS, a first data signal line DATA, a ramp data signal Vsweep, and a light-emitting element. And the first transistor T1 and the second transistor T2 are in response to the scan control line Scan(n) of the nth row, and the seventh transistor T7 is controlled by the second data signal Vba to output a constant current.

The seventh transistor is a driving transistor.

The PWM generation circuit may include: a first capacitor having a first terminal connected to a gate terminal of the third transistor and a source terminal of the first transistor; and a second capacitor having a drain terminal connected to the third transistor and a first terminal The first terminal of the source terminal of the two transistors.

The PWM generation circuit may be further configured to apply a pulse width control voltage to all of the scan control lines (SCAN(n)) of the nth row of the gate terminals of the first and second transistors during the period when the gate terminals of the first and second transistors are turned on. charging the first capacitor and applying the voltage charged into the first capacitor to the gate terminal of the third transistor; charging the second capacitor with the supply voltage, charging the second capacitor to the same level as the supply voltage same.

The shaping circuit may be composed of an inverter and a positive feedback circuit, including: an eighth transistor having a gate segment connected to the drain terminal of the fourth transistor and the drain terminal of the fifth transistor; and having a gate segment connected to the fourth transistor and the drain terminal of the fifth transistor; The drain terminal of the gate terminal of five transistors; the fourth transistor is a P-type transistor, wherein the inverter is the fourth transistor T4 and the fifth transistor T5, and the positive feedback circuit is the eighth transistor T8.

The PWM control module may include a sixth transistor, the current source module may include a seventh drive transistor, the seventh drive transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.

The current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generation circuit, shaping The circuit cooperates at the gate terminal of the sixth switching transistor to control the duration of the current of the light emitting element by the voltage of the first terminal of the first capacitor.

In this embodiment, the current source is the seventh transistor T7.

FIG. 7 is a timing chart illustrating a detailed operation of the pixel circuit according to Example Embodiment 1. FIG. Specifically, FIG. 7 shows the main control signal Scan(n), the data signal lines DATA and Vsweep applied to the pixel circuit, the voltage at the gate of the third transistor T3 (point A), and the first plate of the second capacitor C2 Variation of the voltage at (point B) and the gate of the sixth transistor T6 (point C) and the driving current I _d as a function of time. Under the control of these control signals and data signals, the pixel circuit has completed three stages of initialization, data loading and light-emitting element lighting. The detailed operations of the pixel circuit in each stage are as follows:

(1) Initialization: The scan control line Scan(n) of the pixel in the nth row is given a high level, and the first transistor T1 and the second transistor T2 are turned on accordingly; at this time, the first plate of the first capacitor C1 of the pixel circuit is turned on. It is set to the data voltage V _DATA , and the first plate of the second capacitor C2 is configured to be the high-level power supply voltage VDD; at this time, the sixth transistor T6 is turned on, and the potential of point C is configured to be VSS, which completes this process. several point level settings.

(2) Data loading: the scan control line Scan(n) of the pixel in the nth row is at a low level, the first transistor T1 and the second transistor T2; the Vsweep voltage begins to increase linearly from a low level to a high level. Due to the capacitive coupling effect of the capacitor C1, the voltage at point A of the first plate of the first capacitor C1 is V _A =V _DATA +V _sweep -VSS, and the voltage at point A has not yet reached the threshold voltage V _TH of the third switching transistor T3 At this time, the third transistor T3 is partially turned on, so that the potential of point B decreases slowly; at this time, when the potential of point B decreases to the stage of the threshold voltage V _TH of the transistor T5, the fifth transistor T5 is gradually turned off. When the threshold voltage _VTH of T4 is reached, the fourth transistor is gradually turned on, and the voltage at point C gradually increases; when the voltage at point C reaches the threshold voltage _VTH of the eighth transistor, the voltage at point B is discharged through the eighth transistor T8, thereby accelerating point B The discharge process of the potential forms a positive feedback loop, which accelerates the rising process of the potential at point C.

(3) The light-emitting element emits light: in the data loading stage, the second data signal line changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the sixth transistor T6, thereby making the first The seven transistors are turned on, so that the light-emitting element, the sixth transistor T6 and the seventh transistor T7 form a path, and the second data signal line controls the seventh transistor T7 to form a constant current in the driving loop.

Example 3

As shown in FIG. 8 , the structure of an active electroluminescent display in Embodiment 3 basically consists of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba. The pixel array components are connected to the scan lines SCAN arranged in rows, the first data signal lines and the second data signal lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation. Low-potential power supply VSS and high-potential power supply VDD. The first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal, the second data signal line is used to control the output current of the current source, the low-potential power supply VSS is also used for grounding, and the high-potential power supply VDD is used to supply the The pixel provides power supply, the first data signal line is the output of the data input driver DATA, the second data signal line is the output of the data input driver ba, the scan control line is output by the scan driver Scan, and the ramp signal data line sweep generates the ramp data signal.

The display device of the active electroluminescence display is different from the first embodiment in that the display device of the electroluminescence display uses a P-type transistor as the design of the inverter, and uses the method of discharging and then charging to avoid phase inversion. The device generates a DC path during operation to reduce power consumption.

FIG. 9 is a circuit diagram showing a pixel array part formed on the display device shown in FIG. 8 . 9, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 (PMOSFET), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a seventh transistor T8, The first capacitor C1, the second capacitor C2, the third capacitor C3, the high-potential power supply line VDD, the second data signal Vba, the low-potential power supply line VSS, the data line DATA, the data line Vsweep, the light-emitting element; and the first transistor T1 and the second transistor T2 responds to the first scan control line Scan1(n) of the nth row, the fifth transistor T5 responds to the second scan control line Scan2(n) of the nth row, and the seventh transistor T7 is controlled by the second data signal Vba and output constant current.

The seventh transistor is a driving transistor.

The PWM generation circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2, the first capacitor having a gate terminal connected to the third transistor and a source of the first transistor a first terminal of the terminal; and a second capacitor having a first terminal connected to the drain terminal of the third transistor and the source terminal of the second transistor.

The PWM generation circuit may be further configured to apply a pulse width control voltage to all the first scan control lines SCAN1(n) in the nth row of the gate terminals of the first and second transistors during the period when the gate terminals of the first and second transistors are turned on. charging the first capacitor and applying the voltage charged into the first capacitor to the gate terminal of the third transistor; charging the second capacitor with the supply voltage, charging the second capacitor to the same level as the supply voltage same.

The shaping circuit may be composed of an inverter and a positive feedback circuit, including: an eighth transistor having a gate segment connected to a drain terminal of the fourth transistor; and a drain terminal having a gate terminal connected to the fourth transistor; Three capacitors with a first terminal connected to the source terminal of the fifth transistor and the gate terminal of the eighth feedback transistor; the fourth and fifth transistors are P-type transistors.

The inverter is a fourth transistor, a fifth transistor and a third capacitor. The positive feedback circuit is the eighth transistor T8.

The shaping circuit may be further configured to, during the period in which the second scan control line SCAN2(n) of the nth row of the gate terminal of the fifth transistor is turned on, use the power supply voltage to adjust the third capacitance of the third capacitor. One plate discharges.

The PWM control module may include a sixth transistor, the current source module may include a seventh drive transistor, the seventh drive transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.

The current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generation circuit and the shaping circuit can be connected. Co-acting at the gate terminal of the sixth transistor, the voltage at the first terminal of the first capacitor controls the duration of the current flow to the light emitting element.

10 is a timing chart illustrating a detailed operation of a pixel circuit according to Example Embodiment 3. FIG. Specifically, FIG. 10 shows the main control signals Scan1(n) and Scan2(n), the data signals V _DATA and Vsweep applied to the pixel circuit, the voltage at the gate of the third transistor T3 (point A), the second capacitor C2 The voltage at the first plate (point B) and the gate of the seventh transistor T7 (point C) and the driving current I _d vary with time. Under the control of these control signals and data signals, the pixel circuit has completed three stages of initialization, data loading and light-emitting element lighting. The detailed operations of the pixel circuit in each stage are as follows:

(1) Initialization: The scan control line Scan1(n) of the pixel in the nth row is set to a high level, and the scan control line Scan2(n) is set to a low level, and the first transistor T1, the second transistor T2 and the fifth transistor T5 are respectively turned on At this time, the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage V _DATA , the first plate of the second capacitor C2 is configured to be the high-level power supply voltage VDD, and the first plate of the third capacitor One plate is configured to be the low-level power supply voltage VSS; at this time, the fourth transistor T4 is turned off, the potential of point C is configured to be VSS, and the level setting is completed.

(2) Data loading: the scan control line Scan1(n) of the pixel in the nth row is at a low level, Scan2(n) is at a high level, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off; Vsweep voltage It starts to increase linearly from low level to high level. Due to the capacitive coupling effect of the first capacitor C1, the voltage at point A of the first plate of the first capacitor C1 is V _A =V _DATA +V _sweep -VSS, at A When the point voltage has not reached the threshold voltage _VTH of the third transistor T3, the third transistor T3 is partially turned on, so that the potential of point B is slowly reduced; at this time, when the potential of point B is reduced to the stage of the threshold voltage _VTH of the switching transistor T4 , the fourth transistor T4 is gradually turned on, and the voltage at point C gradually increases; due to the increase in the potential at point C, the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop to accelerate the potential at point D. ascent process.

(3) The light-emitting element emits light: in the data loading stage, Vba changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the sixth transistor T6, so that the sixth switch transistor conducts The light-emitting element, the sixth transistor T6 and the seventh transistor T7 form a path, and the second data signal _Vba controls the seventh transistor T7 to form a constant current in the driving loop.

Example 4

As shown in FIG. 11 , the general structure of the display device of the active electroluminescent display of the fourth embodiment is shown. The device basically consists of a pixel array part Pixel, a scan driver Scan and a data input driver DATA. The pixel array components are all connected with scan lines Scan arranged in rows, first data signal lines DATA and second data signal lines arranged in columns, the pixel array components also include a plurality of power lines and control signals for providing the pixel Required for operation, a low-level power supply VSS, a high-level power supply VDD, a reference voltage Vref, and a control signal CV. The first data line required for the operation of the pixel is used to control the pulse width of the PWM signal, the second data line acts on the drive transistor to provide a stable current to the light-emitting element, the low-potential power supply VSS is also used for grounding, and the high-potential power supply VDD For supplying power to the pixel, the reference voltage Vref is used for a predetermined potential setting, and the control signal CV is used to separate the compensation phase and the light-emitting phase. The display device of the active electroluminescence display realizes the compensation of the pulse width of the PWM signal and the compensation of the current flowing through the light-emitting element by using the multiplexing of the scan driver, which improves the display uniformity of the display device and reduces the The peripheral drive design of the display device is presented.

FIG. 12 is a circuit diagram showing a pixel array part formed on the display device shown in FIG. 11 . 12, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, first capacitor C1, second Capacitor C2, third capacitor C3, high-potential power supply VDD, second data signal line, low-potential power supply VSS, first data signal line, reference voltage Vref, control signal CV, light-emitting element. And the first transistor and the eleventh transistor respond to the scan control line of the n-1th row, the tenth transistor, the twelfth transistor and the thirteenth transistor respond to the scan control line of the nth row, and the second transistor responds to the scan control line of the nth row. The scan control line of row n+1, the fourth transistor responds to the scan control line of row n+2, the fourteenth transistor, the fifteenth transistor and the sixteenth transistor respond to the control signal CV, and the sixth transistor responds to the th Two data signals V _ba .

The PWM generating circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a first capacitor C1 and a second transistor Capacitor C2: a first capacitor having a first plate connected to the gate terminal of the third transistor and the source of the first transistor and the source of the thirteenth transistor; and a second capacitor having a first plate connected to the second transistor the source and the first plate of the source terminal of the fifteenth transistor; the twelfth transistor with the gate connected to the gate of the thirteenth transistor, and the drain connected to the fourteenth transistor and the third transistor the source of the source.

The PWM generation circuit may be further configured to charge the first capacitor with an initialization voltage during a period when the scan control line SCAN(n-1) of the n-1th row of the gate terminal of the first transistor is turned on , and the voltage charged into the first capacitor is applied to the gate terminal of the third transistor; the nth row scan control line SACN(n) of the gate terminals of the twelfth and thirteenth transistors ) and is turned on, the data voltage is coupled to the first terminal of the first capacitor through the third transistor and the thirteenth transistor; the gate terminal of the second transistor obtains the n+1th row scan control line SCAN(n+ 1) During the conduction period, the first terminal of the second capacitor is charged with the power supply voltage, and the second capacitor is charged to be the same as the power supply voltage; The control signal CV is turned on. And the threshold voltage compensation design can be realized for the third transistor T3.

The shaping circuit may be composed of an inverter and a positive feedback circuit, including: a third capacitor having a first plate connected to the source of the fourth transistor and the gate of the fifth transistor; having a drain connected to the sixth transistor and the second plate of the gate of the ninth transistor; the gate of the sixth transistor is connected to the drain of the ninth feedback transistor.

The inverter includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3. The positive feedback circuit includes a ninth transistor T9.

The shaping circuit may be further configured to apply a power supply voltage to the third capacitor during the period when the scan signal SCAN(n+1) of the n+1th row of the gate terminal of the fourth transistor is turned on. The first terminal is charged.

The PWM control module may include a seventh transistor and a sixteenth transistor, the current source module may include an eighth drive transistor, the eighth drive transistor operates in a saturation region, and the current control circuit may include a fourth capacitor having a connection The first terminal to the source terminal of the eleventh transistor, the drain terminal of the tenth transistor, and the gate terminal of the eighth driving transistor.

The current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the ninth feedback transistor, and the PWM generation circuit and the shaping circuit can be connected. Co-acting at the gate terminal of the seventh transistor, the voltage at the first terminal of the first capacitor controls the duration of the current flow to the light emitting element.

In this embodiment, the current source is the eighth transistor T8, which is specifically a driving transistor.

The current control circuit includes T10, T11, and C4, which can perform threshold voltage compensation design for T8.

FIG. 13 is a timing chart illustrating a detailed operation of a pixel circuit according to Example Embodiment 4. FIG. Specifically, FIG. 13 shows the main control signals (scan control lines) Scan(n-1), Scan(n), Scan(n+1) and Scan(n+2) applied to the pixel circuit, CV, first The data signal line, the second data signal line and Vsweep, the reference voltage Vref, the voltage at the gate of the third transistor T3 (point A), the voltage at the first plate of the second capacitor C2 (point B), the third capacitor C3 The voltage at the first plate (point C), the voltage at the gate of the seventh switching transistor T7 (point D), the voltage at the gate of the eighth transistor T8 (point E), and the change of the driving current I _d according to time. Under the control of these control signals and data signals, the pixel circuit has completed five stages of initialization, threshold voltage compensation stage, light-emitting initialization stage, data loading and light-emitting element lighting. The detailed operation of the pixel circuit in each stage is as follows:

(1) Initialization: The scan control line Scan(n-1) of the n-1th row is given a high level, and the first transistor T1 and the eleventh transistor are turned on accordingly; the scan control line Scan(n) of the nth row, The scan control line Scan(n+1) of the n+1th row and the scan control line Scan(n+2) of the n+2th row are given a low level, the control signal CV is given a low level, the second transistor T2, the first The four transistors T4, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor, the fifteenth transistor T15, and the sixteenth transistor are turned off; point A in the pixel circuit and E points are set as the reference voltage Vref, completing the level reset of points A and E.

(2) Threshold voltage latch stage: the scan control line Scan(n) of the nth row is given a high level, the scan control line Scan(n-1) of the n-1th row, and the scan control line of the n+1th row Scan(n+1), the scan control line Scan(n+2) of the n+2th row is low level, the control signal CV is continuously low level, the tenth transistor T10, the twelfth transistor T12, the thirteenth transistor T12 The transistor T13 is turned on accordingly; the first transistor T1, the second transistor T2, the fourth transistor T4, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned off accordingly; at this time, Point A discharges to V _DATA through the twelfth transistor T12 and the thirteenth transistor T13, until the voltage at point _A is VA =V _DATA +V _{TH_T3} ; point E discharges to VSS through the tenth transistor T10 and the eighth transistor T8, Knowing that the voltage at point _E is VE =V _{TH_T8} , the threshold voltages of the thirteenth transistor T3 and the driving transistor T8 are latched at points A and E, respectively.

(3) Lighting initialization: the scan control line Scan(n+1) of the n+1th row changes from low level to high level, the scan control line Scan(n-1) of the n-1th row, the nth row The scan control line Scan(n) and the scan control line Scan(n+2) of the n+2th row are given a low level, the control signal CV continues to output a low level, the second transistor is turned on accordingly, the first transistor T1, The fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned off accordingly; the potential of point B is configured as high level VDD, so that the sixth transistor T6 is turned on, and point D is configured to be low level; then the scan control line Scan(n+2) of the n+2th row is changed from low level to high level. The n-1th row The scan control line Scan(n-1), the scan control line Scan(n) of the nth row, and the scan control line Scan(n+1) of the n+1th row output a low level, so that the fourth transistor T4 is turned on , the third transistor is turned off, and point C is configured as a high level, thus completing the voltage configuration for the above points.

(4) The scan control line Scan(n-1) of the n-1th row, the scan control line Scan(n) of the nth row, the scan control line Scan(n+1) of the n+1th row, and the n+th row The scan control line Scan(n+2) of the 2 rows outputs a low level, the control signal CV outputs a high level, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the transistors T10-T13 correspond to Turn off, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on accordingly; the Vsweep voltage begins to increase linearly from a low level to a high level. Due to the capacitive coupling effect of the first capacitor C1, the first The voltage at point _A of the first plate of the capacitor C1 is VA =V _DATA +V _{TH_T3} +V _sweep -VSS. When the voltage at point A has not yet reached the threshold voltage V _{TH_T3} of the third transistor T3, the third transistor T3 is partially turned on. turn on, so that the potential of point B slowly decreases; at this time, when the potential of point B decreases to the stage of the threshold voltage V _TH of the sixth transistor T6, the sixth transistor T6 is gradually turned on, and the voltage of point D gradually increases; because the potential of point D rises , the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop to accelerate the rising process of the potential at point D; at this time, the light-emitting time of the light-emitting element is:

It can be ensured that the threshold voltage shift of the third transistor T3 has no influence on the light-emitting time of the light-emitting element.

(5) The light-emitting element emits light: in the data loading stage, Vba changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the seventh transistor T7, so that the seventh transistor is turned on , so that the light-emitting element, the sixteenth transistor T16, the seventh transistor T7 and the eighth transistor T8 form a path, and the second data signal _Vba controls and drives the eighth transistor T8 to form a constant current in the drive loop; the voltage at point E at this time Keep it constant, it is Vba+V _{TH_T8} , so the light-emitting element emits the corresponding brightness, and the current flowing through the light-emitting element is:

Wherein, V _gs is the potential difference between the gate and the source of the eighth transistor T8, μ _n is the carrier mobility of the eighth transistor T8, C _OX is the gate insulating layer capacitance of the eighth transistor T8, W/L is the aspect ratio of the driving transistor T8, _Vba is the data voltage, _Vth is the threshold voltage of the eighth transistor T8, and VDD is the applied power supply voltage. It can be seen from the above formula that the current flowing through the light-emitting element has nothing to do with the threshold voltage V _{th_T8} of the eighth transistor T8 and the turn-on voltage of the light-emitting element, so the pixel circuit can maintain the threshold voltage of the driving transistor and the light-emitting element. The current flowing through the light-emitting element is constant, and it can be ensured that the threshold voltage shift of the third transistor T3 has no effect on the light-emitting time of the light-emitting element.

The above-mentioned embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the described embodiments, and any other changes, modifications, substitutions, and combinations made without departing from the spirit and principle of the present invention , simplification, all should be equivalent replacement modes, and are all included in the protection scope of the present invention.

Claims (8)

1. A pixel drive circuit of an active electroluminescent display, characterized in that, comprising: light-emitting element; a current source, comprising a drive transistor connected to the light-emitting element, providing drive currents having different amplitudes to the light-emitting element according to a voltage applied to a gate terminal of the drive transistor; a current control circuit, connected with the current source, for supplying voltages of different levels to the gate terminals of the drive transistors; A PWM generating circuit is used to generate a PWM pulse signal that controls the on-time of the light-emitting element; The PWM generating circuit includes a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor; the drain of the first transistor is connected to the first data signal line, and the source of the first transistor is connected to the first transistor The first plate of the capacitor, the gate of the first transistor is connected to the first scan control line; the drain of the second transistor is connected to the high-potential power supply, and the source of the second transistor is connected to the first plate of the second capacitor and The drain of the third transistor and the gate of the second transistor are connected to the first scan control line; the source of the third transistor is connected to the low-potential power supply, and the gate of the third transistor is connected to the first plate of the first capacitor; the second plate of the first capacitor is connected to the ramp signal data line; the second plate of the second capacitor is connected to the low-potential power supply; The shaping circuit is used to shape the PWM pulse signal; The shaping circuit includes an inverter and a positive feedback circuit. One end of the positive feedback circuit is connected to the first plate of the second capacitor, and the other end is connected to the output end of the inverter. Connect with PWM control circuit; The PWM control circuit obtains the duration for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit. 2 . The pixel driving circuit according to claim 1 , wherein the light-emitting element is a light-emitting diode or an organic light-emitting diode. 3 . 3. The pixel driving circuit according to claim 1, wherein, Set the on-time of the first transistor according to the scanning signal of the gate of the first transistor, and charge the first capacitor; Set the conduction time of the second transistor according to the scanning signal of the gate of the second transistor, and charge the second capacitor; After the first and second capacitors of all pixels have received data, the ramp signal data line starts to output a linear rising voltage signal, which is loaded on the second plate of the first capacitor, through the coupling effect of the first capacitor, so that The voltage of the first plate of the first capacitor rises linearly. When the voltage reaches the threshold voltage V _TH of the third transistor, the voltage of the first plate of the second capacitor is discharged through the third transistor, thereby generating a PWM pulse signal. 4 . The pixel driving circuit according to claim 1 , wherein the inverter is an N-type transistor, a P-type transistor, or a mixed-integrated transistor of N-type and P-type. 5 . 5 . The pixel driving circuit of claim 1 , wherein the first transistor, the second transistor and the third transistor are all switching transistors. 6 . 6. The pixel driving circuit according to any one of claims 1-4, wherein the PWM control circuit comprises a switching transistor, the gate of the switching transistor is connected to the output part of the inverter of the PWM shaping circuit, and the drain The electrode is connected to the cathode portion of the light-emitting element, and the source electrode is connected to the drain portion of the driving transistor. 7. A driving method for realizing the pixel driving circuit according to any one of claims 1-6, characterized in that, comprising the steps of: (1) Initialization: The scan control line of the pixel in the nth row is given a high level, the first transistor and the second transistor are turned on accordingly, the data voltage is transmitted to the first plate of the first capacitor through the first transistor, and the second capacitor is turned on. The first plate is set to a high level through the second transistor; (2) Data loading stage: the scan control line of the pixel in the nth row is at a low level, and the first transistor and the second transistor are turned off; the ramp signal data line begins to grow linearly from a low level to a high level, due to the first capacitor. The capacitive coupling effect of the first capacitor, the voltage of the first plate of the first capacitor is V _DATA + V _sweep – VSS , Wherein V _DATA is the voltage of the first data signal line, V _sweep is the voltage of the ramp data signal line, and VSS is the low-level power supply voltage. When the voltage has not reached the threshold voltage V _TH of the third transistor, the third transistor is partially turned on, so that The potential of the first plate of the second capacitor decreases slowly; at this time, when the potential decreases to the threshold voltage of the inverter, the output voltage of the inverter gradually increases; the output voltage of the inverter reaches the threshold voltage of the feedback transistor When V _TH , the voltage of the first plate of the second capacitor is discharged through the feedback transistor, thereby accelerating the discharge process of the first plate of the second capacitor, forming a positive feedback loop, and accelerating the rising process of the inverter output potential; (3) The light-emitting element emits light: in the data loading stage, the second data signal line changes from a low potential to a constant input voltage, and the output potential of the inverter changes from a low potential to a high potential to load the gate of the switching transistor of the driving loop, thereby The switching transistor is turned on, so that the light-emitting element, the switching transistor and the driving transistor form a path, and the second data signal line controls the driving transistor to form a constant current in the driving loop. 8 . An active light-emitting display, characterized by comprising the pixel driving circuit according to any one of claims 1 to 6 arranged in an array. 9 .

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