TWI694431B - Pixel circuit and display device - Google Patents

Abstract

A pixel circuit includes a light emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. A first terminal of the driving transistor is configured to receive a power signal, and the second terminal of the driving transistor is electrically coupled to the light emitting diode. The compensation transistor is electrically coupled to the second terminal and a control terminal of the driving transistor, and is turned on or turned off according to a first compensation control signal. The capacitive coupling circuit has a first terminal, a first node, and a second node. The second node is electrically coupled to the control terminal of the driving transistor. A first terminal of the first switch transistor is configured to receive a data signal, and a second terminal of the first switch transistor is electrically coupled to the first node.

Description

Pixel circuit and display device

The present disclosure relates to a pixel circuit and a display device, and particularly to a pixel circuit capable of compensating for the critical voltage variation of driving transistors.

Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has high carrier mobility and small size, suitable for high-resolution, narrow frame and low power consumption display panel. At present, the industry widely uses excimer laser annealing (excimer laser annealing) technology to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel. For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages.

At present, the industry widely uses the technical solution of intra-pixel compensation to overcome the above-mentioned critical voltage variation problem. However, the pixel circuit with the internal pixel compensation function has a complicated circuit structure, which lowers the aperture ratio of the related display panel.

One aspect of the present disclosure is a pixel circuit including a light emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive the power signal, and the second end of the driving transistor is electrically connected to the light emitting diode. The compensation transistor has a first end, a second end and a control end. The second terminal of the compensation transistor is electrically connected to the light-emitting diode, and the control terminal of the compensation transistor is used to receive the first compensation control signal. The capacitive coupling circuit has a first end, a first node and a second node. The first end of the capacitive coupling circuit is electrically connected to the reference voltage source, and the second node of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the first end of the compensation transistor. The first switching transistor has a first end, a second end and a control end. The first end of the first switching transistor is used to receive the data signal, and the second end of the first switching transistor is electrically connected to the first node. The control terminal of the first switching transistor is used to receive the gate signal.

Another aspect of this disclosure is a pixel circuit. The pixel circuit includes a light-emitting diode, a driving transistor, a compensation transistor, and a capacitive coupling circuit. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive the power signal, the second end of the driving transistor is electrically connected to the light emitting diode, and the control end of the driving transistor is used to receive the driving voltage to output the power signal according to the driving voltage to emit light Diode. During a reset period, the driving transistor is turned off, so that the voltage on the light emitting diode is discharged. The compensation transistor is used to selectively turn on the control terminal and the second terminal of the driving transistor according to the first compensation signal. The capacitive coupling circuit has a first node and a second node. During the compensation period, the first node of the capacitive coupling circuit is used to receive the data signal, and the second node of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor. When the first node of the capacitive coupling circuit receives the data signal, the voltage level of the driving voltage changes according to the change in the voltage level of the data signal.

Another aspect of the disclosure is a display device. The display device includes a plurality of gate lines, a plurality of data lines, a first compensation control line, and a plurality of pixel circuits. The gate lines are used to transmit a gate signal respectively. The data lines are used to transmit a data signal respectively. The first compensation control line is used to transmit a first compensation control signal. The pixel circuits are arranged in an array shape, and at least one of the pixel circuits includes: a light-emitting diode, a driving transistor, a compensation transistor, a capacitive coupling circuit, and a first switching transistor. The driving transistor has a first end, a second end and a control end. The first end of the driving transistor is used to receive a power signal, and the second end of the driving transistor is electrically connected to the light emitting diode. The compensation transistor has a first end, a second end and a control end. The second end of the compensation transistor is electrically connected to the light-emitting diode, and the control end of the compensation transistor is electrically connected to the first compensation control line for receiving The first compensation control signal. The capacitive coupling circuit has a first terminal, a first node and a second terminal. The first terminal of the capacitive coupling circuit is electrically connected to the reference voltage source, and the second terminal of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the compensation circuit The first end of the crystal. The first switching transistor has a first end, a second end and a control end. The first end of the first switching transistor is electrically connected to one of the data lines for receiving data signals. The second terminal of the first switching transistor is electrically connected to the first node, and the control terminal of the first switching transistor is electrically connected to one of the gate lines to receive the gate signal.

The pixel circuit and the display device of the present disclosure can compensate the control terminal of the driving transistor through the capacitive coupling effect between multiple capacitors in the capacitive coupling circuit to overcome the problem of the critical voltage variation of the driving transistor, and make The pixel circuit has a simplified circuit architecture.

100‧‧‧Pixel circuit

110‧‧‧ LED

120‧‧‧Capacitive coupling circuit

200‧‧‧Display device

201‧‧‧Display area

202‧‧‧non-display area

210‧‧‧Source Driver

220‧‧‧Gate driver

230‧‧‧ Compensation circuit

T1‧‧‧Drive transistor

T2‧‧‧Compensation transistor

T3‧‧‧ First switching transistor

T4‧‧‧second switching transistor

C1‧‧‧ First capacitor

C2‧‧‧Second capacitor

Id‧‧‧Drive current

S1‧‧‧First compensation control signal

S2‧‧‧Second compensation control signal

S3‧‧‧Gate signal

Vdd‧‧‧power signal

Vddl‧‧‧First low level voltage

VL‧‧‧Second low level voltage

Vssl‧‧‧third lowest level voltage

Vddh‧‧‧Highest level voltage

Vssh‧‧‧second highest level voltage

Vref‧‧‧reference level voltage

Vdata‧‧‧Data signal

Vin‧‧‧Input voltage

Vss‧‧‧reference voltage source

A‧‧‧First node

B‧‧‧The second node

P1‧‧‧ reset period

P2‧‧‧ Compensation period

P3‧‧‧Data writing period

P4‧‧‧ during light

FIG. 1 is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure.

FIG. 2 is an operation timing diagram of a pixel circuit according to some embodiments of the present disclosure.

FIGS. 3A to 3D are schematic diagrams of pixel circuits in different operation timings in some embodiments of the present disclosure.

FIGS. 4A to 4D are schematic diagrams of pixel circuits in different operation timings in some embodiments of the present disclosure.

FIG. 5 is an operation timing diagram of a pixel circuit according to some embodiments of the present disclosure.

FIG. 6 is a schematic diagram of a display device according to some embodiments of the present disclosure.

In the following, a plurality of embodiments of the case will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the case. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

In this article, when an element is referred to as "connected" or "coupled", it can be referred to as "electrically connected" or "electrically coupled." "Connected" or "coupled" can also be used to indicate that two or more components interact or interact with each other. In addition, although terms such as "first", "second", etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly dictates, the term does not specifically refer to or imply order or order, nor is it intended to limit the present invention.

Please refer to FIG. 1, which is a schematic diagram of a pixel circuit 100 according to some embodiments of the present disclosure. The pixel circuit 100 includes a light-emitting diode 110, a driving transistor T1, a compensation transistor T2, a capacitive coupling circuit 120, and a first switching transistor T3. The driving transistor T1 has a first end, a second end and a control end, wherein the first end of the driving transistor T1 is used to receive the power signal Vdd, and the second end of the driving transistor T1 is electrically connected to the light emitting diode 110 .

In this embodiment, the compensation transistor T2 has a first end, a second end, and a control end, wherein the second end of the compensation transistor T2 is electrically connected to the light emitting diode 110, and the control end of the compensation transistor T2 is It is used to receive the first compensation control signal S1. In addition, the capacitive coupling circuit 120 has a first terminal, a first node A, and a second node B, wherein the first terminal of the capacitive coupling circuit 120 is electrically connected to the reference voltage source Vss, and the second node B of the capacitive coupling circuit 120 is electrically It is connected to the control terminal of the driving transistor T1 and the first terminal of the compensation transistor T2.

In this embodiment, the first switching transistor T3 has a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switching transistor T3 is used to receive the data signal Vdata, and the first switching transistor T3 The second terminal is electrically connected to the first node A, and the control terminal of the first switching transistor T3 is used to receive the gate signal S3. In this embodiment, the gate signal S3 is used to control the on or off of the first switching transistor T3.

In the circuit architecture of the foregoing embodiment, the pixel circuit 100 can advance the voltage value of the first node A during the reset period, and utilize the capacitive coupling effect of multiple capacitors in the capacitive coupling circuit 120 during the compensation period. A potential difference is generated between the source and gate of the driving transistor T1. In this way, the variation of the threshold voltage can be compensated, so that the display panel produces uniform brightness. In addition, in some embodiments, the power signal can be adjusted during the reset period to release the residual voltage of the light emitting diode 110 to prevent the display panel from flickering.

In some embodiments, the capacitive coupling circuit 120 includes at least a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 are connected in series with each other. Specifically, the first capacitor C1 has a first terminal and a second terminal, and the first terminal of the first capacitor C1 is electrically connected to the reference voltage source Vss. The second terminal of the first capacitor C1 is electrically connected to the first node A. The second capacitor C2 has a first end and a second end, wherein the first end of the second capacitor C2 is electrically connected to the first node A, and the second end of the second capacitor C2 is electrically connected to the driving transistor T1 Control terminal.

In some embodiments, the pixel circuit 100 further includes a second switching transistor T4, and the second switching transistor T4 has a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switching transistor T4 is used To receive the data signal Vdata, the second terminal of the second switching transistor T4 is electrically connected to the first terminal (or second node B) of the compensation transistor T2, and the control terminal of the second switching transistor T4 is used to receive The second compensation control signal S2. In this embodiment, the second compensation control signal S2 is used to control the second switching transistor T4 to be turned on or off.

FIG. 2 is an operation timing chart drawn according to some embodiments of the present disclosure. The duty cycle of the pixel circuit 100 includes a reset period P1, a compensation period P2, a data writing period P3, and a light emitting period P4. In some embodiments, the pixel circuit 100 is applied to a display device, and the processor of the display device sequentially drives the pixel circuits 100 of each row (please refer to the schematic diagram of the display device 200 in FIG. 6). S3[n] and S3[n+1] in FIG. 2 represent the gate signal S3 for driving the adjacent pixel circuit 100.

Please refer to FIGS. 2 and 3A. During the reset period P1, the power signal Vdd is reduced to the first low level voltage Vddl to turn off the driving transistor T1. In this way, it can ensure that the light emitting diode 110 is reset During the period P1, no current flows, and the voltage of the positive terminal of the light-emitting diode 110 is discharged to a low potential to avoid flickering of the display panel. At the same time, the first compensation control signal S1 is the disabled level, so that the compensation transistor T2 is turned off. The gate signal S3 and the second compensation control signal S2 are enable levels, so that the first switching transistor T3 and the second switching transistor T4 are respectively turned on, and the first node A and the second node B receive the data signal Vdata, In one embodiment, during the reset period P1, the data signal Vdata is the reference level voltage Vref, and the reference level voltage Vref is at a high level, so as to raise the voltage values of the first node A and the second node B. For example, in this embodiment, the driving transistor T1, the compensation transistor T2, the first switching transistor T3, and the second switching transistor T4 are all P-type TFTs (thin film transistors). As shown in FIG. 2, for the P-type TFT, the disable level is high and the enable level is low. Conversely, when the driving transistor T1, the compensation transistor T2, the first switching transistor T3, and the second switching transistor T4 are all N-type TFTs, the disable level is low and the enable level is high.

Please refer to FIGS. 2 and 3B. During the compensation period P2, the first compensation control signal S1 and the gate signal S3 are enable levels, so that the compensation transistor T2 and the first switching transistor T3 are turned on. The second compensation control signal S2 is the disable level to turn off the second switching transistor T4. The data signal Vdata remains at the second low level voltage VL, and the power signal remains at the first low level voltage Vddl. In one embodiment, the second low level voltage VL is less than the first low level voltage Vddl. By controlling the data signal Vdata at a lower second low level voltage VL, the voltage value of the first node A can be reduced. At the same time, through the capacitive coupling effect in the capacitive coupling circuit 120, the voltage value of the second node B also drops, so that the source (second end) and the gate (control end) of the driving transistor T1 can be pulled apart ) To ensure that the driving transistor T1 is turned on. At this time, the voltage value of the second node B will be controlled at Vddl-|Vth| (the critical voltage value of the driving transistor T1), and the voltage of the first node A will be controlled at the second low level voltage VL.

Please refer to FIGS. 2 and 3C. During the data writing period P3, the first compensation control signal S1 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2 and the second switching transistor T4. The gate signal S3 is an enable level to maintain the conduction of the first switching transistor T3. In some embodiments, the enable level of the gate signal S3 is a low level voltage. As shown in FIG. 2, the display device sequentially writes data to adjacent pixel circuits 100. Therefore, the gate signals S3 of different pixel circuits 100 (ie, S3[n], S3[n+ 1]) will be controlled to a low level voltage in sequence.

According to the above, during the data writing period P3, the first node A receives the data signal Vdata through the conduction of the first switching transistor T3. The data signal Vdata corresponds to a write voltage Vin, which is used to determine the light emitting intensity of the light emitting diode 110. During the data writing period P3, the voltage value of the first node A changes from the original VL to Vin, therefore, according to the capacitive coupling effect, the voltage value on the second node B will have the same variation range as the first node A . The voltage change range of the first node is "Vin-VL", so the voltage value of the second node B becomes "Vddl-|Vth|+(Vin-VL)".

Please refer to figures 2 and 3D. During the light-emitting period P4, the first compensation control signal S1, the gate signal S3 and the second compensation control signal S2 are kept at the disabled level, so that the compensation transistor T2 and the first switching transistor Both T3 and the second switching transistor T4 are turned off, and the power signal is the first high level voltage Vddh. At this time, the driving transistor T1 can output the power signal Vdd to the light emitting diode 110, so that a driving current Id flows through the light emitting diode 110 to generate a desired brightness. According to the current formula of the transistor "I=K×(Vsg-|Vth|) ² ", where K represents the carrier mobility of the driving transistor T1, the unit capacitance of the gate oxide layer and the gate The product of width to length ratio. Vsg is the voltage difference between the second terminal (source) of the driving transistor T1 and the control terminal. |Vth| is the critical voltage value of the driving transistor T1. When the driving transistor T1 is turned on, the first end and the second end thereof can be regarded as a short circuit. Therefore, the second end (source) of the driving transistor T1 can be regarded as the first high level voltage Vddh. The aforementioned formula can be sorted into "I=K×(Vddh-Vddl+|Vth|-(Vin-VL)-|Vth|) ² ", because the current is independent of the critical voltage value, so that the light emitting diode 110 can be guaranteed to emit light The strength will not be affected by the variation of the critical voltage value.

Please refer to FIGS. 4A to 4D and 5 for schematic diagrams drawn according to other embodiments of the present disclosure. Please refer to FIGS. 4A and 5. In some embodiments, the first end of the driving transistor T1 receives the fixed power signal Vdd, and the first end of the second switching transistor T4 is used to receive the power signal Vdd. The second end of the driving transistor T1 is electrically connected to the reference voltage source Vss through the light-emitting diode 110.

In this embodiment, during the reset period P1, the reference voltage source Vss is the second highest level voltage Vssh, so that the driving transistor T1 and the light-emitting diode 110 are turned off to avoid the flicker phenomenon of the light-emitting diode 110 . The first compensation control signal S1 and the gate signal S3 are the disable level, the second compensation control signal S2 is the enable level, and the data signal Vdata is the reference level voltage Vref. At this time, the voltage of the second node B will be controlled at the power signal Vdd.

Please refer to FIG. 4B and FIG. 5, in the compensation period P2, the first compensation control signal S1 and the gate signal S3 are enable levels to turn on the compensation transistor T2 and the first switching transistor T3. The second compensation control signal S2 is the disable level to turn off the second switching transistor T4. The data signal Vdata is a low-level reference level voltage Vref. In one embodiment, the second high level voltage Vssh is greater than the reference level voltage Vref. At this time, the first node A receives the data signal Vdata through the first switching transistor T3, so that the voltage value is controlled to a low potential. Through the capacitive coupling effect of the capacitive coupling circuit 120, the voltage of the second node B will drop accordingly, so that the driving transistor T1 can be turned on. At the same time, since the gate (control terminal) and source (second terminal) of the driving transistor T1 are conducted through the compensation transistor T2, the voltage value of the second node B will be controlled at Vdd-|Vth| The threshold voltage of the crystal T1), and the voltage of the first node A is controlled at the reference level voltage Vref.

Please refer to FIG. 4C and FIG. 5, during the data writing period P3, the first compensation control signal S1 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2 and the second switching transistor T4. The gate signal S3 is the enabling level. At this time, the first node A receives the data signal Vdata through the first switching transistor T3, and the data signal Vdata corresponds to the write voltage Vin for determining the subsequent light emitting intensity of the light emitting diode 110. During the data writing period P3, the voltage value of the first node A changes from the original Vref to Vin, therefore, according to the capacitive coupling effect, the voltage value on the second node B will have the same variation range as the first node A . The voltage change range of the first node is "Vin-Vref", so the voltage value of the second node B becomes "Vdd-|Vth|+(Vin-Vref)".

Please refer to FIG. 4D and FIG. 5, during the light-emitting period P4, the first compensation control signal S1, the gate signal S3 and the second compensation control signal S2 are disabled levels to turn off the compensation transistor T2, the first The switching transistor T3 and the second switching transistor T4. The reference voltage source Vss changes to the third lowest level voltage Vssl. According to the capacitive coupling effect, the voltage changes of the first node A and the second node B will occur, and the change amplitude will be consistent with the voltage value of the reference voltage source Vss "Vssh-Vssl", that is, the second node B The voltage value will become "Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)". At this time, the driving transistor T1 can output the power signal Vdd to the light emitting diode 110 to make the light emitting diode 110 emit light.

When the driving transistor T1 is turned on, the first end and the second end thereof can be regarded as a short circuit. Therefore, the second end (source) of the driving transistor T1 can be regarded as the first high level voltage Vddh. The current formula of the transistor can be sorted into "I=K×(Vdd-(Vdd-|Vth|+(Vin-Vref)-(Vssh-Vssl)-|Vth|) ² ", because the current has nothing to do with the critical voltage value Therefore, it can be ensured that the light emitting intensity of the light emitting diode 110 is not affected by the variation of the threshold voltage value.

Figures 3A~3D and 4A~4D illustrate the two partial embodiments of the disclosure, the difference between the two is that the embodiments of Figures 4A~4D are by adjusting the voltage value of the reference voltage source Vss To control the driving transistor T1 to be turned on or off. In addition, in the embodiment shown in FIGS. 4A to 4D, the second switching transistor T4 is electrically connected to the power signal Vdd. The embodiment of the figure is different.

Please refer to FIG. 6, which is a display device 200 according to some embodiments of the present disclosure. The display device 200 includes at least a source driver 210, a gate driver 220, and a compensation circuit 230. The display device 200 is used to drive a display panel to generate a desired image. In some embodiments, the display panel includes a display area 201 and a non-display area 202, a plurality of pixel circuits 100 are located in the display area 201, and a plurality of compensation circuits 230 are located in the non-display area 202.

In some embodiments, the display device 200 further includes a plurality of gate lines GL, a plurality of data lines DL, at least one first compensation control line 203 and at least one second compensation control line 204. The gate lines GL are electrically connected to the gate driver 220 and the pixel circuit 100 (eg, electrically connected to the control end of the first switching transistor T3), and are used to transmit the gate signal S3 respectively. The data lines DL are electrically connected to the source driver 210 and the pixel circuit 100 (eg, electrically connected to the first switching transistor T3 and the second switching transistor T4) for transmitting the data signal Vdata. The first compensation control line 203 is electrically connected to the compensation circuit 230 and the pixel circuit (eg, electrically connected to the control terminal of the compensation transistor T2), and is used to transmit the first compensation control signal S1. The second compensation control line 204 is electrically connected to the compensation circuit 230 and the pixel circuit (eg, electrically connected to the control terminal of the second switching transistor T4), and is used to transmit the second compensation control signal S2.

In some embodiments, multiple pixel circuits are arranged in an array shape. Referring to FIGS. 1 and 6, the pixel circuit 100 includes a light-emitting diode 110, a driving transistor T1, a compensation transistor T2, a capacitive coupling circuit 120, a first switching transistor T3, and a second switching transistor T4. The driving transistor T1 has a first end, a second end and a control end. The first end of the driving transistor T1 is used to receive the power signal Vdd. The second end of the driving transistor T1 is electrically connected to the light emitting diode 110. The control terminal of the driving transistor T1 is used to receive the driving voltage to output the power signal Vdd to the light emitting diode 110 according to the driving voltage. In some embodiments, the driving voltage is the data signal Vdata (ie, the input voltage Vin) in the aforementioned data writing period P3. In the reset period P1, the driving transistor T1 is turned off, so that the voltage on the light emitting diode 110 is discharged.

The compensation transistor T2 is used to selectively turn on the control terminal of the driving transistor T1 and the second terminal according to the first compensation signal S1. In some embodiments, the control terminal of the compensation transistor T2 is electrically connected to the first compensation control line to receive the first compensation control signal S1. The capacitive coupling circuit 120 has a first node A and a second node B. During the compensation period P2, the first node A of the capacitive coupling circuit 120 is used to receive the data signal Vdata (ie, the aforementioned input voltage Vin), and the second node B is electrically connected to the control terminal of the driving transistor T1. The capacitive coupling circuit 120 includes a plurality of capacitors, so that when the first node A receives the data signal Vdata, the voltage level of the driving voltage of the control terminal of the driving transistor T1 changes according to the change in the voltage level of the data signal Vdata.

In some embodiments, the first end of the first switching transistor T3 is electrically connected to one of the data lines DL for receiving the data signal Vdata. The control terminal of the first switching transistor T3 is electrically connected to one of the gate lines GL for receiving the gate signal S3. The control terminal of the second switching transistor T4 is electrically connected to the second compensation control line for receiving the second compensation control signal S2.

In some embodiments of the present disclosure, the display device 200 controls all pixel circuits to reset and compensate simultaneously. Then, the gate driver 220 controls the pixel circuits of each column to sequentially write data. Since those skilled in the art can understand the operation sequence of the pixel circuit for driving the display panel, it will not be repeated here.

Although the present disclosure has been disclosed as above by way of implementation, it is not intended to limit the content of the present invention. Anyone who is familiar with this skill can make various changes and modifications within the spirit and scope of the present content, so the present invention The protection scope of the content shall be deemed as defined by the scope of the attached patent application.

100‧‧‧Pixel circuit

110‧‧‧ LED

120‧‧‧Capacitive coupling circuit

T1‧‧‧Drive transistor

T2‧‧‧Compensation transistor

T3‧‧‧ First switching transistor

T4‧‧‧second switching transistor

C1‧‧‧ First capacitor

C2‧‧‧Second capacitor

S1‧‧‧First compensation control signal

S2‧‧‧Second compensation control signal

S3‧‧‧Gate signal

Vdd‧‧‧power signal

Vdata‧‧‧Data signal

Vss‧‧‧reference voltage source

A‧‧‧First node

B‧‧‧The second node

Claims (23)

A pixel circuit includes: a light-emitting diode; a driving transistor having a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, The second end of the driving transistor is electrically connected to the light-emitting diode; a compensation transistor has a first end, a second end and a control end, wherein the second end of the compensation transistor is electrically Connected to the light-emitting diode, the control terminal of the compensation transistor is used to receive a first compensation control signal; a capacitive coupling circuit has a first terminal, a first node and a second node, wherein the capacitor The first end of the coupling circuit is electrically connected to a reference voltage source, and the second node of the capacitive coupling circuit is electrically connected to the control end of the driving transistor and the first end of the compensation transistor; a first The switching transistor has a first end, a second end and a control end, the first end of the first switching transistor is used to receive a data signal, and the second end of the first switching transistor is electrically Connected to the first node, the control terminal of the first switching transistor is used to receive a gate signal; and a second switching transistor has a first terminal, a second terminal and a control terminal, the second The first end of the switching transistor is used to receive the data signal, the second end of the second switching transistor is electrically connected to the first end of the compensation transistor, and the second end of the second switching transistor The control terminal is used to receive a second compensation control signal; wherein the capacitive coupling circuit further includes: a first capacitor having a first terminal and a second terminal, the The first end is electrically connected to the reference voltage source, and the second end of the first capacitor is electrically connected to the first node; and a second capacitor has a first end and a second end, the first The first terminal of the two capacitors is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the control terminal of the driving transistor. The pixel circuit according to claim 1, wherein during a reset period, the power signal is a first low level voltage, the first compensation control signal is a disabled level, the gate signal and the first The second compensation control signal is a uniform energy level, and the data signal is a reference level voltage. The pixel circuit according to claim 2, wherein in a compensation period, the first compensation control signal and the gate signal are the enable level, and the second compensation control signal is the disable level, the data The signal is a second low level voltage. The pixel circuit according to claim 3, wherein the second low level voltage is smaller than the first low level voltage. The pixel circuit according to claim 4, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level, and the gate signal is the enable level. The pixel circuit as described in claim 5, wherein in a light-emitting period In the meantime, the first compensation control signal, the gate signal and the second compensation control signal are the disable level. The pixel circuit of claim 1, wherein the second terminal of the driving transistor is electrically connected to the reference voltage source, and during a reset period, the reference voltage source is a first high level voltage, the The first compensation control signal and the gate signal are a disabling level, the second compensation control signal is a uniform level, and the data signal is a reference level voltage. The pixel circuit according to claim 7, wherein in a compensation period, the first compensation control signal and the gate signal are at a uniform energy level, and the second compensation control signal is the disabled level. The pixel circuit according to claim 8, wherein the first high level voltage is greater than the reference level voltage. The pixel circuit according to claim 9, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level, and the gate signal is the enable level. The pixel circuit according to claim 10, wherein the first compensation control signal, the gate signal and the second compensation control signal are the disable level during a light-emitting period. A pixel circuit includes: a light-emitting diode; a driving transistor having a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, The second end of the driving transistor is electrically connected to the light emitting diode, and the control end of the driving transistor is used to receive a driving voltage to output the power signal to the light emitting diode according to the driving voltage, During a reset period, the driving transistor is turned off to discharge the voltage on the light-emitting diode; a compensation transistor is used to selectively turn on the control of the driving transistor according to a first compensation signal End and the second end; and a capacitive coupling circuit, having a first node and a second node, and the first node of the capacitive coupling circuit is used to receive a data signal during a compensation period, the capacitive coupling circuit The second node is electrically connected to the control terminal of the driving transistor; wherein when the first node of the capacitive coupling circuit receives the data signal, the voltage level of the driving voltage corresponds to the voltage level of the data signal Change and change. The pixel circuit according to claim 12, wherein the capacitive coupling circuit includes: a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is electrically connected to a reference voltage Source, the second end of the first capacitor is electrically connected to the first node; and a second capacitor has a first end and a second end, wherein the second The first terminal of the capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the control terminal of the driving transistor. The pixel circuit according to claim 12, further comprising: a first switching transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switching transistor is used to Receiving the data signal during the compensation period, the second end of the first switching transistor is electrically connected to the first node, wherein, when the first switching transistor is turned on, the first node passes through the first switch The transistor receives the data signal. The pixel circuit according to claim 14, further comprising: a second switching transistor having a first terminal, a second terminal and a control terminal, and the first terminal of the second switching transistor is used for Receiving the data signal, the second end of the second switching transistor is electrically connected to the second node. The pixel circuit according to claim 15, wherein during the reset period, the first switching transistor and the second switching transistor are respectively turned on, so that the first node and the second node respectively receive a reference level Signal. The pixel circuit according to claim 14, wherein the first switching transistor and the compensation transistor are turned on during a compensation period. The pixel circuit according to claim 14, further comprising: a second switching transistor having a first terminal, a second terminal and a control Terminal, wherein the first terminal of the second switching transistor is used to receive the power signal, and the second terminal of the second switching transistor is electrically connected to the second node. A display device includes: a plurality of gate lines for transmitting a gate signal; a plurality of data lines for transmitting a data signal; a first compensation control line for transmitting a first compensation control signal A second compensation control line for transmitting a second compensation control signal; and a plurality of pixel circuits, arranged in an array shape, at least one of the pixel circuits includes: a light emitting diode; The driving transistor has a first end, a second end and a control end, wherein the first end of the driving transistor is used to receive a power signal, and the second end of the driving transistor is electrically connected to the light emitting Diode; a compensation transistor with a first end, a second end and a control end, wherein the second end of the compensation transistor is electrically connected to the light-emitting diode, the compensation transistor The control terminal is electrically connected to the first compensation control line for receiving the first compensation control signal; a capacitive coupling circuit has a first terminal, a first node and a second terminal, wherein the The first terminal is electrically connected to a reference voltage source, the second terminal of the capacitive coupling circuit is electrically connected to the control terminal of the driving transistor and the first terminal of the compensation transistor; a first switching transistor , With a first end, a second end and a control End, the first end of the first switching transistor is electrically connected to one of the data lines for receiving the data signal, and the second end of the first switching transistor is electrically connected to the first node , The control terminal of the first switching transistor is electrically connected to one of the gate lines for receiving the gate signal; and a second switching transistor has a first end and a second end And a control end, the first end of the second switching transistor is used to receive the data signal, the second end of the second switching transistor is electrically connected to the first end of the compensation transistor, and The control terminal of the second switching transistor is electrically connected to the second compensation control line for receiving the second compensation control signal. The display device of claim 19, wherein during a reset period, the first compensation control signal is a disabling level, and the second compensation control signal is a uniform level. The display device of claim 20, wherein in a compensation period, the first compensation control signal is the enabling level, and the second compensation control signal is the disabling level. The display device according to claim 21, wherein during a data writing period, the first compensation control signal and the second compensation control signal are the disable level. The display device according to claim 22, wherein during a light-emitting period, The first compensation control signal and the second compensation control signal are the disable level.

Images