CN112599078B

CN112599078B - Pixel unit and pixel external analog domain compensation display system

Info

Publication number: CN112599078B
Application number: CN202011495974.3A
Authority: CN
Inventors: 林兴武; 张盛东; 张敏; 焦海龙; 邱赫梓; 李成林
Original assignee: Peking University Shenzhen Graduate School
Current assignee: Peking University Shenzhen Graduate School
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2022-03-01
Anticipated expiration: 2040-12-17
Also published as: CN112599078A

Abstract

The invention provides a pixel unit and an off-pixel analog domain compensation display system, wherein the pixel unit comprises a driving tube, a second switching tube, a third switching tube, a light emitting diode, a first capacitor and a second capacitor; the display system comprises M columns of driving channels, each column of driving channels comprises a detection unit and the pixel units, the detection unit comprises a source driving module and a detection module, and the detection module comprises a comparator. The pixel unit of the invention does not need to control the gate-source voltage difference of the driving tube Q1 according to the traditional current source design scheme so as to control the current provided by the driving tube Q1 to the light emitting diode T1, thereby realizing improvement on the basis of the traditional scheme. The display system of the invention directly detects the threshold voltage of the pixel unit driving tube and the threshold voltage change condition of the OLED by repeatedly using the existing module, thereby optimizing the overall design of the display system.

Description

Pixel unit and pixel external analog domain compensation display system

Technical Field

The invention relates to the technical field of photoelectricity, in particular to a pixel unit and an off-pixel analog domain compensation display system.

Background

In an OLED (Organic Light-Emitting Diode or Organic electroluminescent Display) Display system in the prior art, for example, an OLED-on-Silicon (OLED-on-Silicon) Display system, a pixel unit circuit is designed as a current source, and the OLED is generally driven by voltage programming and current driving. That is, the display voltage related to the gray scale is written into the pixel unit circuit in the form of voltage, and then the pixel unit circuit generates a current with a fixed magnitude according to the magnitude of the display voltage to drive the OLED to emit light. The pixel unit circuit of the current source controls the magnitude of the driving current by controlling the voltage difference between the gate and the source of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) device. The disadvantage of this method is that the highest and lowest amplitudes of the display voltage are relatively small, resulting in relatively small gate-source voltage difference distances between each gray scale, as shown by curve 1 in fig. 4, and also resulting in increased difficulty in circuit design.

In many display products in the prior art, for example, an AMOLED (Active-matrix organic light-emitting diode or Active-matrix organic light-emitting diode) is a display screen that uses a TFT (Thin Film Transistor) to display a pixel unit circuit and adds an OLED thereon. The micro-display product of OLED-on-Silicon or QLED-on-Silicon type is a pixel unit circuit array made of Silicon, and OLED or QLED (Quantum Dot Light Emitting Diodes T1) Light Emitting devices are added on the micro-display product. TFT, OLED, QLED, etc. all suffer from aging problems after light emission, e.g., TFT threshold voltage rise causes the TFT to age the same display signal giving less current. When the display screen starts displaying, the threshold voltage of the aging TFT or the threshold voltage of the aging OLED can shift. The increase in OLED threshold voltage results in a decrease in OLED current. The light emitting efficiency of an aging OLED decreases, i.e., the same input current, and the light emitted by the aging OLED decreases. Besides the aging problem, the TFT, the OLED, the QLED, and the like have the problem of uneven threshold voltage, for example, uneven threshold voltage and uneven light emitting brightness of the display screen may be caused during the production process due to the process. Due to the different display positions of the pixel units on the display screen, the uneven power supply voltage of the pixel units can be caused by the flowing of current when the display screen emits light, and the uneven temperature can cause the uneven current of the driving tubes. The unevenness of each channel source driving module can cause the unevenness of the feedback driving current. In addition, the display driving chips of all pixel systems have the problem of uneven driving of different driving channels, i.e. driving circuits.

Disclosure of Invention

The invention provides a pixel unit, which comprises a driving tube, a second switching tube, a third switching tube, a light-emitting device, a first capacitor and a second capacitor, wherein the driving tube is connected with the second switching tube; the grid electrode of the second switch tube is used for being connected to the first display address wire, the first pole of the second switch tube is used for being connected to the display signal wire, and the second pole of the second switch tube is connected to the grid electrode of the driving tube and the first pole of the first capacitor; the second pole of the first capacitor is connected to the ground end of the driving circuit or the cathode of the light-emitting device; the first pole of the driving tube is connected to the high potential end, and the second pole of the driving tube is connected to the anode of the light-emitting device and the first pole of the third switching tube; the cathode of the light emitting device is connected to the low potential terminal; the grid electrode of the third switching tube is used for being connected to the feedback address wire, and the second pole of the third switching tube is used for being connected to the feedback signal wire; the first pole of the second capacitor is connected to the ground end of the driving circuit, and the second pole of the second capacitor is connected to the low potential end; the high potential end is a power supply voltage end of the light emitting device, and the low potential end is a negative voltage end with the voltage absolute value smaller than the threshold voltage absolute value of the light emitting device.

The invention also provides an off-pixel analogue domain compensation display system, which comprises M rows of driving channels; each row of driving channels comprises a detection unit and the pixel units; the detection unit comprises a source driving module and a detection module; the detection module comprises a comparator; the system is an out-of-pixel compensation double-digital-analog converter display system, and a first digital-analog converter and a second digital-analog converter are arranged in the source driving module; the source driving module is connected to the pixel unit through a display signal line; a first input end of the comparator is connected to the pixel unit through a feedback signal line and used for receiving a feedback voltage corresponding to a feedback signal of the pixel unit; the second input end of the comparator is connected to the second digital-to-analog converter and used for receiving the comparison voltage output by the second digital-to-analog converter; the output end of the comparator is used for outputting a detection result obtained by comparing the feedback voltage with the comparison voltage; wherein M is an integer of 1 or more.

The pixel unit of the invention does not need to control the gate-source voltage difference of the driving tube Q1 according to the traditional current source design scheme so as to control the current provided by the driving tube Q1 to the light-emitting diode T1, thereby realizing improvement on the basis of the traditional scheme, designing the pixel circuit as a voltage source, accurately controlling the anode voltage of the light-emitting diode T1, and controlling the current of the light-emitting diode T1 by utilizing the relation of the voltage and the current of the light-emitting diode T1. With the same current amplitude, the programming voltage amplitude of the light emitting diode T1 is larger, and the gate-source voltage difference amplitude of the driving transistor Q1 is much smaller, so that the programming voltage amplitude is also smaller, and further the design difficulty is larger, as shown in the curve 1 and the curve 2 of fig. 4. The display system of the invention directly detects the threshold voltage of the pixel unit driving tube and the threshold voltage change condition of the OLED by repeatedly using the existing modules (namely DAC and comparator), thereby optimizing the overall design of the display system.

Drawings

Fig. 1 is a schematic circuit diagram of a pixel unit according to a first embodiment;

FIG. 2 is a timing diagram illustrating a display operation of a pixel unit according to a first embodiment;

FIG. 3 is a timing diagram illustrating a correction feedback operation of a pixel unit according to the first embodiment;

FIG. 4 is a graph showing gray scale versus display voltage;

FIG. 5 is a schematic circuit diagram of a pixel unit according to a second embodiment;

FIG. 6 is a timing diagram illustrating a display operation of a pixel unit according to a second embodiment;

FIG. 7 is a schematic circuit diagram of a pixel unit according to a third embodiment;

fig. 8 is a schematic structural view of a display system according to the fourth embodiment to the ninth embodiment;

FIG. 9 is a schematic diagram of a conventional external compensation display system;

FIG. 10 is a schematic partial structure diagram of a display system according to a fourth embodiment;

FIG. 11 is a schematic view of a flow chart of a detecting operation according to the fourth embodiment to the ninth embodiment;

FIG. 12 is a schematic partial structure diagram of a display system according to the fifth embodiment;

FIG. 13 is a schematic partial structure diagram of a display system according to a sixth embodiment;

FIG. 14 is a schematic partial structure diagram of a display system according to a seventh embodiment;

FIG. 15 is a schematic partial structure diagram of a display system according to an eighth embodiment;

FIG. 16 is a schematic partial structure diagram of a display system according to the ninth embodiment;

FIG. 17 is a schematic diagram illustrating comparison between feedback voltage and comparison voltage;

FIG. 18 is a schematic diagram of a pixel unit circuit according to an embodiment;

FIG. 19 is a schematic circuit diagram of a pixel unit according to a second modification of the first embodiment;

fig. 20 is a schematic circuit diagram of a pixel unit according to a third improvement of the embodiment.

Reference numerals: the display device comprises a controller 10, a row scan driver 20, a source driver 30, a display panel 40, a timing control module 11, a compensation algorithm module 12, an aging information memory 13, a first shift-in circuit 34, a second shift-in circuit 35, a detection unit 32, a shift-out circuit 33, a source drive module 321, a detection module 322, a first digital-to-analog converter 61, a second digital-to-analog converter 62, an analog adder 63, a comparator 72, a current source 73, a pixel unit 41, a display address line 42, a feedback address line 43, a display signal line 44, a feedback signal line 45, a second switching tube Q2, a third switching tube Q3, a driving tube Q1, a light emitting diode T1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth switching tube Q4, a fifth switching tube Q5, a first switch sw1 and a second switch sw 2.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present invention have not been shown or described in the specification in order to avoid obscuring the present invention from the excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they can be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" as used herein includes both direct and indirect connections (couplings), unless otherwise specified.

Herein, N is an integer of 1 or more and N or less; m is an integer greater than or equal to 1, and M is an integer greater than or equal to 1 and less than or equal to M; k is a natural number greater than 0, and K is a natural number greater than 0.

The skilled person can select specific types of the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 according to actual situations, for example, the types of the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 can be transistors prepared by amorphous silicon, polycrystalline silicon, oxide semiconductors, organic semiconductors, thin film processes, NMOS processes, PMOS processes or CMOS processes. When the specific types of the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 are selected, the display panel circuit structure can be formed only by adaptively adjusting the connection relationship of the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5, and the display panel is designed by replacing the driving transistor Q1, the second switching transistor Q2, the third switching transistor Q3, the fourth switching transistor Q4 and the fifth switching transistor Q5 with a certain type of transistor. The second switching tube Q2, the driving tube Q1, the third switching tube Q3, the fourth switching tube Q4 and the fifth switching tube Q5 may be N-type tubes, or a person skilled in the art may select the second switching tube Q2, the driving tube Q1, the third switching tube Q3, the fourth switching tube Q4 and the fifth switching tube Q5 as P-type tubes according to actual requirements of circuit design, and only the connection mode of the switching tubes needs to be adaptively adjusted, which also falls within the technical scheme of the present application.

In the design process of a specific circuit structure, a person skilled in the art can use a source electrode of a transistor as a first pole and a drain electrode as a second pole; alternatively, the drain of the transistor may be a first electrode and the source may be a second electrode.

It should be understood by those skilled in the art that, in the present invention, the "feedback signal" may refer to "feedback voltage" hereinafter, and may also refer to "feedback information". In the following embodiments, the feedback information, the feedback signal and the feedback voltage may represent the aging information or the aging condition of the device.

The display system of the present invention is an out-of-pixel compensation dual DAC display system, alternatively referred to as an out-of-pixel compensation AMOLED display system.

The comparator of the detecting unit 32 in the present invention is a voltage comparator, and the detecting module 322 is a module for detecting aging information.

The Light Emitting device is a Light Emitting Diode, and may be an Organic Light Emitting Diode (OLED), or a quantum dot Light Emitting Diode (QLED), or a general type and other various types of LEDs (Light-Emitting Diode).

The aging information memory 13 can store various kinds of aging information.

The first embodiment is as follows:

fig. 1 shows a circuit structure of a pixel unit of this embodiment, which includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3, a light emitting diode T1, a first capacitor C1, and a second capacitor C2. In this embodiment, the pixel units in the nth row and the mth column in the off-pixel analog domain compensation display system are taken as an example for description.

The gate of the second switch tube Q2 is used to connect to the first display address line SCAN [ n ] of the nth row (V _ SCAN _ n is the nth row display address signal), the first pole thereof is used to connect to the display signal line DATA [ m ] of the mth column (V _ DATA _ n _ m is the display signal of the mth row and mth column pixel unit), the second pole thereof is connected to the gate of the driving tube Q1 and the first pole of the first capacitor C1; the second pole of the first capacitor C1 is connected to the VSS terminal (i.e. the ground of the display system driving circuit) or to the cathode of the light emitting diode T1; a first pole of the driving transistor Q1 is connected to the VOLED _ HIGH terminal (i.e., HIGH potential terminal), and a second pole thereof is connected to the anode of the light emitting diode T1 and the first pole of the third switching transistor Q3; the cathode of the light emitting diode T1 is connected to the VOLED _ LOW terminal (i.e., the LOW potential terminal); the gate of the third switch Q3 is used to connect to the feedback address line FB _ SCAN [ n ] (V _ FB _ SCAN _ n is the nth row feedback address signal) of the nth row, and the second pole is used to connect to the feedback signal line FB _ DATA [ m ] (V _ FB _ DATA _ n _ m is the feedback signal of the mth row pixel unit of the mth column).

A first pole of the second capacitor C2 is connected to the VSS terminal, and a second pole thereof is connected to the VOLED _ LOW terminal. The second capacitor C2 may be placed within the circuitry of the pixel cell, such that the second capacitor C2 is part of the pixel cell layout; or, the pixel unit is a part of the micro display chip, and the second capacitor C2 is disposed outside the circuit of the pixel unit and inside the chip where the pixel unit is located; or, the pixel unit is a part of the micro display chip, the micro display chip is inserted on the integrated circuit board, and the second capacitor C2 is disposed outside the chip where the pixel unit is located and on the integrated circuit board where the chip is located.

The VOLED _ HIGH terminal is a power voltage terminal of the light emitting diode T1, and is responsible for supplying power to the light emitting diode T1. The voltage of the VOLED _ LOW terminal is an absolute value of a threshold voltage of the light emitting diode T1, the voltage of the VOLED _ LOW terminal is smaller than an absolute value of a threshold voltage of the light emitting diode T1, the VOLED _ LOW terminal may be, for example, a 0V voltage terminal or a negative voltage terminal having a voltage smaller than a threshold voltage of the light emitting diode T1, for example, the threshold voltage of the light emitting diode T1 is 3V, and the voltage of the cathode terminal of the light emitting diode T1 is-2V. The VSS terminal is the ground of the display system driving circuit and is 0V.

The driving transistor Q1 is responsible for transferring a part of its gate voltage to its source and the anode of the light emitting diode T1 as a voltage source (also called as a voltage follower or source follower), the second switching transistor Q2 is a display signal writing channel of the pixel unit, and the third switching transistor Q3 is a feedback channel of the feedback signal of the pixel unit. The light emitting diode T1 is an OLED and emits light with a luminance corresponding to the anode voltage thereof.

In a modified solution, on the basis of the above design of the pixel unit circuit, a third capacitor C3 may be added to the circuit to obtain a modified pixel unit circuit as shown in fig. 18, where a first pole of the third capacitor C3 is connected to the gate of the driving transistor Q1, and a second pole thereof is connected to the anode of the light emitting diode T1.

The pixel cell circuit of this embodiment operates on the principle that when the display signal of V _ DATA _ n _ m is written into the gate of the driving transistor Q1 of the nth row and mth column of pixel cells, the voltage is subtracted by a gate-source voltage difference (Vds, g) of the driving transistor Q1 and then transmitted to the source of the driving transistor Q1, i.e., the voltage transmitted to the source of the driving transistor Q1 is V _ DATA _ n _ m-Vds, g. Vds, g represents the gate-source voltage difference of the driving tube Q1 when the current corresponding to the gray scale g flows out from the driving tube Q1 when the display gray scale is g. The source of the driving transistor Q1 is also the anode of the led T1, and the led T1 emits light corresponding to the gray level g under the action of the voltage. In this process, the driving transistor Q1 is equivalent to a voltage source, and the pixel unit circuit of this embodiment designs the driving transistor Q1 as a voltage source, which can provide voltage to the OLED, so as to limit the current by the OLED. It can be seen that the display system of the present embodiment does not use the conventional current source design concept to design the driving transistor Q1 as a current source, but improves on the conventional solution, which uses a method of controlling the gate-source voltage difference of the driving transistor Q1 to control the current supplied by the driving transistor Q1 to the light emitting diode T1. The control effect of the present embodiment is difficult to achieve by the conventional pixel unit circuit because the difference between the display signal voltages of the lowest and highest gray scales of the conventional pixel unit circuit is relatively small.

In the case where the pixel cell is applied to the display system shown in fig. 8 during the display operation, the switches sw1 and sw2 shown in fig. 8 are configured such that the display signal line is connected to the output terminal of the source driving module and disconnected from the V1 terminal. As shown in fig. 2, which is a timing diagram of the display operation of the pixel units in the 1 st row to the nth row, the update process of the display signal of one frame is as follows: the row scanning driver sends out display address signals V _ SCAN _1, V _ SCAN _2, V _ SCAN _3, … V _ SCAN _ N row by row through row display address lines SCAN [1], SCAN [2], … SCAN [ N ], and the writing channels for gating the pixel units of the 1 st row, the 2 nd row, the 3 rd row and the … Nth row by row. When the source driver gates a writing channel of the pixel unit in the 1 st row, the source driver simultaneously sends out a display signal of the pixel unit in the 1 st row through a display signal line in the 1 st row, and V _ DATA _ n is the display signal of the pixel unit in the nth row; the value of N ranges from 1 to N. L _1 in the V _ DATA _ N waveform represents the display signals of all the pixels in the 1 st row, L _2 represents the display signals of all the pixels in the 2 nd row, L _3 represents the display signals of all the pixels in the 3 rd row.

t _ display _ period is a full-screen display signal (display signal of one frame) update period during which the display signals of all pixel units are updated once. t _ blank _ period is a blank period between frames, i.e., a period before a frame finishes writing a display signal of the last line and a next frame starts writing a display signal of the first line.

Fig. 3 is a timing diagram illustrating a correction feedback operation of a pixel unit circuit, and fig. 3 is a description of a pixel unit of an nth row, and the correction feedback operation is based on the display system shown in fig. 8. The feedback operation may be performed during a blank period t _ blank _ period from frame to frame. In the display system shown in fig. 8, there are M pixel units in the nth row, and in fig. 3, the M _ n signal is a feedback signal of the pixel units in the nth row, and the M _ n signal includes M feedback signals. The V _ FB _ DATA _ n signal includes a V _ FB _ DATA _ n _ m signal, and the V _ FB _ DATA _ n _ m signal indicates that the feedback signal of the mth column pixel unit in the nth row is fed back on the FB _ DATA [ m ] line (corresponding to the circuit diagram of FIG. 5 and other pixel units).

The correction operation process is divided into 3 steps:

step 1, performed during a time t _ wcali, writes a correction signal. The correction signal is written in the same manner as the display operation of a single line. The line scanning driver gates a writing channel of the target line pixel unit through a line display address line, and the source driver outputs a correction signal of the line to a display signal line; alternatively, in the case where the pixel unit is applied to the display system shown in fig. 8, the switch sw1 and the switch sw2 may be configured such that the display signal line is connected to the V1 terminal. After the write channel is turned off, the calibration signal is stored in the first capacitor C1 and the gate of the driving transistor Q1.

And step 2, during the period of t _ fdback _ sense, the line scanning driver gates a feedback channel of the target line pixel unit through a feedback address line, and the pixel unit outputs a feedback signal to a detection module of the source driver through a feedback signal line. The detection module completes detection of the feedback signal before the feedback channel is turned off and turned on.

And step 3, during the period of t _ back, writing back the original display signals of the pixel units of the target row through a single-row display operation. After the correction signal is written into the pixel unit, the pixel unit can display abnormal pictures, and the normal picture display cannot be influenced because the time is short (for example, 20us-100us) and the picture cannot be identified by naked eyes. The calibration signal may be a low voltage, such as 0V, which ensures that the driving transistor Q1 is turned off and on.

The detection module compares the voltage obtained by feedback of the feedback signal line with a reference voltage by using a comparator, and the comparison result is a digital signal of one bit, and the digital signal is transmitted to the controller from the source driver and is used for updating the data of the aging memory.

The pixel cell circuit of this embodiment can also be used to detect the threshold voltage change of the OLED. The OLED starts to age when it starts to emit light, and after aging, the threshold voltage of the OLED rises. At the beginning of step 2 of the calibration feedback operation, the detection module of the source driver will emit a fixed LOW current, such as 1nA, to flow into the OLED via the feedback signal line and the feedback channel of the pixel unit to the VOLED _ LOW terminal. Since the driving transistor Q1 is turned off and on, all the current will flow to the OLED. Because the current is relatively small, when the voltage on the feedback signal line is stable, the voltage on the feedback signal line can be used to estimate the threshold voltage of the OLED. The threshold voltage of the OLED can be considered as the voltage difference between the voltage on the feedback signal line and the voltage at the VOLED LOW terminal.

The pixel unit circuit of this embodiment adopts voltage programming and voltage driving to make the OLED emit light, that is, the pixel unit circuit is designed as a voltage source, and after a display voltage is written, a relevant voltage is transmitted to the anode of the OLED to make the OLED emit light, and the current is determined by the voltage of the final anode of the OLED. Since OLED devices generally have poorer performance (current) than silicon transistors, if the OLED anode voltage is small enough, a pA level current, such as 2pA, can be generated. In addition, since the performance (current) of the OLED device is poor, the distance of each gray scale of the display voltage written into the pixel unit can be large by using the OLED device for current control, for example, curve 2 in fig. 4. In fig. 4, curve 2 shows the relationship between the gray scale of the pixel unit circuit and the display voltage, and curve 1 shows the relationship between the gray scale of the pixel unit circuit and the display voltage.

Example two:

fig. 5 shows a pixel unit circuit structure of this embodiment, which includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3, a light emitting diode T1, a fourth switching tube Q4, a first capacitor C1, and a second capacitor C2. In this embodiment, the pixel units in the nth row and the mth column in the off-pixel analog domain compensation display system are taken as an example for description.

The difference between the present embodiment and the first embodiment is that the pixel unit circuit of the present embodiment is additionally provided with a fourth switch Q4, a gate of the fourth switch Q4 is used to connect to the second display address line SCAN2[ n ], a first pole of the fourth switch Q4 is connected to the second voltage terminal V2, and a second pole of the fourth switch Q4 is connected to the anode of the light emitting diode T1. The second voltage terminal V2 is a ground terminal; alternatively, the second voltage terminal V2 can be designed to be a voltage terminal with a voltage value lower than the voltage value of the anode of the light emitting diode T1 when the gray scale is 0. The SCAN signal of the second display address line SCAN2[ n ] is V _ SCAN2_ n.

In a modified embodiment, based on the above pixel unit circuit design, a third capacitor C3 may be added to the circuit to obtain a modified pixel unit circuit as shown in fig. 19, where a first pole of the third capacitor C3 is connected to the gate of the driving transistor Q1, and a second pole of the third capacitor C3 is connected to the anode of the light emitting diode T1.

Other technical features of the pixel unit circuit of this embodiment are consistent with those of the embodiment, and thus are not described again.

The voltage of the anode of the OLED is discharged to the VOLED _ LOW end by the OLED, and when the gray scale is relatively LOW, the discharging current is very small, as small as 2pA, which requires a relatively long discharging time. In particular, if the voltage currently written into the pixel unit is smaller than the voltage previously written into the pixel unit (for example, the display voltage previously written into the gray scale 255, and the display voltage currently written into the gray scale 0), the voltage of the anode of the OLED needs to be slowly discharged to the Voled voltage corresponding to the gray scale 0 by the OLED, which requires a particularly long time. By adding the fourth switching tube Q4, the voltage at the anode of the OLED is discharged as soon as possible through the fourth switching tube Q4 tube to reach the voltage at the V2 terminal. The voltage at the V2 terminal may be VSS or other voltage values below the voltage of the OLED anode at gray level 0. Through the improvement of this embodiment, except accelerating the discharge of OLED positive pole, also let establish the grey scale voltage of OLED positive pole at every turn and can both begin from same starting point voltage, make OLED luminous more accurate.

As shown in fig. 6, which is a timing diagram of the display operation of the pixel unit circuit of this embodiment, after each row of display operations is completed, the fourth transistor Q4 is turned on for a period of time, so that the fourth transistor Q4 completes the discharge of the OLED anode, and then the voltage (V _ DATA _ n _ m-Vds, g) of the OLED anode is established according to the gate voltage (V _ DATA _ n _ m) of the write driver Q1.

The pixel unit circuit display operation timing of this embodiment may be further designed to SCAN2[ n ] ═ SCAN [ n ], and two SCAN signal lines are connected together, both using the signal of SCAN [ n ].

The feedback detection operation of the pixel unit circuit of this embodiment is the same as that shown in fig. 3, wherein the writing of the correction signal follows the display operation timing sequence of this embodiment.

Example three:

fig. 7 shows a pixel unit circuit structure of this embodiment, which includes a second switching tube Q2, a driving tube Q1, a third switching tube Q3, a light emitting diode T1, a fourth switching tube Q4, a fifth switching tube Q5, a first capacitor C1, and a second capacitor C2. In this embodiment, the pixel units in the nth row and the mth column in the off-pixel analog domain compensation display system are taken as an example for description.

The difference between this embodiment and the second embodiment is that the pixel unit circuit of this embodiment is additionally provided with a fifth switch Q5, the gate of the fifth switch Q5 is used for being connected to the inverted display address line EM [ n ] of the second display address line, the first pole of the fifth switch Q5 is connected to the VOLED _ HIGH terminal, the second pole of the fifth switch Q5 is connected to the first pole of the driving transistor Q1, and thus the fifth switch Q5 is connected between the VOLED _ HIGH terminal and the driving transistor Q1.

In a modified embodiment, based on the above pixel unit circuit design, a third capacitor C3 may be added to the circuit to obtain a modified pixel unit circuit as shown in fig. 20, where a first pole of the third capacitor C3 is connected to the gate of the driving transistor Q1, and a second pole of the third capacitor C3 is connected to the anode of the light emitting diode T1.

When the fourth switch transistor Q4 is turned on, there may be useless current flowing from the VOLED _ HIGH terminal to the VOLED _ LOW terminal through the driving transistor Q1 and the fourth switch transistor Q4. The problem can be solved by adding the fifth switch tube Q5, the control signal EM [ n ] of the fifth switch tube Q5 is the inverse of SCAN2[ n ], when the fourth switch tube Q4 is turned on, the fifth switch tube Q5 is turned off and turned on, so that no useless current flows from the VOLED _ HIGH end to the VOLED _ LOW end.

The display operation timing of the pixel unit circuit of the present embodiment is the same as that shown in fig. 6.

The pixel cell circuit feedback detection operation of the present embodiment is identical to that shown in fig. 3, in which the correction signal is written in a new display operation.

Example four:

in the technical field, schemes for compensating an AMOLED display system are divided into in-pixel compensation and out-pixel compensation (or external compensation), an out-pixel compensation method is divided into a real-time compensation method and a non-real-time compensation method, the non-real-time compensation method is divided into a digital domain compensation method and an analog domain compensation method, and the AMOLED display system adopts an analog domain compensation method.

Fig. 8 is a schematic structural diagram of a display system according to fourth to ninth embodiments of the present invention, where the pixel unit according to the first to third embodiments of the present invention is applicable to the display system of fig. 8, fig. 9 is a partial structural diagram of a conventional external compensation display system, each source driver module has two sets of 256 reference voltage signal lines (i.e., signal lines extending from left ends of the first digital-to-analog converter 61 and the second digital-to-analog converter 62 in fig. 9) corresponding to the first digital-to-analog converter 61 and the second digital-to-analog converter 62, one set of reference voltages is V _ disp _0, V _ disp _1.. V _ disp _255, which represent 256 reference voltages with different sizes for the display DAC, and the other set of reference voltages is V _ comp _0, V _ comp _1.. V _ comp _255, which represents 256 reference voltages with different sizes for the compensation DAC. The DAC in each source driving module is only a simple decoding circuit, and after 8-bit digital signals are decoded and input, a corresponding reference voltage is selected from 256 voltages and distributed to an output end. The complete structure of the conventional external compensation display system also adopts the schematic diagram shown in fig. 8. In fig. 8, the display system includes a controller 10, a line scan driver 20, a source driver 30, and a display panel 40, and the controller 10 is connected to the line scan driver 20 and the source driver 30. The controller 10 includes a timing control module 11, a compensation algorithm module 12 and an aging information memory 13 connected in sequence. The source driver 30 includes a first shift-in circuit 34, a second shift-in circuit 35, a shift-out circuit 33, and M detection units 32; the detection unit 32 includes a source driving module 321 and a detection module 322; the source driving module 321 includes a first digital-to-analog converter, a second digital-to-analog converter and an analog adder, and the detecting module 322 includes a comparator.

The display panel 40 comprises N rows and M columns of pixel units 41, and the row scanning driver 20 draws N rows of first display address lines 42 and feedback address lines 43; wherein, the nth row first display address line 42 and the feedback address line 43 are respectively connected to each pixel unit 41 of the nth row; corresponding to the first to third embodiments, the first display address line of the nth row is SCAN [ n ], and V _ SCAN _ n is the display address signal of the nth row; the feedback address line of the nth row is FB _ SCAN [ n ], and V _ FB _ SCAN _ n is the feedback address signal of the nth row; the row scan driver 20 is configured to receive a row control signal from the controller 10 and gate the write channels of the pixel units in the rows 1 to N sequentially through the row 1 to N first display address lines. The pixel units in the first row are respectively numbered as [1,1]. to. [1, M ]. to. [1, M ], the pixel units in the nth row are respectively numbered as [ N,1]. to. [ N, M ], and the pixel units in the nth row are respectively numbered as [ N,1]. to. [ N, M ].

The timing control module 11 is connected to the first shift-in circuit 34, and the first shift-in circuit 34 is connected to the first digital-to-analog converters of all columns in sequence, for example, for the mth column, the timing control module 11, the first shift-in circuit 34, and the mth column first digital-to-analog converters are connected. The compensation algorithm module 12 is connected to the second shift-in circuit 35, and the second shift-in circuit 35 is connected to the second digital-to-analog converters of all columns in sequence, for example, for the mth column, the compensation algorithm module 12, the second shift-in circuit 35, and the mth column second digital-to-analog converter are connected in sequence. The source driving module 321 of the m-th column detection unit 32 is connected to the m-th column display signal line 44 and further connected to each pixel unit 41 of the m-th column, respectively. Corresponding to the first to third embodiments, the display signal line in the mth column is DATA [ m ], and V _ DATA _ n _ m is the display signal of the pixel unit in the mth column in the nth row.

The detection module 322 in the m-th column of the detection unit 32 is respectively connected to each pixel unit 41 in the m-th column through the m-th column feedback signal line 45, and is configured to receive a feedback voltage corresponding to a feedback signal of the pixel unit 41; corresponding to the first to third embodiments, the feedback signal line in the mth column is FB _ DATA [ m ], and V _ FB _ DATA _ n _ m is the feedback signal of the pixel unit in the mth column in the nth row. It should be understood by those skilled in the art that the detection module 322 in the m-th column of detection units 32 can also be used for receiving the feedback current corresponding to the feedback signal of the pixel unit 41, and the same applies to the technical effects of the present invention.

The output terminals of the detection modules 322 in all the column detection units 32 are connected to the shift-out circuit 33, and the shift-out circuit 33 is connected to the aging information memory 13, for example, for the mth column, the output terminals of the detection modules 322 in the mth column detection unit 32, the shift-out circuit 33 and the aging information memory 13 are sequentially connected, so that the output terminals of the mth column detection module 322 compare the feedback voltage with the comparison voltage through the shift-out circuit 33, and the detection result obtained by comparing the feedback voltage with the comparison voltage is fed back to the controller 10 through the shift-out circuit 33.

The M-th row of the pixel units 41 and the M-th row of the detecting units 32 form an M-th row of the driving channels, and the display system is divided into M rows of the driving channels.

The display signal line 44 of each column is provided with a switch sw2, and a switch sw1 is provided between the display signal line 44 and the V1 terminal.

When a correction operation is required, the display system of the present embodiment improves the connection manner on the basis of the conventional external compensation display system shown in fig. 9 to obtain the display system shown in fig. 8 and 10; when the display operation is performed, the connection method shown in fig. 9 may be used. As shown in fig. 8 and 10, the second digital-to-analog converter 62 originally connected to the analog adder 63 in fig. 9 is changed to be connected to the comparator 72 as shown in fig. 10, and the display system of the feedback signal detection method of the present embodiment uses the pixel unit shown in fig. 1, the detection module 322 further includes a current source 73, and the current source 73 of the m-th column detection module 322 is respectively connected to each pixel unit 41 of the m-th column through the m-th column feedback signal line 45. In the mth column source driving module 321, the first dac 61 is connected to the analog adder 63, and the analog adder 63 is connected to the pixel unit 41 of the mth column driving channel through the display signal line 44.

The positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45 and the current source 73, and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter 62 of the mth column source driving module 321.

When the aging phenomenon occurs after the light emitting diode T1 starts emitting light, the threshold voltage of the light emitting diode T1 shifts to a higher value. The display system of this embodiment can detect the threshold voltage of the light emitting diode T1, and first, 2 DACs are configured to be the same linear DAC, and one of the configuration methods is to disable all gamma voltages of the 2 resistor strings; or a selector is used to copy 256 output voltages from the compensation DAC (i.e., the second DAC, assuming the DAC is already linear) resistor string to the output of the display resistor string, and the output of the display resistor string needs to be disabled first, i.e., the command is sent

V_disp_0＝V_comp_0

V_disp_1＝V_comp_1

…

V_disp_255＝V_comp_255。

The feedback signal detection method of the embodiment is used for detecting the threshold voltage of the light emitting diode T1, and includes the following steps:

the first process is as follows: sequentially gating the writing channels of the pixel units in the 1 st row to the Nth row and carrying out detection operation when the writing channel of each row of pixel units is gated;

for the nth row of pixel units, as shown in fig. 11, the process of the detection operation is specifically as follows:

st1, the row scan driver 20 gates the write channel of the nth row of pixel cells.

St2, the pixel unit 41 is controlled to generate a feedback voltage and to control the second digital-to-analog converter 62 to output a comparison voltage.

Specifically, the first switch sw1 is closed, the second switch sw2 is opened, and the driving tube of the mth column is controlled to be turned off and turned on; the display signal line is disconnected from the output terminal of the analog adder, and 0V is input from the low power supply V1 to the display signal line, so that the driving transistor Q1 is turned off and on, and the analog adder 63 and the first digital-to-analog converter 61 are idle.

The result of detecting the threshold voltage of the light emitting diode obtained by the pixel unit 41 in the n-th row and the m-th column stored in the information memory 13 is output to the second digital-to-analog converter 62 in the m-th column, so that the second digital-to-analog converter 62 in the m-th column converts the result into a voltage signal.

The current source 73 outputs a preset small current, which may be 10nA, for example, to the light emitting diode T1 in the nth row and the mth column through the feedback channel. Since the current is small, after the feedback signal line is stabilized, the voltage on the feedback signal line can be considered to be equal to the threshold voltage of the light emitting diode.

The row scan driver 20 gates the feedback channels of the n-th row of pixel cells 41.

The obtained comparison voltage is the voltage obtained by the conversion of the second digital-to-analog converter 62 in the mth column, and the obtained feedback voltage of the pixel unit 41 in the nth row and the mth column is the voltage on the feedback signal line 45 in the mth column.

St3, comparator 72 compares the feedback voltage with the comparison voltage.

St4, the comparator 72 feeds back the detection result obtained by the comparison to the aging information memory 13 through the shift-out circuit 33, and the aging information memory 13 stores the detection result and updates the data.

And a second process: repeating the first process, as the first process is repeated, the input value of the dac 51 will steadily jump between K and K +1 in the following operation, and the final result of the comparison between the feedback voltage and the comparison voltage can be determined.

Those skilled in the art will appreciate that the first process may be repeated over and over again.

Example five:

as shown in fig. 8 and 12, the display system of the present embodiment can detect the threshold voltage of the light emitting diode T1, and the difference of the fourth embodiment is that the pixel unit circuit shown in fig. 5 is adopted in the present embodiment, and other technical features of the display system of the present embodiment are the same as those of the fourth embodiment, and thus are not repeated.

Example six:

as shown in fig. 8 and 13, the display system of the present embodiment can detect the threshold voltage of the light emitting diode T1, and the difference of the fourth embodiment is that the pixel unit circuit shown in fig. 7 is adopted in the present embodiment, and other technical features of the display system of the present embodiment are the same as those of the fourth embodiment, and thus are not repeated.

Example seven:

when a correction operation is required, the display system of the present embodiment improves the connection manner on the basis of the conventional external compensation display system shown in fig. 9 to obtain the display system shown in fig. 8 and 14; when the display operation is performed, the connection method shown in fig. 9 may be used. As shown in fig. 8 and 14, the first digital-to-analog converter 61 and the second digital-to-analog converter 62 originally connected to the analog adder 63 in fig. 9 are respectively connected to the display signal line 44 and the comparator 72 as shown in fig. 14 in the present embodiment, and the display system of the feedback signal detection method of the present embodiment adopts the pixel unit shown in fig. 1; in the mth column source driving module 321, the first dac 61 is connected to the pixel unit 41 of the mth column driving channel through the display signal line 44. The analog adder 63 in the source driver module 321 is idle. Another design scheme is that the left input port of the analog adder 63 is connected to the output of the first dac 61, and the right input port is connected to 0V, so that the output voltage of the analog adder 63 is the output voltage of the first dac 61, which is the same as the design effect of directly connecting the output of the first dac 61 to the display signal line.

The positive input terminal of the comparator 72 in the mth column detection module 322 is connected to the mth column feedback signal line 45, and the negative input terminal of the comparator 72 is connected to the second digital-to-analog converter 62 of the mth column detection unit 32.

The display system of this embodiment can detect the threshold voltage of the driving transistor Q1, and first configure 2 DACs into the same linear DAC, one of the configuration methods is to disable all gamma voltages of 2 resistor strings; or a selector is adopted to copy 256 output voltages of the compensation DAC (namely, the second digital-to-analog converter) resistor string to the output end of the display resistor string, and the output of the original display resistor string needs to be disabled firstly, namely, the command is transmitted

V_disp_0＝V_comp_0

V_disp_1＝V_comp_1

…

V_disp_255＝V_comp_255。

The feedback signal detection method of the embodiment is used for detecting the threshold voltage of the driving tube Q1, and comprises the following processes:

St2, the pixel cell is controlled to generate a feedback voltage and to control the second digital-to-analog converter to output a comparison voltage.

Specifically, the result of the driving tube source voltage Vs obtained by detecting the pixel unit 41 in the n-th row and the m-th column stored in the information memory 13 is output to the second digital-to-analog converter 62 in the m-th column through the second shift-in circuit 35; the second digital-to-analog converter 62 of the mth column is used to convert the result into a voltage signal.

And outputting a second preset display signal to the display signal line of the mth column, so as to turn on the driving tube Q1 and the light emitting diode T1 of the pixel unit 41 of the nth row and the mth column. The second predetermined display signal is a fixed value, such as 255.

The threshold voltage of the driving transistor Q1 is equal to the gate voltage Vg minus the source voltage Vs. The digital signal of the 8-bit DAC corresponding to the gate voltage Vg may be 255, and the digital signal of the 8-bit DAC corresponding to the source voltage Vs is one of the data stored in the aging memory.

The obtained feedback voltage of the pixel unit 41 in the nth row and the mth column is the voltage on the feedback signal line 45 in the mth column, i.e., the source voltage of the driving tube Q1, and the obtained comparison voltage is the voltage converted by the second digital-to-analog converter 62 in the mth column.

St3, comparator 72 compares the feedback voltage with the comparison voltage.

Example eight:

as shown in fig. 8 and fig. 15, the difference between the present embodiment and the seventh embodiment in which the threshold voltage of the driving transistor Q1 can be detected is that the pixel unit circuit shown in fig. 5 is adopted in the present embodiment, and other technical features of the display system of the present embodiment are consistent with those of the seventh embodiment, and thus are not repeated.

Example nine:

as shown in fig. 8 and 16, the difference between the present embodiment and the seventh embodiment in which the threshold voltage of the driving transistor Q1 can be detected is that the pixel unit circuit shown in fig. 7 is adopted in the present embodiment, and other technical features of the display system of the present embodiment are consistent with those of the seventh embodiment, and thus are not repeated.

The schematic diagram of the operation flow of detecting the feedback signal shown in fig. 11 is suitable for describing the detection operation of the display system in the fourth to ninth embodiments, where the fourth, fifth and sixth embodiments are a group, the seventh, eighth and ninth embodiments are a group, and the main difference between the two groups is the St2 process. For convenience of description and analysis, the detection operation herein is directed to the pixel units in the nth row and the mth column, and the pixel units in the nth row and the mth column are used as the target pixel units. The St1 process and the St2 process may be performed simultaneously.

The feedback signal detection method of the present invention includes the following processes:

for the nth row of pixel units, the detection operation process specifically includes:

st1, gating the write channel of the pixel cells of the nth row;

st2, controlling the pixel unit to generate a feedback voltage and controlling the reference dac to output a comparison voltage such that the first input terminal of the comparator receives the feedback voltage and the second input terminal of the comparator receives the comparison voltage;

st3, comparing the feedback voltage with the comparison voltage;

st4, controlling the comparator to feed back the detection result obtained by comparison to the aging information memory through the shift-out circuit;

and a second process: repeating process one, the input value of the dac 51 will steadily jump between K and K +1 in the following operation as process one is repeated. Those skilled in the art will appreciate that the first process may be repeated over and over again.

In the present invention, the positive input terminal of the comparator 72 may be set as the first input terminal, and the negative input terminal may be set as the second input terminal. St3 compares the feedback voltage with the comparison voltage by:

when the row scanning driver 20 performs the writing channel for gating each pixel unit in the nth row in the first scanning, the comparator 72 compares the comparison voltage with the feedback voltage;

if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 1, when the line scan driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to increase by the preset value k; if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 0, when the line scanning driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to be decreased by the preset value k;

after the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result that is inverted for the first time when the line scanning driver 20 performs a certain scanning round, if the result is inverted to 1 to 0 for the first time, when the nth line writing channel is gated next time, the comparison voltage is controlled to be reduced by 1; if the first inversion is 0 to 1, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

the row scanning driver 20 continues to repeatedly perform multiple scanning strobing on the pixel units in the 1 st row to the Nth row, and when the writing channel in the Nth row is strobed again, if the result of the last comparison is 1, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 0, the comparison voltage is controlled to be reduced by 1;

the line scan driver 20 continues to repeatedly perform multiple scanning strobes on the pixel units in the 1 st to nth rows until the writing channel in the nth row is subsequently strobed, and if the result output by comparing the feedback voltage with the comparison voltage with the value of K +1 is 0 and the result output by comparing the feedback voltage with the comparison voltage with the value of K is 1, a certain value between K and K +1 is taken as a final result. For example, an intermediate value between K and K +1, an average value, a value K, or a value K +1 may be used as the detection result, and the solution of the average value includes calculating an arithmetic scheme such as an arithmetic average value or a geometric average value. The operation "take a certain value between K and K +1 as the final result" can be performed by the timing control module 11, and can be determined by the skilled person.

For example, as shown in fig. 17, the display system uses the pixel unit shown in fig. 1, the comparison voltage is a DAC input value, first, a value is selected at the DAC input end, and after the value is assumed to start from 0, the DAC converts the DAC into an analog signal (voltage) corresponding to the value 0 and outputs the analog signal to the negative input end of the comparator 72, and the signal to be detected (i.e., the feedback voltage) is input to the positive input end of the comparator 72. If the result is 0, the selected voltage of the DAC is indicated to be higher, but the input of the DAC is already 0 and can not be lower any more, and the voltage which needs to be detected by the input is indicated to be beyond the detectable range. If 1, it means that the voltage selected by the DAC is not enough, k needs to be added to the input value of the DAC in the next comparison. Where k is an integer other than 0, e.g., 1. If the next round of comparison still yields a 1, the DAC input value is again raised until the output of the comparator 72 is 0, indicating that the voltage corresponding to the input value selected by the DAC has exceeded the detected signal at the positive input of the comparator, which is the first flip.

As shown in fig. 17, the DAC value starts from 0 and the final achieved state should be: when the DAC value rises to K +1, the output result of the comparator 72 is 0, which indicates that the voltage selected by the DAC is larger than the compared voltage, and then the voltage selected by the DAC is reduced by 1 in the next comparison; when the DAC value is reduced to K, the output result of the comparator 72 is 1, which indicates that the voltage selected by the DAC is smaller than the compared voltage, and then the voltage selected by the DAC is added with 1 in the next comparison; the circulation is carried out in such a way to achieve the stability. Finally, the input value of the whole DAC is stabilized to jump between K and K +1, which shows that the compared voltage is between the voltages corresponding to K and K + 1.

Alternatively, the negative input of the comparator 72 may be set as the first input and the positive input may be set as the second input by those skilled in the art according to the actual requirements of the circuit design. Then, St3 compares the feedback voltage with the comparison voltage by:

if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 0, when the line scan driver 20 performs the n-th line writing channel in the second scanning, the comparison voltage is controlled to increase by the preset value k; if the output result of the comparator 72 comparing the comparison voltage with the feedback voltage in the first scanning is 1, controlling the comparison voltage to decrease by a preset value k when the nth row writing channel is gated again in the second scanning by the row scanning driver 20;

after the comparator 72 compares the comparison voltage with the feedback voltage and outputs a result that is inverted for the first time when the line scanning driver 20 performs a certain scanning round, if the result is inverted to 0 to 1 for the first time, when the nth line writing channel is gated next time, the comparison voltage is controlled to be reduced by 1; if the first inversion is 1 to 0, controlling the comparison voltage to increase by 1 when the nth row writing channel is gated next time;

the row scanning driver 20 continues to repeatedly perform multiple scanning strobing on the pixel units in the 1 st row to the Nth row, and when the writing channel in the Nth row is strobed again, if the result of the last comparison is 0, the comparison voltage is controlled to be increased by 1; if the result of the last comparison is 1, the comparison voltage is controlled to be reduced by 1;

the line scan driver 20 continues to repeatedly perform multiple scanning strobes on the pixel units in the 1 st to nth rows until the writing channel in the nth row is subsequently strobed, and if the feedback voltage is compared with the comparison voltage with the value of K +1 to output a result of 1 and the feedback voltage is compared with the comparison voltage with the value of K to output a result of 0, then a certain value between K and K +1 is taken as a final result. For example, an intermediate value between K and K +1, an average value, a value K, or a value K +1 may be used as the detection result, and the solution of the average value includes calculating an arithmetic scheme such as an arithmetic average value or a geometric average value.

The off-pixel analog domain compensation display system according to the fourth embodiment to the ninth embodiment is an off-pixel compensation dual DAC display system, and aging information fed back by a target pixel unit is detected by using a digital-to-analog converter and a comparator of the off-pixel compensation display system in a matched manner, specifically, the threshold voltage of a light emitting device and the threshold voltage of a driving tube in the pixel unit are detected, so that devices such as a TFT, an OLED and a QLED can be detected, and further, the problems of device aging, uneven threshold voltage, uneven driving and the like are analyzed. The prior art has the disadvantages that the pixel unit can only feed back a fixed expected current by using a compensated correction signal, and the aging information detection module compares the current with a reference current and indirectly calculates the aging degree of the pixel unit driving tube. In the invention, the threshold voltage of the pixel unit driving tube and the threshold voltage change condition of the OLED are directly detected by repeatedly using the existing modules (namely the DAC and the comparator).

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. A pixel cell, comprising a first pixel, a second pixel,

the driving circuit comprises a driving tube, a second switching tube, a third switching tube, a light-emitting device, a first capacitor and a second capacitor;

the grid electrode of the second switch tube is used for being connected to a first display address wire, the first pole of the second switch tube is used for being connected to a display signal wire, and the second pole of the second switch tube is connected to the grid electrode of the driving tube and the first pole of the first capacitor;

the second pole of the first capacitor is connected to the ground end of the driving circuit or the cathode of the light-emitting device;

the first pole of the driving tube is connected to a high potential end, and the second pole of the driving tube is connected to the anode of the light-emitting device and the first pole of the third switching tube;

the cathode of the light emitting device is connected to a low potential terminal;

the grid electrode of the third switching tube is used for being connected to a feedback address wire, and the second pole of the third switching tube is used for being connected to a feedback signal wire;

the first pole of the second capacitor is connected to the ground end of the driving circuit, and the second pole of the second capacitor is connected to the low potential end;

the high potential end is a power supply voltage end of the light emitting device, and the low potential end is a negative voltage end with the voltage absolute value smaller than the threshold voltage absolute value of the light emitting device.

2. The pixel cell of claim 1,

the light emitting device is a light emitting diode;

the pixel unit further comprises a second capacitor;

the second capacitor is arranged in the circuit of the pixel unit; or the second capacitor is arranged outside the circuit of the pixel unit and inside the chip where the pixel unit is located; or the second capacitor is arranged outside the chip where the pixel unit is located and on the integrated circuit board where the chip is located.

3. The pixel cell of claim 2,

the device also comprises a fourth switching tube;

the grid electrode of the fourth switching tube is used for being connected to a second display address wire, the first pole of the fourth switching tube is connected to the second voltage end, and the second pole of the fourth switching tube is connected to the anode of the light-emitting device;

the second voltage end is a grounding end; or the voltage value of the second voltage end is lower than the voltage value of the anode of the light-emitting device when the gray scale is 0.

4. The pixel cell of claim 3,

the device also comprises a fifth switching tube;

the grid electrode of the fifth switch tube is used for being connected to an inverted display address wire of the second display address wire, the first pole of the fifth switch tube is connected to the high potential end, and the second pole of the fifth switch tube is connected to the first pole of the driving tube;

the second switching tube, the driving tube, the third switching tube, the fourth switching tube and/or the fifth switching tube are/is N-shaped tubes; the first pole is a source electrode, and the second pole is a drain electrode; alternatively, the first pole is a drain and the second pole is a source.

5. The pixel cell of any of claims 1-4,

the pixel unit further comprises a third capacitor;

the first pole of the third capacitor is connected to the grid electrode of the driving tube, and the second pole of the third capacitor is connected to the anode of the light-emitting device.

6. An off-pixel analog domain compensation display system is characterized in that,

comprises M rows of driving channels;

each column of drive channels comprising a detection unit (32) and a pixel unit (41) according to any one of claims 1-5; the detection unit (32) comprises a source driving module (321) and a detection module (322); the detection module (322) comprises a comparator (72);

the system is an off-pixel compensation double-digital-to-analog converter display system, and a first digital-to-analog converter (61) and a second digital-to-analog converter (62) are arranged in the source driving module (321);

the source driving module (321) is connected to the pixel unit (41) through a display signal line (44);

a first input end of the comparator (72) is connected to the pixel unit (41) through a feedback signal line (45) and is used for receiving a feedback voltage corresponding to a feedback signal of the pixel unit (41); a second input terminal of the comparator is connected to the second digital-to-analog converter (62) for receiving the comparison voltage output by the second digital-to-analog converter (62); the output end of the comparator (72) is used for outputting a detection result obtained by comparing the feedback voltage with the comparison voltage;

wherein M is an integer of 1 or more.

7. The system of claim 6,

the display device also comprises a controller (10), a line scanning driver (20), a source driver (30) and a display panel (40);

the controller (10) is connected to the line scan driver (20) and the source driver (30);

the display panel (40) is provided with N rows and M columns of pixel units (41), and the row scanning driver (20) leads out N rows of first display address lines (42) and feedback address lines (43); wherein, the first display address line (42) and the feedback address line (43) of the nth row are respectively connected to each pixel unit (41) of the nth row; the row scanning driver (20) is used for receiving row control signals of the controller (10) and gating write-in channels of the pixel units in the 1 st row to the Nth row through first display address lines in the 1 st row to the Nth row in sequence;

the source driver (30) comprises a first shift-in circuit (34), a second shift-in circuit (35), a shift-out circuit (33) and M detection units (32);

the controller (10), the first shift-in circuit (34) and a first digital-to-analog converter (61) in the mth column source driving module (321) are sequentially connected;

the controller (10), the second shift-in circuit (35) and a second digital-to-analog converter (62) in the m-th column source driving module (321) are sequentially connected;

the controller (10) is used for controlling a second digital-to-analog converter (62) in the mth column source driving module (321) to output a comparison voltage;

the output end of the m column comparator (72) is connected to the controller (10) through the shift-out circuit (33) and used for feeding back the detection result to the controller (10) through the shift-out circuit (33);

wherein N is an integer greater than or equal to 1, and N is an integer greater than or equal to 1 and less than or equal to N; m is an integer of 1 to M.

8. The system of claim 7,

the controller (10) comprises a time sequence control module (11), a compensation algorithm module (12) and an aging information memory (13) which are connected in sequence;

the time sequence control module (11), the first shift-in circuit (34) and a first digital-to-analog converter (61) in the mth column source driving module (321) are sequentially connected;

the compensation algorithm module (12), the second shift-in circuit (35) and a second digital-to-analog converter (62) in the m-th column source driving module (321) are connected in sequence;

the output end of the m-th row comparator (72), the shift-out circuit (33) and the aging information memory (13) are connected in sequence.

9. The system of claim 7 or 8,

the first input end of the comparator (72) is a positive input end, and the second input end is a negative input end;

when the row scanning driver (20) gates a writing channel of the pixel units of the nth row, the comparator (72) is used for comparing the comparison voltage with the feedback voltage;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to increase by a preset value k; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to be reduced by a preset value k;

when the comparator (72) firstly inverts the comparison voltage and the feedback voltage to output a result, and if the result is inverted to 1 to 0 for the first time, the controller (10) controls the comparison voltage to be reduced by 1 when the nth row writing channel is next gated; if the first inversion is 0 to 1, when the nth row writing channel is gated next time, the controller (10) controls the comparison voltage to increase by 1;

when the nth row writing channel is gated again, if the last comparison result is 1, the controller (10) controls the comparison voltage to increase by 1; if the last comparison result is 0, the controller (10) controls the comparison voltage to be reduced by 1;

until the nth row of write channels is subsequently gated, comparing the feedback voltage with the comparison voltage with the value of K +1 to output a result of 0 and comparing the feedback voltage with the comparison voltage with the value of K to output a result of 1, and taking a certain value between K and K +1 as a final result;

or the first input end of the comparator (72) is a negative input end, and the second input end is a positive input end;

if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 0, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to increase by a preset value k; if the comparator (72) compares the comparison voltage with the feedback voltage and outputs a result of 1, when the nth row writing channel is gated again, the controller (10) controls the comparison voltage to be reduced by a preset value k;

when the comparator (72) firstly inverts the comparison voltage and the feedback voltage to output a result, and if the result is inverted to 0 to 1 for the first time, the controller (10) controls the comparison voltage to be reduced by 1 when the nth row writing channel is gated next time; if the first inversion is 1 to 0, when the nth row writing channel is gated next time, the controller (10) controls the comparison voltage to increase by 1;

when the nth row writing channel is gated again, if the last comparison result is 0, the controller (10) controls the comparison voltage to increase by 1; if the result of the last comparison is 1, the controller (10) controls the comparison voltage to be reduced by 1;

until the nth row of write channels is subsequently gated, comparing the feedback voltage with the comparison voltage with the value of K +1 to output a result of 1 and comparing the feedback voltage with the comparison voltage with the value of K to output a result of 0, and taking a certain value between K and K +1 as a final result;

wherein K is a natural number greater than 0, and K is a natural number greater than 0.

10. The system of claim 8,

in the mth column of source driving modules (321), the first digital-to-analog converter (61) is connected to an analog adder (63), and the analog adder (63) is connected to the pixel units (41) of the mth column of driving channels through display signal lines (44);

the detection module (322) further comprises a current source (73), the current source (73) in the mth column is connected to each pixel unit (41) in the mth column through a feedback signal line (45) in the mth column;

the row scanning driver (20) is used for gating a writing channel of the pixel units (41) of the nth row;

the time sequence control module (11) is used for controlling the driving tubes in the mth row of driving channels to be switched on and off;

the compensation algorithm module (12) is used for outputting the result of the threshold voltage of the light-emitting device, which is stored in the aging information memory (13) and obtained by detecting the pixel units (41) in the n-th row and the m-th column, to the second digital-to-analog converter (62) in the m-th column through the second shift-in circuit (35); a second digital-to-analog converter (62) of the mth column for converting the result into a voltage signal;

the current source (73) is used for outputting preset current to the light emitting device of the mth column;

the row scanning driver (20) is also used for gating a feedback channel of the pixel unit (41) of the nth row;

the m-th row comparator (72) is used for comparing a feedback voltage with a comparison voltage and feeding back a detection result to the aging information memory (13) through the shift-out circuit (33);

the feedback voltage of the pixel unit (41) in the nth row and the mth column is the voltage on the feedback signal line (45) in the mth column, and the comparison voltage is the voltage converted by the second digital-to-analog converter (62) in the mth column.

11. The system of claim 8,

in the mth column source driving module (321), the first digital-to-analog converter (61) is connected to the pixel unit (41) of the mth column driving channel through a display signal line (44);

the time sequence control module (11) is used for outputting a second preset display signal to an mth column display signal line so as to conduct a driving tube and a light-emitting device of the pixel unit (41) in the nth row and the mth column;

the compensation algorithm module (12) is used for outputting the result of the driving tube source voltage obtained by detecting the pixel units (41) in the nth row and the mth column stored in the aging information memory (13) to a second digital-to-analog converter (62) in the mth column through the second shift-in circuit (35); a second digital-to-analog converter (62) of the mth column for converting the result into a voltage signal;