TW202147288A - Pixel compensation circuit - Google Patents

Abstract

A pixel compensation circuit, including a light emitting diode, a driving unit, a control unit, a data writing unit, a reset unit, and a pulldown unit, is disclosed. The driving unit is connected to the light emitting diode and a first node. The control unit is connected to the first node. The data writing unit is connected to the control unit. The reset unit is connected to the first node. The pull down unit is connected to the control unit. The control unit is further configured to control a voltage decrease time of the first node according to the data voltage value received by the data writing unit to adjust gray scale of the light emitting diode. The data writing unit includes a first transistor, a second transistor, a second transistor, a third transistor, and a first capacitor. A first terminal of the first transistor is connected to a first voltage source, and a second terminal of the first transistor is connected to a second node. A first end of the second transistor is connected to the second node, and a second end of the second transistor is connected to a third node. A first terminal and a control terminal of the third transistor are connected to the third node, and a second terminal of the third transistor is connected to a data input source. A first terminal of the first capacitor is connected to the second node, and a second terminal of the first capacitor is connected to a first reference voltage source.

Description

pixel compensation circuit

The contents of the embodiments described in the present disclosure relate to a pixel compensation circuit, especially a pixel compensation circuit that utilizes a constant current to purchase grayscales of light-emitting diodes.

In order to produce LED backlight panels with uniform brightness, many methods have been proposed. However, when outputting high brightness, the voltage drop generated by the large current flowing through the driving transistor may lead to difficulty in current control. Although the problem of difficult current control can be solved by increasing the voltage across the driving transistor, it will increase power consumption. In addition, since micro-sized light-emitting diodes (mini LEDs) require larger driving currents than general organic light-emitting diodes, the voltage source is easily offset due to the wire resistance in the transmission path, resulting in the voltage source of each pixel. The voltages at the terminals are different, resulting in an error in the output current.

Some embodiments of the present disclosure relate to a pixel compensation circuit including a light emitting diode, a driving unit, a control unit, a data writing unit, a reset unit, and a pull-down unit. The driving unit is connected to the light emitting diode and the first node. The control unit is connected to the first node. The data writing unit is connected to the control unit. The reset unit is connected to the first node. The pull-down unit is connected to the control unit. The control unit is further used for controlling the voltage falling time of the first node according to the data voltage value received by the data writing unit, so as to adjust the gray scale of the light emitting diode. The data writing unit includes a first transistor, a second transistor, a second transistor, a third transistor and a first capacitor. The first end of the first transistor is connected to the first voltage source, and the second end of the first transistor is connected to the second node. The first end of the second transistor is connected to the second node, and the second end of the second transistor is connected to the third node. The first terminal and the control terminal of the third transistor are connected to the third node, and the second terminal of the third transistor is connected to the data input source. The first end of the first capacitor is connected to the second node, and the second end of the first capacitor is connected to the first reference voltage source.

As used herein, the term "coupled" may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected." "Coupled" and "connected" may also refer to two or more elements cooperating or interacting with each other.

Refer to Figure 1. FIG. 1 is a schematic diagram of a pixel compensation circuit 100 according to some embodiments of the present disclosure.

Taking the example of FIG. 1 as an example, the pixel compensation circuit 100 includes a light emitting diode 105 , a driving unit 110 , a pull-down unit 130 , a reset unit 150 , a control unit 170 and a data writing unit 190 .

In terms of connection, the light emitting diode 105 is connected to the driving unit 110 . The driving unit 110 , the reset unit 150 and the control unit 170 are all connected to the node A. The pull-down unit 130 is connected with the control unit 170 . The data writing unit 190 is connected to the control unit 170 .

In detail, the driving unit 110 includes a transistor 110 . The pull-down unit 130 includes a transistor T2 and a transistor T3. The reset unit 150 includes a transistor T5. The control unit 170 includes transistors T4, T6, T7, T8, T9 and capacitors C1 and C3. The data writing unit 190 includes transistors T10, T11, T12 and a capacitor C2.

In terms of connection, one end of the light emitting diode 105 is connected to the voltage source VDD, and the other end of the light emitting diode 105 is connected to the transistor T1. One end of the transistor T1 is connected to the light emitting diode 105 , the other end of the transistor T1 is connected to the voltage source VSS, and the control end of the transistor T1 is connected to the node A.

One end of the transistor T2 is connected to the low voltage source VL, and the other end of the transistor T2 is connected to the node B. The control terminal of the transistor T2 receives the control signal S3. One end of the transistor T3 is connected to the node B, the other end of the transistor T3 is connected to the voltage source VSS, and the control end of the transistor T3 receives the control signal S4.

One end of the transistor T5 is connected to the voltage source VSS, the other end of the transistor T5 is connected to the node A, and the control end of the transistor T5 receives the control signal S5.

One end of the transistor T4 is connected to the node A, the other end of the transistor T4 is connected to the node D, and the control end of the transistor T4 receives the control signal S3. One end of the transistor T6 is connected to the node A, the other end of the transistor T6 is connected to the node C, and the control end of the transistor T6 is connected to the node D. One end of the transistor T7 is connected to the node D, the other end of the transistor T7 is connected to the reference voltage source VLED, and the control end of the transistor T7 receives the control signal S4. One end of the transistor T8 is connected to the reference voltage source VREF, the other end of the transistor T8 is connected to the node C, and the control end of the transistor T8 is connected to the node E. One end of the transistor T9 is connected to the high voltage source VH, the other end of the transistor T9 is connected to the node C, and the control end of the transistor T9 receives the control signal S2. One end of the capacitor C1 is connected to the node A, and the other end of the capacitor C1 is connected to the node B. One end of the capacitor C3 is connected to the node C, and the other end of the capacitor C3 is connected to the reference voltage source VLED.

One end of the transistor T10 is connected to the voltage source VSS, the other end of the transistor T10 is connected to the node E, and the control end of the transistor T10 receives the control signal S1. One end of the transistor T11 is connected to the node E, the other end of the transistor T11 is connected to the node F, and the control end of the transistor T11 receives the control signal S2. One end of the transistor T12 is connected to the node F, the other end of the transistor T12 is connected to the data input source VDATA, and the control end of the transistor T12 is connected to the node F. One end of the capacitor C2 is connected to the node E, and the other end of the capacitor C2 is connected to the reference voltage source VLED.

Please refer to Figure 2. FIG. 2 is a schematic diagram illustrating an operation sequence 200 of the pixel compensation circuit 100 according to some embodiments of the present disclosure. The operation method of the pixel compensation circuit 100 of FIG. 1 will be described with reference to FIGS. 3 to 7 .

Please refer to Figure 3. FIG. 3 is a schematic diagram illustrating the operation of the pixel compensation circuit 100 in FIG. 1 during the time interval TP1 in FIG. 2 according to some embodiments of the present disclosure. The time interval TP1 is the reset time interval. During the time interval TP1, the control signals S1, S2 and S4 are at the low voltage value VGL, the control signals S3 and S5 are at the high voltage value VGH, and the reference voltage source VREF is at the high voltage value VREF_H.

Since the control signals S1 , S2 , and S4 are of low voltage value VGL, the transistors T3 , T7 , T9 , T10 , and T11 are not turned on, while the transistors T2 , T4 and T5 are turned on. After the transistors T4 and T5 are turned on, the voltage value of the node A is the voltage value V_SS of the voltage source VSS. Since the voltage value V_SS of the voltage source VSS is a low voltage value, the transistor T1 is not turned on. In addition, since the transistor T2 is turned on, the voltage value of the node B is the voltage value V_L of the low voltage source VL.

Please refer to Figure 4. FIG. 4 is a schematic diagram illustrating the operation of the pixel compensation circuit 100 in FIG. 1 during the time interval TP2 in FIG. 2 according to some embodiments of the present disclosure. The time interval TP2 is a compensation time interval. During the time interval TP2, the control signals S1 and S3 are at the high voltage value VGH, the control signals S2, S4 and S5 are at the low voltage value VGL, and the reference voltage source VREF is at the high voltage value VREF_H.

Since the control signals S2, S4 and S5 are at the low voltage value VGL, the transistors T3, T5, T7, T9 and T11 are not turned on. Since the control signals S1 and S3 are high voltage values VGH, the transistors T2, T4 and T10 are turned on. Since the transistor T10 is turned on, the voltage value of the node E is the voltage value V_SS of the voltage source VSS. At this time, the voltage value of the node E is reset, and the transistor T8 is turned on. At this time, the voltage value of the node C is the voltage value VREF_H of the voltage source VREF. The voltage value of the node A and the node D is the voltage value VREF_H plus the threshold voltage VTH_T6 of the transistor T6. At this time, the transistor T6 performs matching compensation for the threshold voltage of the transistor T1.

Please refer to Figure 5. FIG. 5 is a schematic diagram illustrating the operation of the pixel compensation circuit 100 in FIG. 1 during the time interval TP3 in FIG. 2 according to some embodiments of the present disclosure. The time interval TP3 is the compensation time interval. During the time interval TP3, the control signals S2 and S3 are at the high voltage value VGH, the control signals S1, S4 and S5 are at the low voltage value VGL, and the reference voltage source VREF is at the high voltage value VREF_H.

Since the control signals S1 , S4 , and S5 are of the low voltage value VGL, the transistors T3 , T5 , T7 , and T10 are not turned on. Since the control signals S2 and S3 are high voltage values VGH, the transistors T4, T9, T11 and T12 are turned on. The voltage value of the node C is the voltage value V_H of the high voltage source VH. Current flows from node E to voltage source VDATA. The voltage value of the node E is the voltage value V_DATA of the voltage source VDATA plus the threshold voltage VTH_T12 of the transistor T12. At this time, the transistor T12 performs matching compensation for the threshold voltage of the transistor T8. In addition, since the transistor T2 is turned on, the voltage value of the node B is the voltage value V_L of the high voltage source VL.

Please refer to Figure 6. FIG. 6 is a schematic diagram illustrating the operation of the pixel compensation circuit 100 in FIG. 1 during the time interval TP4 in FIG. 2 according to some embodiments of the present disclosure. The time period TP4 is the light emission time period.

During the time interval TP4, the voltage value of the control signal S4 is the high voltage value VGH, and the voltage values of the control signals S1, S2, S3, and S5 are the low voltage value VGL. The reference voltage source VREF is a low voltage value VREF_L.

Since the voltage values of the control signals S1 , S2 , S3 , and S5 are the low voltage values VGL, the transistors T2 , T4 , T5 , T9 , T10 , and T11 are not turned on. Since the voltage value of the control signal S4 is the high voltage value VGH, the transistors T3 and T7 are turned on. The voltage value of node B rises from V_L to V_SS. Since node A is floating, the voltage value of node A is V_SS-V_L+VREF_H+VTH_T6 at this time. The transistor T1 is turned on.

After the transistor T1 is turned on, the current value flowing through the light-emitting diode 105 is 0.5k(VREF_H-V_L) ² .

Since the voltage value of the node E is V_DATA+VTH_V12 and the reference voltage source VREF is the low voltage value VREF_L, the transistor T8 is turned on. After the transistor T8 is turned on, the current flows from the node C to the reference voltage source VREF. At this time, the magnitude of the current flowing through the transistor T8 is 0.5k(V_DATA-VREF_L) ² . The constant current flowing through the transistor T8 discharges the node C, and the voltage value of the node C gradually decreases.

Please refer to Figure 7. FIG. 7 is a schematic diagram illustrating the operation of the pixel compensation circuit 100 in FIG. 1 during the time interval TP4 in FIG. 2 according to some embodiments of the present disclosure. Continue the operation in Figure 6. When the voltage value of the node C gradually decreases below the voltage value of the node D minus the threshold voltage VTH_T6 of the transistor T6, the transistor T6 enters the linear region. At this time, the voltage value of node A is equal to the voltage value of node C. The voltage value at node C is V_H minus ΔV. ΔV is the voltage value at which the current flowing through the transistor T8 discharges the node C and causes the node C to drop.

After the transistor T6 is turned on, the voltage value of the node A gradually decreases. When the voltage value of the node A is less than the voltage value V_SS plus the threshold voltage VTH_T1 of the transistor T1, the transistor T1 is turned off.

The constant current flowing through the transistor T8 continues to discharge the node C until the voltage value of the node C reaches VREF_L plus the threshold voltage VTH_T8 of the transistor T8.

According to the above paragraphs, the voltage value V_DATA will affect the magnitude of the constant current passing through the transistor T8, and further affect the voltage drop time of the node A. By controlling the voltage drop time of the node A, the gray scale of the light emitting diode 105 can be controlled.

Please refer back to Figure 2. During the time interval TP5, the control signals S1, S2 and S4 are at the low voltage value VGL, the control signals S3 and S5 are at the high voltage value VGH, and the reference voltage source VREF is at the high voltage value VREF_H. The time interval TP5 is the same as the time interval TP1, both are reset time intervals, and the operations of the time interval TP5 and the time interval TP1 are the same, and the description is not repeated here.

In practice, the transistors T1 to T12 in FIG. 1 can be implemented by P-type low temperature polysilicon thin film transistors, but this embodiment is not limited to this. For example, the transistors T1 to T12 can also be implemented with P-type amorphous silicon thin film transistors. In some embodiments, N-type thin film transistors can also be used to implement, and the present invention does not limit the type of transistors used.

According to the above paragraphs, in the embodiments of the present application, a 12T3C circuit structure is proposed, and the circuit structure is applied to the Mini LED backlight panel. In the embodiment of this case, the light-emitting time of the light-emitting diode is determined by constant current discharge to control the gray scale of the light-emitting diode, and the VDD-VSS required by the circuit can be reduced by reducing the number of transistors on the light-emitting path. Overvoltage, so that the light-emitting diode can achieve the highest luminous efficiency and reduce power consumption. In addition, by compensating for the variation of the threshold voltage of the transistor and the increase of the IR of the VSS, the magnitude of the light-emitting current can be made more precise.

Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection shall be determined by the scope of the appended patent application.

100: pixel compensation circuit 105: Light Emitting Diodes 110: Drive unit 130: Pull down unit 150: Reset Unit 170: Control Unit 190:Data writing unit T1,T2,T3,T4,T5,T6,T7,T8,T9,T10,T11,T12: Transistor C1, C2, C3: Capacitors S1, S2, S3, S4, S5: control signal A,B,C,D,E,F: Nodes VL: voltage source VH: Voltage source VSS: Voltage Source VDD: voltage source VLED: Voltage source VDATA: voltage source VREF: Voltage source 200: Operation timing TP1,TP2,TP3,TP4,TP5: time interval VREF_H, VREF_L: Voltage value VGH, VGL: voltage value

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows: FIG. 1 is a schematic diagram of a startup system according to some embodiments of the present disclosure; FIG. 2 is a schematic diagram illustrating the operation timing of the pixel compensation circuit according to some embodiments of the present disclosure; FIG. 3 is a schematic diagram illustrating the operation of the pixel compensation circuit in FIG. 1 in the time interval of FIG. 2 according to some embodiments of the present disclosure; FIG. 4 is a schematic diagram illustrating the operation of the pixel compensation circuit in FIG. 1 in the time interval of FIG. 2 according to some embodiments of the present disclosure; FIG. 5 is a schematic diagram illustrating the operation of the pixel compensation circuit in FIG. 1 in the time interval of FIG. 2 according to some embodiments of the present disclosure; 6 is a schematic diagram illustrating the operation of the pixel compensation circuit in FIG. 1 during the time interval in FIG. 2 according to some embodiments of the present disclosure; and FIG. 7 is a schematic diagram illustrating the operation of the pixel compensation circuit in FIG. 1 in the time interval of FIG. 2 according to some embodiments of the present disclosure.

100: pixel compensation circuit

105: Light Emitting Diodes

110: Drive unit

130: Pull down unit

150: Reset Unit

170: Control Unit

190:Data writing unit

T1,T2,T3,T4,T5,T6,T7,T8,T9,T10,T11,T12: Transistor

C1, C2, C3: Capacitors

S1, S2, S3, S4, S5: control signal

A,B,C,D,E,F: Nodes

VL: voltage source

VH: Voltage source

VSS: Voltage Source

VDD: voltage source

VLED: Voltage source

VDATA: voltage source

VREF: Voltage source

Claims (10)

A pixel compensation circuit, comprising: a light-emitting diode; a driving unit connected to the light-emitting diode and a first node; a control unit, connected to the first node; a data writing unit, connected to the control unit; a reset unit connected to the first node; and A pull-down unit, connected to the control unit; wherein the control unit is further configured to control a voltage drop time of the first node according to a data voltage value received by the data writing unit, so as to control a gray scale of the light emitting diode; The data writing unit includes: a first transistor, wherein a first end of the first transistor is connected to a first voltage source, and a second end of the first transistor is connected to a second node; a second transistor, wherein a first end of the second transistor is connected to the second node, and a second end of the second transistor is connected to a third node; a third transistor, wherein a first terminal and a control terminal of the third transistor are connected to the third node, and a second terminal of the third transistor is connected to a data input source; and a first capacitor, wherein a first end of the first capacitor is connected to the second node, and a second end of the first capacitor is connected to a first reference voltage source. The pixel compensation circuit of claim 1, wherein in a reset time interval, the reset unit is further configured to reset a voltage value of the first node. The pixel compensation circuit of claim 1, wherein the driving unit comprises: a fourth transistor, a first end of the fourth transistor is connected to the light-emitting diode, a second end of the fourth transistor is connected to the first voltage source, a control of the fourth transistor The terminal is connected to the first node. The pixel compensation circuit of claim 3, wherein the pull-down unit comprises: a fifth transistor, wherein a first end of the fifth transistor is connected to a low voltage source, and a second end of the fifth transistor is connected to a fourth node; and a sixth transistor, wherein a first end of the sixth transistor is connected to the fourth node, and a second end of the sixth transistor is connected to the first voltage source. The pixel compensation circuit of claim 4, wherein the reset unit further comprises: A seventh transistor, wherein a first end of the seventh transistor is connected to the first voltage source, and a second end of the seventh transistor is connected to the first node. The pixel compensation circuit of claim 5, wherein the control unit further comprises: an eighth transistor, wherein a first end of the eighth transistor is connected to the first node, and a second end of the eighth transistor is connected to a second node; a ninth transistor, wherein a first end of the ninth transistor is connected to the first node, a second end of the ninth transistor is connected to a third node, and a control end of the ninth transistor connected to the second node; a tenth transistor, wherein a first end of the tenth transistor is connected to the first reference voltage source, and a second end of the tenth transistor is connected to the second node; an eleventh transistor, wherein a first end of the eleventh transistor is connected to the third node, a second end of the eleventh transistor is connected to a second reference voltage source, the eleventh transistor a control end of the transistor is connected to the second node; a twelfth transistor, wherein a first end of the twelfth transistor is connected to a high voltage source, and a second end of the twelfth transistor is connected to the third node; a second capacitor, wherein a first end of the second capacitor is connected to the fourth node, and a second end of the second capacitor is connected to the fourth node; and a third capacitor, wherein a first end of the third capacitor is connected to the third node, and a second end of the third capacitor is connected to the first reference voltage source. The pixel compensation circuit of claim 6, wherein in a reset time interval, the eighth transistor and the seventh transistor are turned on to reset the voltage value of the first node to the voltage value of the first voltage source Voltage value. The pixel compensation circuit of claim 6, wherein in a first compensation time interval, the second reference voltage source is a high voltage value, the first transistor and the eighth transistor are turned on, so that the first transistor is turned on. The ninth transistor is connected to the eleventh transistor, and a threshold voltage of the fourth transistor is compensated by the ninth transistor. The pixel compensation circuit of claim 8, wherein in a second compensation time interval, the fifth transistor, the eighth transistor, the twelfth transistor, the second transistor and the third transistor The crystal is turned on to compensate a threshold voltage of the eleventh transistor with the third transistor. The pixel compensation circuit of claim 6, wherein in a light-emitting time interval, the eleventh transistor is turned on, so that the voltage value of the third node is gradually reduced to turn on the ninth transistor, and the ninth transistor is turned on. After the transistor is turned on, a voltage value of the first node gradually decreases. When the voltage value of the first node is less than a turn-on threshold, the fourth transistor is turned off, so that the light emitting diode is not turned on.

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