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TWI351729B - Semiconductor device and method for fabricating th - Google Patents

Semiconductor device and method for fabricating th Download PDF

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Publication number
TWI351729B
TWI351729B TW096124083A TW96124083A TWI351729B TW I351729 B TWI351729 B TW I351729B TW 096124083 A TW096124083 A TW 096124083A TW 96124083 A TW96124083 A TW 96124083A TW I351729 B TWI351729 B TW I351729B
Authority
TW
Taiwan
Prior art keywords
layer
metal
bump
wafer
carrier
Prior art date
Application number
TW096124083A
Other languages
English (en)
Other versions
TW200903670A (en
Inventor
Jeng Yuan Lai
Chien Ping Huang
Chun Chi Ke
Yu Po Wang
Chiao Hung Yen
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW096124083A priority Critical patent/TWI351729B/zh
Priority to US12/217,365 priority patent/US20090008801A1/en
Publication of TW200903670A publication Critical patent/TW200903670A/zh
Application granted granted Critical
Publication of TWI351729B publication Critical patent/TWI351729B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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1351729 f 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置及其製法，尤指一種 覆晶薄膜（COF)之半導體裝置及其製法。 【先前技術】 目前運用軟質承載板作為封裝晶片載體以將晶片與軟 性基板電性連接之習知技術中，其可大約分為捲帶式自動 封裝（Tape Carrier Bonding,TCP)以及覆晶薄膜（Chip 〇n _ Film，COF)等技術。其中，為改善捲帶式自動封裝（Tcp) .之散熱問題，如美國專利第6,297,074、、 .4,849,857、5,095,404等專利揭示於晶片之主動面或非主動 面上貼附導熱件，以藉由該導熱件逸散晶片運作時所產生 之熱量。 然而，由於傳統之捲帶式自動封裝（Tcp)技術中，其最 小引線間距（lead pitch)僅於35微米以叫，無法滿足業界 #對於更小間距的需求，為此，業界遂開發一種可提供更小 弓丨線間距之覆晶薄膜(C0F)技術’依目前業界之覆晶薄膜 (COF)能力，其最小引線間距可至⑼微米，相關技術内容 係可參閱美國專利g 6,710,458、6 559 524、Μ64,ιΐ9等 專利所揭示。 請參閱第4A至4J圖，係為習知覆晶薄膜（c〇F)半導 體裝置之製法示意圖。首先，如第4A^4D圖所示，提供 具有設有複數鋒墊4〇1之晶片400,該晶片4〇〇上覆蓋有 一絕緣層410’且該絕緣層410中形成有開孔4u，以外露 110358 5 1351729 t 出該些銲墊401，藉以於該絕緣層410及其開孔411表面 以如藏鑛（sputtering)之技術形成如鈦化鎮（Ti/W)之第一導 電層420及金(Au)之第二導電層430。 接著，於該第二導電層430上覆蓋一阻層440，並形 成有複數開口 441以外露出該第二導電層430，以於該些 阻層開口 441中以如電鍍之方式形成如金（Au)之金屬凸塊 (Au bump)450，之後移除該阻層440及其覆蓋之第一及第 二導電層420,430。 _ 如第4E至41圖所示，提供軟質載板500，並於該載 板500之表面上以如藏鐘之方式形成如銅（Cu)之導電層 510，再於該導電層510上形成阻層520，並於該阻層520 中形成複數對應該晶片400之金屬凸塊450之開口 521， 接著，於該阻層開口 521中以如電鍍之方式形成如銅/錫 (Cu/Sn)或銅/錫/金（Cu/Sn /Au)之金屬引線層530，以製得 細間距之引線（fine pitch lead)，接著再移除該阻層520及 I其覆蓋之導電層510，再將防銲層550覆蓋於該載板500 上且外露出該金屬引線層530。 如第4J圖所示，將該晶片400與該載板500藉由熱壓 (thermal compression)方式相接合，亦即將該晶片之金屬凸 塊（Au bump)450與該載板之金屬引線層（Sn)530形成共金 結構而相互電性連接，之後再利用覆晶底部填膠材料 (underfill) 600填充該晶片400及載板500間隙，以形成覆 晶薄膜（COF)半導體裝置。 此方法雖可較前述捲帶式自動封裝（TCP)技術提供更 6 110358 1351729 « ，細之引線間距：惟其結構上之變化而導致習知導熱方式無 法應用於覆晶i#膜（COF)半導體裝置上，因此將造成散熱 性不佳之問題。更甚者’由於該覆晶薄膜（c〇f)半導體裝 置係以捲帶式（feel to reel)方式來生產，如利用外加之散熱 件黏附於晶片上，將造成無法捲帶，或於捲帶上造成散敎 件之損壞。 因此，鑑於上述問題，如何提供覆晶薄膜（c〇f)之半 導體裝置良好散熱效果，實已成為目前業界亟欲解決之課 題。 【發明内容】 鑑於前述習知技術之缺失，本發明之一目的係提供一 種半導體裝置及其製法，可供覆晶薄膜（C0F)之半導體裝 置有效逸散晶片運件時產生之熱量。 本發明之另一目的係提供一種半導體裝置及其製法， 以供覆晶薄膜（C0F)半導體裝置良好散熱效果，同時避免 鲁以捲帶式（reeltoreeI)方式生產時，因使用外加散熱件造成 無法捲帶或於捲帶上發生散熱件損壞問題。 為達上述及其它目的，本發明揭露一種半導體裝置之 製法，係包括：提供具有相對主動面及非主動面之晶片與 具有相對第一表面及第二表面之軟質載板，該晶片主動面 上設有複數銲墊’且各該銲墊上形成有金屬凸塊，並於該 些金屬凸塊間形成有散熱凸塊，該軟質載板第一表面形成 有相對應該金屬凸塊之金屬引線層及對應該散熱凸塊之第 一散熱金屬層，並於該第二表面上形成有第二散熱金屬 Π0358 7 1351729 » 層^將該晶片之主動面接置於該軟質載板之第一表面，且 使該晶片主動面上之金屬凸塊與散熱凸塊電性連接至對應 該金屬引線層及第-散熱金屬層；以及於該晶片與: 板間隙填充絕緣膠。 .、 2晶片之金屬凸塊及散熱凸塊之製法係包括：提供表 :覆盍有絕緣層之晶片，且該絕緣層形成有複數開孔以外 路$晶片銲墊；於該絕緣層及其開孔表面形成導電層；於 該導電2上覆蓋阻層’並於該阻層巾形成複數對應該鲜塾 位置之第一開口，及於該些第一開口間形成第二開口，以 夕卜露出該導電層；以及於㈣—及第二開口中電鐘形成金 凸塊及散熱凸塊，並移除該阻層及其覆蓋之導電層。 該軟質載板之金屬引線層、第一及第二散熱金^層之 衣法係包括：提供具有相對第—及第二表面之軟質載板， 於，軟質載板第-及第二表面形成導電層；於該導電層上 覆蓋阻層’並令該阻層於軟質載板第一表面形成有對‘晶 片金屬凸塊及散熱凸塊之第三及第四開口，以及於第二表 面形成有第五開口；於該第三及第四開口中電鍍形成金屬 引:線層及第一散熱_，並於該第五開口中電鍍形成第 一散熱金屬層；以及移除該阻層及其覆蓋之導電層。 另外，於該軟質載板中復可形成電性連接第1散熱金 屬士層及第二散熱金屬層之導電結構，如此即可供晶片運件 t所產生之熱量迅速經由其散熱凸塊及軟f載板之第一及 笫一散熱金屬詹向外逸散。 本發明亦揭露-半導體裝置，係包括：载板，具有相 110358 8 1351729 對之弟-表面及第二表面，該第—表面形成有金屬引線層 」第：散熱金屬層，並於該第二表面形成有第二散熱金屬 朗片’係具有相對之主動面及非主動面，該主動面上 没有被數銲塾，各該銲墊上具有對應該金屬引線層之金屬 凸塊’且該些金屬凸塊間形成有對應該第一散熱金屬層之 散熱凸塊’以供該晶片間隔該金屬凸塊及散熱凸塊接置於 •該軟質载板之金屬引線層及第一散熱金屬層上；以及絕緣 膠·，知填充於該晶片與軟質載板間之間隙。 鲁 $外於該軟質載板第一表面復形成有防銲層，盆中々 防銲層係外露出該第-散熱金屬層及用以連接晶片金屬凸/ 塊之金屬引線層端部，俾與該晶片電性耦合。 因此，本發明之半導體裝置及其製法主要係提供一1 有第-表面及第二表面之軟質載板，且於該第一表面上开; 成金屬引線層及第-散熱金屬層’而該第二表面上形成有 第二散熱金屬層，另提供具有相對主動面及非主動面之晶 φ片，於該主動面上設有複數銲墊，且各該鲜塾上形成有= 應該金屬引線層之金屬凸塊’並於該些金屬凸塊間形成有 =應該第-散熱金屬層之散熱凸塊’以供晶片接置於該軟 質載板上時’令該晶片金屬凸塊對應電性連接至該軟質^ 板之金屬引線層’以作訊號傳遞，同時供晶片運作時所產 生之熱量得以透過該晶片之散熱凸塊連接至軟質載板之第 -散熱金屬層’並經由軟質載板第二表面之第二散 層向外逸散’進而提高晶片散熱性。如此當半導體裝置以 捲帶式（reel to reel)方式生產時，即可避免習知因使用外加 Π0358 9 1351729 » .散熱件造成無法捲帶或於捲帶上發生散熱件損壞問題。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。 1_一 f施例 °月參閱弟1A至II圖，係為本發明之半導體裝置及立 製法第一實施例之示意圖。 鲁 如第圖所示，提供具有相對之主動面及非主 動面102之晶片1〇〇，該晶片1〇〇主動面1〇1上設有複數 銲墊103,且該晶片1〇〇主動面1〇〗覆蓋有絕緣層11〇，並 於該絕緣層110中形成有複數開孔m，以外露出該銲墊 103 ° 如第1B圖所示，於該絕緣層丨1〇及其開孔】2丨表面 以如藏鑛（sputtering)之方式形成材質為鈦化鎢（Tiw)之第 籲一導電層12〇’及材質為金（AU)之第二導電層〗3〇。 如第1C及1D圖所示，於該第二導電層丨3〇上形成阻 層140 ’該阻層HO中形成有複數對應晶片銲墊ι〇3位置 之第一開口 141，並於該些第一開口 141間形成第二開口 142’以使第二導電層13〇外露出該些第一開口 141及第二 開口 142，再於該些第一開口 141及該第二開口 142中電 鍍形成材質為金（Au)之金屬凸塊151及散熱凸塊ι52，並 移除s亥阻層140及其覆蓋之第一及第二導電層12〇，13〇， 其中該金屬凸塊15係形成於該銲塾1 〇3上。 110358 10 1351729 . 11玄金屬凸邋151係與晶片銲墊l〇3連接，.可供晶片loo -與外界,性耗合’且位於該金屬凸塊151貞晶片銲塾103 間之第一及第二導電層12〇13()即為凸塊底部金屬層 (UBM);再者，該散熱凸塊152係形成於該晶片_之主 動面上）隹未與該晶片銲墊1〇3連接，而為偽凸塊（^町 bump) ° • 如第1E圖所示’另提供例如為聚醯亞胺（ρι)膠片（hpe) 之軟質載板扇，並以捲帶式（㈣心叫方式進行製程。 •該軟質載板200係具有相對之第一表面2〇1及第二表面 2〇2，且於該軟質載板第一及第二表面201,202以如濺鍍 (sputtering)之方式形成有如銅（Cu)之導電層22〇。 如第1F圖所示，於該導電層22〇上覆蓋阻層23〇，並 令該阻層230於軟質載板第一表面2〇1形成有對應晶片金 屬凸塊151及散熱凸塊152之第三開〇 231及第四開口 232，以及於第二表面2〇2形成有第五開口 233。 • 如第1G圖所示，該第三及第四開口 231，232中以電鍍 ，式形成金屬引線層241及第一散熱金屬層242，並於該 第五開口 233中電鍍形成第二散熱金屬層243。該金屬引 線層241第政熱金屬層242及第二散熱金屬層例 如為厚約6-15微米之銅/錫（cu/sn)層。 如第1H圖所示，移除該阻層23〇及其覆蓋之導電層 220，並於該軟質載板第一表面201上覆一防銲層25〇，且 T該防銲層250外露出該第一散熱金屬層242及用以連接 晶片金屬凸塊151之金屬引線層241端部，俾與該晶片電 110358
II 1351729 性麵合。 如弟Η圖所不’將該晶片100之主動面1〇1與該軟質 載板200之第一表面2〇1連接，亦即藉由熱壓方式將該晶 片主動面101上之金屬凸塊151及散熱凸塊152與該軟質 載板第一表面201上之金屬引線層241及第一散熱金屬層 242相互對應壓合形成共金結構，以供該晶片1 得以透 過該金屬凸塊151與載板金屬引線層241相互電性耦合而 作訊號傳遞，同時供該晶片1〇〇藉由其散熱凸塊（偽凸 塊）152與載板第一表面2〇1之第一散熱金屬層242連接， 再透過形成於载板第二表面2〇2之第二散熱金屬層M3而 得有效傳遞晶片100運作時所產生之熱量。 之後再於該晶片1 〇〇與軟質載板2〇〇間之間隙填充女 覆晶底部填膠材料（underfiI1)之絕緣膠3〇〇，以製得本發甲 之覆晶薄膜（COF)半導體裝置。 因此，透過如述製法，本發明亦揭露一 係包括:軟質载板20。，具有相對之第一表面 表面202 β亥第一表面2〇1形成有金屬引線層μ卜且於該 :金屬引線層241間形成有第一散熱金屬層242，並於該 第表面2〇2形成有第二散熱金屬層243 ;晶片1〇〇，且有 相對之主動面101及非主動 _ + _ 八 複數銲塾103,且各外熱^該主動面1〇1上設有 全屬引结爲， 形成有對應該軟質載板 直之孟屬凸塊15卜該些金屬凸塊151 間形成有對應該軟質载板第一 ⑸，以供該晶片〗。。間隔該金:::屬f 242之散熱凸塊 μ金屬凸塊151及散熱凸塊152 Π0358 12 1351729. 接置於該軟質載板金屬引線層241及第一散熱金屬層242 上；以及絕緣膠300 ’係填充於該晶片1 〇〇與軟質載板2〇〇 間之間隙。 ' 另外’於該軟質載板200之第一表面2〇1上復形成有 外路出该金屬引線層241及第一散熱金屬層242之防銲層 25〇;於該晶片1〇〇之主動面101上則形成有外露出該銲墊 之絕緣層110,且該晶片銲墊103與金屬凸塊15丨間及 晶片主動面101與散熱凸塊152間係間隔有導電層 120,130 〇 曰 因此，本發明之半導體裝置 有相對第-表面及第二表面之軟質載板，且於該第一表面 =有金屬引線層及第一散熱罐，而該第二表面上 :成有第二散熱金屬層，另提供具有相對主動面及非主動 =片，於該主動面上設有複數鮮墊，且各該銲 成有對應該金屬引線層之金屬凸塊，並於該 形成有對應該第一散熱金屬層之散熱凸塊；供晶片= 於该軟質載板上時，令該晶 i, ^ ^ ^ s 曰曰乃金屬凸塊對應電性連接至該
权貝载板金^丨線層，以作訊號 X 所產生之熱量得以读禍訪B w 了仏日日片運作時 第-散教金屬⑯κΙΓ之散熱凸塊連接至軟質載板 屬層向=進板第二表面之第二散熱金 「通月文進而如向晶片散熱性。 "\施例 復請參閱第2Α至圖，传Α太& 其製法第η 明之半導體裝置及 Α例之不意圖。同時為簡化本圖示，本實施 110358 13 1351729. ^例中對應前述相同或相似之元件係採用相同標號表示。 . *實施例之半導體裝置及其製法與前述；：二：致相 同，主要差異在於請參閱第2A圖，係於具相對第一表面 201及第二表面202之軟質載板20〇中形成穿孔203,並使 該軟質載板200第-及二表面201，2〇2及穿孔2〇3表面以 如賤鍍之方式覆蓋一如銅（Cu)之導電層22〇。 ' 如第2B圖所示，於該導電層220上覆蓋一阻層23〇， 且令該阻層230於軟質載板第一表面2〇1形成有對曰應晶片 學金屬凸塊及散熱凸塊之第三開口 231及第四開口 232,及 於第二表面202形成有第五開口 233,其中，該第四及第 五開口 232,233連通至該穿孔203。 如第2C圖所示，於該第三開口 231、第四開口 及第五開口 233中以電鍍方式形成金屬引線層24ι、第一 散熱金屬層242及第二散熱金屬層243，並於該穿孔2们 中電鐘形成|電結構244，藉以電性連接軟質载板第一表 #面201之第一散熱金屬層242及第二表面2〇2之第二散熱 金屬層243。 … 如第2D圖所示，移除該阻層23〇及其覆蓋之導電層 220，亚將防銲層25〇覆蓋於該軟質載板第一表面 201’且令該第一散熱金屬層242及金屬引線層24ι端部外 露出該防銲層250。 如第2E圖所示，將主動面1〇1形成有金屬凸塊】51 ^散熱凸塊152之晶片1〇〇與該軟質載板2〇〇連接，亦即 藉由熱壓方式將該晶片主動面1〇1上之金屬凸塊ΐ5ι及散 Π0358 1351729. 熱^塊152與該軟質載板第一表® 2〇1之金屬引線層241 及第-散熱金屬層242相互對應墨合形成共金結構，以供 該晶片_得以透過該金屬凸塊151與軟質載板金屬引線 層⑷相互電性耗合而作訊號傳遞，同時供該晶片_藉 由其散熱凸塊（偽凸塊）152與軟質載板第一表㊆训之第 政…、金屬層242連接’再透過形成於軟質載板綱中之 =電結構244及其第二表面2〇2之第二散熱金屬層⑷而 得有效傳遞晶片1 00運作時所產生之熱量。 之後再於該晶片J 〇 〇與軟質載板2 〇 〇間之間隙填充如 1晶底部填膠材料（underfill)之絕緣勝3GG，以製得 之半導體裝置。 " 差三實施你丨 復請參閱第3圖，係為本發明之半導體裝置第三實施 =示意圖。同時為簡化本圖示，本實施例中對應前述相 同或相似之TL件係採用相同標號表示。 本實施例之半導體裝置與前述實施例大致相同，主要 差異係在軟質載板200之第-*而u * ^ ^ 弟一表面202上，另形成有一遮 覆弟一散熱金屬層243之霜芸爲γη 為拒銲層。 之覆盍層，該覆蓋260層例如 上述實施例僅為例示性說明本發明之原理及其功效， 於限制本發明。任何熟習該項技術之人士均可在不 =發明之精神與範轉下’對上述實施 。因此’本發明之權利保護範圍，應專二 範圍所列。 次κ γ。月寻利 110358 15 1351729, 【圖式簡單說明】 第1A至II圖係為本發明之半導體裝置及其製法第一 實施例之示意圖； 第2A至2E圖係為本發明之半導體裝置及其製法 實施例之示意圖； 〜 第3圖係為本發明之半導體裝置第三實施 圖；以及 、〜不思、
第4A至4J圖係為習知覆晶薄膜（c〇F)半導體 製法之實施例之示意圖。 '"之 【主要元件符號說明】
100晶片 1 μ 非主動面 110絕緣層 120 第一導電層 140 阻層 142第二開口 152 散熱凸塊 201第一表面 203穿孔 230 阻層 232第四開口 241 金屬引線層 243 第二散熱金屬層 250防銲層 101 主動面 103 銲墊 111 開孑L 130 第二導電層 141 第一開口 151 金屬凸塊 200 軟質載板 202 第二表面 220 導電層 231 第三開口 233 第五開口 242 第一散熱金屬層 244 導電結構 300 絕緣膠 110358 16 1351729, * 400 晶片 401 銲塾 410 絕緣層 411 開孔 4 420 第一導電層 430 第二導電層 440 阻層 441 開口 450 金屬凸塊 500 軟質載板 510 導電層 520 阻層 521 開口 530 金屬引線層 550 防鲜層 600 覆晶底部填膠材料
17 110358

Claims (1)

  1. 十、申請專利範圍： h 一種半導體裝置之製法，係包括 一提供具有相對主動面及非主動面之晶片與具有相 :弟-表面及第二表面之軟質載板，該晶片主動面上設 有複數銲塾，且各該銲塾上形成有金屬凸塊，並於該些 f屬凸塊間形成有散熱凸塊，該軟質載板第-表面形成 有相對應该金屬凸挽^ @ p丨 鬼之孟屬引線層及對應該散熱凸塊 ^一散熱金屬層，並於該第二表面上形成有第二散熱 金屬層； 將該晶片之主動面接置於該軟質載板之第一表 面，且使該晶片主動面上之金屬凸塊與散熱凸塊電性連 接至對應該金屬引線層及第一散熱金屬層；以及 於該晶片與軟質載板間隙填充絕緣膠。 2.如申請專利範圍第]項之半導體裝置之製法，其中，該 晶片之金屬凸塊及散熱凸塊之製法係包括： ^提供表面覆蓋有絕緣層之晶片，且該絕緣層形成有 複數開孔以外露出晶片銲墊； 於。亥纟a緣層及其開孔表面形成導電層； 於該導電層上覆蓋阻層，並於該阻層中形成複數對 :k銲墊位置之第一開口，及於該些第一開口間形成第 二開口’以外露出該導電層；以及 :該第及第一開口中電鐘形成金屬凸塊及散熱 凸塊，並移除該阻層及其覆蓋之導電層。 3·如申請專利範圍第2項之半導體裝置之製法，其中，該 120358 18 1351729. 導電層包括鈦化鎢（Tiw)及金（Au)，該金屬凸塊及散熱 凸塊材質為金（Au)，且該金屬凸塊係形成於該鮮塾上。 4. 如申請專利範圍第丨項之半導體裝置之製法，其中，該 軟質載板之金屬引線層、第—及第二散熱金屬層之製法 係包括： 提供具有相對第-及第二表面之軟f載板，於該軟 質載板第一及第二表面形成導電層； 於該導電層上覆蓋阻層’並令該阻層於軟質載板第 一表面形成有對應晶片金屬凸塊及散熱凸塊之苐三及 第四開〇,以及於第二表面形成有第五開口 ； 在於該第三及第四開口中電鍍形成金屬引線層及第 “ 弟五開口中電銀形成第二散熱金 屬層；以及 移除該阻層及其覆蓋之導電層。 5. 如申請專利範圍第【項之半導體裝置之製法，其中，該 m之金屬引線層、第一散熱金屬層及第：散熱： 屬層之製法係包括： 於具相對第一表面及第二表面之軟質載板中形成 r;:亚於該軟質載板第-及二表面及穿孔表面覆蓋導 Μ* /a ， ^導電層上覆蓋-阻層’且令該阻層於軟質載板 f=rr對應晶片金屬凸塊及散熱凸塊之第三 開口及第四開口，及於第二表面形成有第五開口，直 中，該第四及第五開口連通至該穿孔； / 110358 19 1351729. , '於該第三開口、第四開口及第五開口中以電鍍方式 形成金屬弓丨線層、第一散熱金屬層及第二散熱金屬層， 並於該穿孔令電鍍形成導電結構，藉以電性連接軟質曰载 板第-表面之第一散熱金屬層及第二表面之第二散 金屬層；以及 … 移除該阻層及其覆蓋之導電層。 6·如申請專利範圍第1項之半導體裝置之製法，其中，該 金屬凸塊與晶片銲墊連接，以供晶片與外界電性耦合， •該散熱凸塊形成於該晶片之主動面上，並未與該晶片銲 墊連接’而為偽凸塊（dummy bump)。 7. 如申請專利範圍第1項之半導體裝置之製法，其中，該 軟質載板為聚醯亞胺（PI)膠片（tape)，並以捲帶式I reel)方式進行製程。 8. 如申請專利範圍第1項之半導體裝置之製法，其中，該 金屬引線層、第-散熱金屬層及第二散熱金屬層之材質乂 φ 為銅/錫（Cu/Sn) ’厚度為6至IS微米。 9. 如申請專利範圍第1項之半導體裝置之製法，其中，該 晶片主動面上之金屬凸塊及散熱凸塊係藉由熱壓方^ 與該軟質載板第-表面上之金屬^線層及第—散熱金 屬層相互對應壓合形成共金結構。 10. 如申請專利範圍第丨項之半導體裝置之製法，其令，該 晶片透過該金屬凸塊與載板金屬引線層相互 而作訊號傳遞，該晶片藉由散熱凸塊與載板第一表面之 第一散熱金屬層連接，再透過形成於载板第二表面之第 IJ0358 20 1351729. 二散熱金屬層而傳遞晶片運作時所產生之埶量。 U.=f利範圍第1項之半導體裝置之製二其中，， 表面覆風有防銲層，且外露出該金屬弓丨绵 層端部及第一散熱金屬層。 5丨線 12·2請專鄉圍第1項之半導體裝置之製法，其中1 ::載板弟二表面，形成有—遮覆第二散熱金屬層之覆 盍層。 吸 13. 如申料利範圍第12項之半導體裝置之製法，其中， 該覆盍層為拒銲層。 14. 一種半導體裝置，係包括： 軟質载板，具有相對之第—表面及第二表面， 一表面形成有金屬引線層，且於該些金屬引線層間形 =了散熱金屬層’並於該第二表面形成有第二散熱金 晶片’具有相對之主動面及非主動面，該主動面上 • 銲墊，且各該銲塾上形成有對應該軟質载板金 屬引線層位置之金屬凸塊，該些金屬凸塊間形成有對應 該軟質載板第一散熱金屬層之散熱凸塊，以供該晶片 隔該金屬凸塊及散熱凸塊接置於該軟質載板金^ 曰引^ 層及第一散熱金屬層上；以及 ’ 知填充於該晶片與軟質載板間之間隙 m. w 15.如申請專利範圍第14項之半導體裝置，其 .^ 〆、T ，邊晶片 主動面上形成有外露出該銲墊之絕緣層，且該晶片銲墊 與金屬凸塊間及晶片主動面與散熱凸塊間係間隔有導 110358 21 1351729. 電層。 16·如申請專利範圍第15項之半導體裝置，其中，該導電 層為凸塊底部金屬層（UBM)，其包括有鈦化鎢（Tiw)及 金（Au)。 17. 如申請專利範圍第14項之半導體裝置，其中，該軟質 載板中形成有電性連接第一散熱金屬層及第二散熱金 屬層之導電結構。 18. 如申請專利範圍第14項之半導體裝置，其中，該金屬 ♦ 凸塊與晶片銲塾連接’以供晶片與外界電性麵合，該散 熱凸塊形成於該晶片之主動面上，並未與該晶片銲墊連 接’而為偽凸塊（dummy bump)。 19. 如申請專利範圍第14項之半導體裝置，其中，該軟質 載板為聚醯亞胺（PI)膠片（tape)。 20_如申請專利範圍第14項之半導體裝置，其中，該金屬 引線層、第-散熱金屬層及第二散熱金屬層之材°質為銅 • /錫（Ο,厚度為6至15微米，該金屬凸塊及散熱凸 塊材質為金(Au)。 21.如申請專利範圍第14項之半導體裝置，其中，該晶片 主動面上之金屬凸塊及散熱凸塊與該軟質載板第:表 面上之金屬引線層及第一散熱金屬層相互形成共金結 構。 22.如申請專利範圍第14項之半導 透過該金屬凸塊與軟質載板金屬引線層指互電性 ：合 而作訊號傳遞，該晶片藉由散熱凸塊與載板第一表面之 110358 22 1351729. 第:散熱金屬層連接，再透過形成於载板第二表 -散熱金屬層而傳遞晶片運作時 弟 23.如申請專職_14項之半導職置，^括有防鲜 層，係覆盍於該軟質載板第—表面，且外露出該金屬引 線層端部及第一散熱金屬層。 24·如申請專利範圍第14項之半導體裝置，復包括有覆蓋 層，係形成於該軟質載板第二表面，且遮覆第二散熱金 屬層。 25·如申請專利範圍第24項之半導體裝置，其中，該覆蓋 層為拒銲層。 23 110358
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