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KR910020729A - 반도체 기억회로 - Google Patents

반도체 기억회로 Download PDF

Info

Publication number
KR910020729A
KR910020729A KR1019910007291A KR910007291A KR910020729A KR 910020729 A KR910020729 A KR 910020729A KR 1019910007291 A KR1019910007291 A KR 1019910007291A KR 910007291 A KR910007291 A KR 910007291A KR 910020729 A KR910020729 A KR 910020729A
Authority
KR
South Korea
Prior art keywords
bit line
sense amplifier
pair
semiconductor memory
amplifier node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1019910007291A
Other languages
English (en)
Inventor
마사루 위에스기
Original Assignee
고스기 노부미쓰
오끼뎅끼 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼뎅끼 고오교오 가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR910020729A publication Critical patent/KR910020729A/ko
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 기억회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예를 표시하는 반도체 기억회로에 있어서의 센스앰프 회로부분의 회로도.

Claims (3)

  1. 비트선쌍과 워드선이 각각 복수개 교차배열되어 그 각교차개소에 각각 접속된 다이내믹형 메모리셀과 상기 비트선쌍에 접속된 센스앰프노드쌍을 가지고 있고 그 센스앰프노드쌍간에 접속된 센스앰프를 구비한 반도체 기억회로에 있어서, 상기 비트선쌍과 상기 센스앰프노드쌍과의 사이에 각각 독립적으로 제어가능한 스위치수단을 설치한 것을 특징으로 하는 반도체 기억장치.
  2. 비트선쌍과 워드선이 각각 복수개 교차배열되어 그 각교차개소에 각각 접속된 다이내믹형 메모리셀과 상기 비트선쌍에 접속된 센스앰프노드쌍을 가지고 있고 그 센스앰프노드쌍간에 접속된 센스앰프와 상기 비트선쌍에 접속된 비트선전압원을 구비한 반도체 기억회로에 있어서, 상기 비트선쌍과 상기 비트선 전압원과의 사이에 각각 독립적으로 제어가능한 스위치수단을 설치한 것을 특징으로 하는 반도체 기억장치.
  3. 제2항에 있어서, 상기 비트선쌍과 상기 센스앰프노드쌍과의 사이에 각각 독립적으로 제어가능한 다른스위치수단을 설치한 반도체 기억회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910007291A 1990-05-25 1991-05-06 반도체 기억회로 Abandoned KR910020729A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2-136223 1990-05-25
JP2136223A JPH0430388A (ja) 1990-05-25 1990-05-25 半導体記憶回路

Publications (1)

Publication Number Publication Date
KR910020729A true KR910020729A (ko) 1991-12-20

Family

ID=15170175

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007291A Abandoned KR910020729A (ko) 1990-05-25 1991-05-06 반도체 기억회로

Country Status (5)

Country Link
US (1) US5278799A (ko)
EP (1) EP0458351B1 (ko)
JP (1) JPH0430388A (ko)
KR (1) KR910020729A (ko)
DE (1) DE69127317T2 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04353692A (ja) * 1991-05-30 1992-12-08 Sanyo Electric Co Ltd メモリセルの書き込み方法
US5280452A (en) * 1991-07-12 1994-01-18 International Business Machines Corporation Power saving semsing circuits for dynamic random access memory
US5737711A (en) * 1994-11-09 1998-04-07 Fuji Jukogyo Kabuishiki Kaisha Diagnosis system for motor vehicle
US5640114A (en) * 1995-12-27 1997-06-17 Vlsi Technology, Inc. Versatile select and hold scan flip-flop
JP2000132969A (ja) 1998-10-28 2000-05-12 Nec Corp ダイナミックメモリ装置
US6687175B1 (en) 2000-02-04 2004-02-03 Renesas Technology Corporation Semiconductor device
KR100368133B1 (ko) * 2000-03-28 2003-01-15 한국과학기술원 메모리 셀 정보 저장 방법
JP4934897B2 (ja) * 2001-01-12 2012-05-23 ソニー株式会社 メモリ装置
KR100990468B1 (ko) 2006-03-28 2010-10-29 후지쯔 세미컨덕터 가부시키가이샤 반도체 메모리 및 시스템
JP4996422B2 (ja) * 2007-11-05 2012-08-08 ルネサスエレクトロニクス株式会社 半導体装置
US8116157B2 (en) * 2007-11-20 2012-02-14 Qimonda Ag Integrated circuit
TW201201206A (en) 2010-06-10 2012-01-01 Mosaid Technologies Inc Semiconductor memory device with sense amplifier and bitline isolation
US8681574B2 (en) * 2011-03-31 2014-03-25 Mosys, Inc. Separate pass gate controlled sense amplifier
US8451675B2 (en) 2011-03-31 2013-05-28 Mosys, Inc. Methods for accessing DRAM cells using separate bit line control
KR20130055992A (ko) * 2011-11-21 2013-05-29 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이를 이용한 반도체 집적 회로

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5836504B2 (ja) * 1980-02-22 1983-08-09 富士通株式会社 半導体記憶装置
JPS5856287A (ja) * 1981-09-29 1983-04-02 Nec Corp 半導体回路
JPS60206161A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体集積回路
JPS6180597A (ja) * 1984-09-26 1986-04-24 Hitachi Ltd 半導体記憶装置
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
JPH0652632B2 (ja) * 1985-01-23 1994-07-06 株式会社日立製作所 ダイナミツク型ｒａｍ
JPH0785354B2 (ja) * 1985-05-08 1995-09-13 日本電気株式会社 半導体メモリ
JPS6280897A (ja) * 1985-10-04 1987-04-14 Mitsubishi Electric Corp 半導体記憶装置
US4710902A (en) * 1985-10-04 1987-12-01 Motorola, Inc. Technique restore for a dynamic random access memory
DE3884859T2 (de) * 1987-06-04 1994-02-03 Nippon Electric Co Dynamische Speicherschaltung mit einem Abfühlschema.
JPS6457495A (en) * 1987-08-28 1989-03-03 Hitachi Ltd Semiconductor memory device
EP0321847B1 (en) * 1987-12-21 1994-06-29 Kabushiki Kaisha Toshiba Semiconductor memory capable of improving data rewrite speed
JPH0229989A (ja) * 1988-07-19 1990-01-31 Mitsubishi Electric Corp ダイナミックランダムアクセスメモリ装置

Also Published As

Publication number Publication date
DE69127317T2 (de) 1998-04-02
EP0458351A3 (en) 1994-08-17
JPH0430388A (ja) 1992-02-03
US5278799A (en) 1994-01-11
EP0458351B1 (en) 1997-08-20
EP0458351A2 (en) 1991-11-27
DE69127317D1 (de) 1997-09-25

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Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19910506

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Patent event date: 19990118

Patent event code: PE09021S01D

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