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KR920010638A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR920010638A
KR920010638A KR1019910019888A KR910019888A KR920010638A KR 920010638 A KR920010638 A KR 920010638A KR 1019910019888 A KR1019910019888 A KR 1019910019888A KR 910019888 A KR910019888 A KR 910019888A KR 920010638 A KR920010638 A KR 920010638A
Authority
KR
South Korea
Prior art keywords
potential
bit lines
control signal
sense amplifier
precharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019910019888A
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English (en)
Other versions
KR950001289B1 (ko
Inventor
이사미히또 이께다
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR920010638A publication Critical patent/KR920010638A/ko
Application granted granted Critical
Publication of KR950001289B1 publication Critical patent/KR950001289B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음.

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이발명의 1실시예에 의한 쉐아드센스앰프 방식의 반도체기억장치의 주요부의 구성을 표시하는 회로도.

Claims (1)

  1. 복수의 메모리셀이 접속되는 제1비트선, 복수의 메모리셀이 접속되는 제2의 비트선, 상기 제1 및 제2의 비트선에 공통으로 설치되는 센스앰프수단과, 상기 제2의 비트선과 상기 센스 앰프수단과의 사이에 접속되고 제1의 전위에 응답하고 도통하는 제1의 스위칭수단과, 상기 제2의 비트선과 상기 센스앰프수단과의 사이에 접속되고 제2의 전위에 응답하고 도통하는 제2의 스위칭수단과, 프리챠지기간에 상기 제1 및 제2의 비트선을 소정의 전위에 프리챠지하는 프리챠지수단과, 그리고 액세스 기간에 상기 제1의 전위 또는 상기 제2의 전위에 변화하고 또한 상기 프리챠지기간에 상기 제1의 전위와 상기 제2의 전위와의 중간전위에 변화하는 제어신호를 발생하고 그의 제어신호를 상기 제1 및 제의 스위치수단에 제공하는 제어신호발생수단을 구비한 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910019888A 1990-11-21 1991-11-09 반도체기억장치 Expired - Fee Related KR950001289B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-318676 1990-11-21
JP2318676A JPH04186593A (ja) 1990-11-21 1990-11-21 半導体記憶装置

Publications (2)

Publication Number Publication Date
KR920010638A true KR920010638A (ko) 1992-06-26
KR950001289B1 KR950001289B1 (ko) 1995-02-15

Family

ID=18101786

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019888A Expired - Fee Related KR950001289B1 (ko) 1990-11-21 1991-11-09 반도체기억장치

Country Status (5)

Country Link
US (1) US5243574A (ko)
JP (1) JPH04186593A (ko)
KR (1) KR950001289B1 (ko)
DE (1) DE4138340C2 (ko)
IT (1) IT1252280B (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3319610B2 (ja) * 1991-11-22 2002-09-03 日本テキサス・インスツルメンツ株式会社 信号伝達回路
KR970004460B1 (ko) * 1992-06-30 1997-03-27 니뽄 덴끼 가부시끼가이샤 반도체 메모리 회로
JP2814846B2 (ja) * 1992-07-29 1998-10-27 日本電気株式会社 半導体記憶装置
JPH0757466A (ja) * 1993-08-12 1995-03-03 Toshiba Corp 半導体集積回路
JPH07326192A (ja) * 1994-05-31 1995-12-12 Toshiba Micro Comput Eng Corp 半導体記憶装置
US5907516A (en) * 1994-07-07 1999-05-25 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device with reduced data bus line load
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
US5561630A (en) * 1995-09-28 1996-10-01 International Business Machines Coporation Data sense circuit for dynamic random access memories
US5710738A (en) * 1996-12-17 1998-01-20 Powerchip Semiconductor Corp. Low power dynamic random access memory
JPH10302469A (ja) * 1997-04-25 1998-11-13 Fujitsu Ltd 半導体記憶装置
KR100297727B1 (ko) * 1998-08-13 2001-09-26 윤종용 분리 제어라인의 큰 부하에 의한 스피드 손실을 방지할 수 있는반도체 메모리 장치
KR100395877B1 (ko) * 2000-11-10 2003-08-25 삼성전자주식회사 반도체 메모리의 데이타 감지 장치
KR100382614B1 (ko) * 2000-12-29 2003-05-09 주식회사 하이닉스반도체 저전력의 메모리 코아 제어 장치
US6580655B2 (en) * 2001-08-29 2003-06-17 International Business Machines Corporation Pre-charge circuit and method for memory devices with shared sense amplifiers
JP4462528B2 (ja) 2002-06-24 2010-05-12 株式会社日立製作所 半導体集積回路装置
KR100838363B1 (ko) * 2005-10-20 2008-06-13 주식회사 하이닉스반도체 센스앰프 회로
KR100871083B1 (ko) * 2007-02-27 2008-11-28 삼성전자주식회사 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조
US8050127B2 (en) * 2009-02-06 2011-11-01 Hynix Semiconductor Inc. Semiconductor memory device
US8437204B2 (en) * 2009-06-12 2013-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array with corresponding row and column control signals
KR101033490B1 (ko) * 2009-11-30 2011-05-09 주식회사 하이닉스반도체 패드를 선택적으로 이용하는 반도체 메모리 장치

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273694A (ja) * 1986-05-22 1987-11-27 Sony Corp センスアンプ
JPS632197A (ja) * 1986-06-20 1988-01-07 Mitsubishi Electric Corp 半導体記憶装置
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH0229989A (ja) * 1988-07-19 1990-01-31 Mitsubishi Electric Corp ダイナミックランダムアクセスメモリ装置
JPH0713861B2 (ja) * 1988-12-05 1995-02-15 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
US5243574A (en) 1993-09-07
ITMI913091A0 (it) 1991-11-20
ITMI913091A1 (it) 1993-05-20
JPH04186593A (ja) 1992-07-03
KR950001289B1 (ko) 1995-02-15
DE4138340C2 (de) 1994-01-20
IT1252280B (it) 1995-06-08
DE4138340A1 (de) 1992-05-27

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