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KR100797210B1 - 다층구조의 제조방법 - Google Patents

다층구조의 제조방법 Download PDF

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Publication number
KR100797210B1
KR100797210B1 KR1020057010109A KR20057010109A KR100797210B1 KR 100797210 B1 KR100797210 B1 KR 100797210B1 KR 1020057010109 A KR1020057010109 A KR 1020057010109A KR 20057010109 A KR20057010109 A KR 20057010109A KR 100797210 B1 KR100797210 B1 KR 100797210B1
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KR
South Korea
Prior art keywords
layer
level
support substrate
sige
semiconductor material
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Expired - Lifetime
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KR1020057010109A
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English (en)
Korean (ko)
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KR20050084146A (ko
Inventor
까르로 마주르
Original Assignee
에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
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Application filed by 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 filed Critical 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지
Publication of KR20050084146A publication Critical patent/KR20050084146A/ko
Application granted granted Critical
Publication of KR100797210B1 publication Critical patent/KR100797210B1/ko
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
KR1020057010109A 2002-12-06 2003-12-05 다층구조의 제조방법 Expired - Lifetime KR100797210B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0215499A FR2848334A1 (fr) 2002-12-06 2002-12-06 Procede de fabrication d'une structure multicouche
FR02/15499 2002-12-06

Publications (2)

Publication Number Publication Date
KR20050084146A KR20050084146A (ko) 2005-08-26
KR100797210B1 true KR100797210B1 (ko) 2008-01-22

Family

ID=32320086

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057010109A Expired - Lifetime KR100797210B1 (ko) 2002-12-06 2003-12-05 다층구조의 제조방법

Country Status (8)

Country Link
EP (1) EP1568073A1 (fr)
JP (1) JP4762547B2 (fr)
KR (1) KR100797210B1 (fr)
CN (1) CN1720605A (fr)
AU (1) AU2003294170A1 (fr)
FR (1) FR2848334A1 (fr)
TW (1) TWI289880B (fr)
WO (1) WO2004053961A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7110081B2 (en) 2002-11-12 2006-09-19 Asml Netherlands B.V. Lithographic apparatus and device manufacturing method
US7247545B2 (en) * 2004-11-10 2007-07-24 Sharp Laboratories Of America, Inc. Fabrication of a low defect germanium film by direct wafer bonding
JP2011517061A (ja) * 2008-03-13 2011-05-26 エス．オー．アイ．テック シリコン オン インシュレータ テクノロジーズ 絶縁埋め込み層に帯電領域を有する基板
CN105023991B (zh) * 2014-04-30 2018-02-23 环视先进数字显示无锡有限公司 一种基于无机物的led积层电路板的制造方法
CN108231695A (zh) * 2016-12-15 2018-06-29 上海新微技术研发中心有限公司 复合衬底及其制造方法
CN107195534B (zh) * 2017-05-24 2021-04-13 中国科学院上海微系统与信息技术研究所 Ge复合衬底、衬底外延结构及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002015244A2 (fr) 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
FR2783254B1 (fr) * 1998-09-10 2000-11-10 France Telecom Procede d'obtention d'une couche de germanium monocristallin sur un substrat de silicium monocristallin,et produits obtenus
JP2001015721A (ja) * 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
US6323108B1 (en) * 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
JP3607194B2 (ja) * 1999-11-26 2005-01-05 株式会社東芝 半導体装置、半導体装置の製造方法、及び半導体基板
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
WO2002071491A1 (fr) * 2001-03-02 2002-09-12 Amberwave Systems Corporation Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse
WO2002082514A1 (fr) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology Procede de fabrication d'un dispositif semi-conducteur
US6566158B2 (en) * 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
JP2003249641A (ja) * 2002-02-22 2003-09-05 Sharp Corp 半導体基板、その製造方法及び半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002015244A2 (fr) 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle

Also Published As

Publication number Publication date
TW200511393A (en) 2005-03-16
EP1568073A1 (fr) 2005-08-31
CN1720605A (zh) 2006-01-11
WO2004053961A1 (fr) 2004-06-24
JP2006509361A (ja) 2006-03-16
JP4762547B2 (ja) 2011-08-31
FR2848334A1 (fr) 2004-06-11
TWI289880B (en) 2007-11-11
KR20050084146A (ko) 2005-08-26
AU2003294170A1 (en) 2004-06-30

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