JP4762547B2 - 多層構造の製造方法 - Google Patents
多層構造の製造方法 Download PDFInfo
- Publication number
- JP4762547B2 JP4762547B2 JP2004558309A JP2004558309A JP4762547B2 JP 4762547 B2 JP4762547 B2 JP 4762547B2 JP 2004558309 A JP2004558309 A JP 2004558309A JP 2004558309 A JP2004558309 A JP 2004558309A JP 4762547 B2 JP4762547 B2 JP 4762547B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- support substrate
- lattice constant
- embrittlement zone
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 43
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 230000007547 defect Effects 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 8
- 230000006641 stabilisation Effects 0.000 claims description 6
- 238000011105 stabilization Methods 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000006978 adaptation Effects 0.000 claims 3
- 230000002040 relaxant effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 126
- 235000012431 wafers Nutrition 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 239000002344 surface layer Substances 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 239000000872 buffer Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910006990 Si1-xGex Inorganic materials 0.000 description 1
- 229910007020 Si1−xGex Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- -1 helium ions Chemical class 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR02/15499 | 2002-12-06 | ||
| FR0215499A FR2848334A1 (fr) | 2002-12-06 | 2002-12-06 | Procede de fabrication d'une structure multicouche |
| PCT/IB2003/006397 WO2004053961A1 (fr) | 2002-12-06 | 2003-12-05 | Procede de fabrication d'une structure multicouche |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006509361A JP2006509361A (ja) | 2006-03-16 |
| JP4762547B2 true JP4762547B2 (ja) | 2011-08-31 |
Family
ID=32320086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004558309A Expired - Lifetime JP4762547B2 (ja) | 2002-12-06 | 2003-12-05 | 多層構造の製造方法 |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1568073A1 (fr) |
| JP (1) | JP4762547B2 (fr) |
| KR (1) | KR100797210B1 (fr) |
| CN (1) | CN1720605A (fr) |
| AU (1) | AU2003294170A1 (fr) |
| FR (1) | FR2848334A1 (fr) |
| TW (1) | TWI289880B (fr) |
| WO (1) | WO2004053961A1 (fr) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7110081B2 (en) | 2002-11-12 | 2006-09-19 | Asml Netherlands B.V. | Lithographic apparatus and device manufacturing method |
| US7247545B2 (en) * | 2004-11-10 | 2007-07-24 | Sharp Laboratories Of America, Inc. | Fabrication of a low defect germanium film by direct wafer bonding |
| JP2011517061A (ja) * | 2008-03-13 | 2011-05-26 | エス．オー．アイ．テック シリコン オン インシュレータ テクノロジーズ | 絶縁埋め込み層に帯電領域を有する基板 |
| CN105023991B (zh) * | 2014-04-30 | 2018-02-23 | 环视先进数字显示无锡有限公司 | 一种基于无机物的led积层电路板的制造方法 |
| CN108231695A (zh) * | 2016-12-15 | 2018-06-29 | 上海新微技术研发中心有限公司 | 复合衬底及其制造方法 |
| CN107195534B (zh) * | 2017-05-24 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Ge复合衬底、衬底外延结构及其制备方法 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121377A (ja) * | 1997-08-26 | 1999-04-30 | Internatl Business Mach Corp <Ibm> | 半導体材料薄膜の製造のための改良型スマート・カット・プロセス |
| JP2001217430A (ja) * | 1999-11-26 | 2001-08-10 | Toshiba Corp | 半導体基板の製造方法およびこれにより製造された半導体基板 |
| WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
| WO2002015244A2 (fr) * | 2000-08-16 | 2002-02-21 | Massachusetts Institute Of Technology | Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle |
| JP2002525255A (ja) * | 1998-09-10 | 2002-08-13 | フランス テレコム | 単結晶シリコン基板上に単結晶ゲルマニウム層を得る方法およびそれにより得られた生成物 |
| US20020168864A1 (en) * | 2001-04-04 | 2002-11-14 | Zhiyuan Cheng | Method for semiconductor device fabrication |
| JP2003249641A (ja) * | 2002-02-22 | 2003-09-05 | Sharp Corp | 半導体基板、その製造方法及び半導体装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015721A (ja) * | 1999-04-30 | 2001-01-19 | Canon Inc | 複合部材の分離方法及び薄膜の製造方法 |
| US6323108B1 (en) * | 1999-07-27 | 2001-11-27 | The United States Of America As Represented By The Secretary Of The Navy | Fabrication ultra-thin bonded semiconductor layers |
| WO2002071491A1 (fr) * | 2001-03-02 | 2002-09-12 | Amberwave Systems Corporation | Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse |
| US6566158B2 (en) * | 2001-08-17 | 2003-05-20 | Rosemount Aerospace Inc. | Method of preparing a semiconductor using ion implantation in a SiC layer |
-
2002
- 2002-12-06 FR FR0215499A patent/FR2848334A1/fr active Pending
-
2003
- 2003-12-05 WO PCT/IB2003/006397 patent/WO2004053961A1/fr active Application Filing
- 2003-12-05 AU AU2003294170A patent/AU2003294170A1/en not_active Abandoned
- 2003-12-05 JP JP2004558309A patent/JP4762547B2/ja not_active Expired - Lifetime
- 2003-12-05 EP EP03789590A patent/EP1568073A1/fr not_active Withdrawn
- 2003-12-05 KR KR1020057010109A patent/KR100797210B1/ko active IP Right Grant
- 2003-12-05 TW TW092134368A patent/TWI289880B/zh not_active IP Right Cessation
- 2003-12-05 CN CNA2003801052499A patent/CN1720605A/zh active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121377A (ja) * | 1997-08-26 | 1999-04-30 | Internatl Business Mach Corp <Ibm> | 半導体材料薄膜の製造のための改良型スマート・カット・プロセス |
| JP2002525255A (ja) * | 1998-09-10 | 2002-08-13 | フランス テレコム | 単結晶シリコン基板上に単結晶ゲルマニウム層を得る方法およびそれにより得られた生成物 |
| JP2001217430A (ja) * | 1999-11-26 | 2001-08-10 | Toshiba Corp | 半導体基板の製造方法およびこれにより製造された半導体基板 |
| WO2001093325A1 (fr) * | 2000-05-30 | 2001-12-06 | Commissariat A L'energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
| WO2002015244A2 (fr) * | 2000-08-16 | 2002-02-21 | Massachusetts Institute Of Technology | Procede de production d'articles semiconducteurs par croissance epitaxiale graduelle |
| US20020168864A1 (en) * | 2001-04-04 | 2002-11-14 | Zhiyuan Cheng | Method for semiconductor device fabrication |
| JP2003249641A (ja) * | 2002-02-22 | 2003-09-05 | Sharp Corp | 半導体基板、その製造方法及び半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2848334A1 (fr) | 2004-06-11 |
| CN1720605A (zh) | 2006-01-11 |
| EP1568073A1 (fr) | 2005-08-31 |
| KR100797210B1 (ko) | 2008-01-22 |
| KR20050084146A (ko) | 2005-08-26 |
| TWI289880B (en) | 2007-11-11 |
| WO2004053961A1 (fr) | 2004-06-24 |
| JP2006509361A (ja) | 2006-03-16 |
| AU2003294170A1 (en) | 2004-06-30 |
| TW200511393A (en) | 2005-03-16 |
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