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WO2002071491A1 - Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse - Google Patents

Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse Download PDF

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Publication number
WO2002071491A1
WO2002071491A1 PCT/US2002/003688 US0203688W WO02071491A1 WO 2002071491 A1 WO2002071491 A1 WO 2002071491A1 US 0203688 W US0203688 W US 0203688W WO 02071491 A1 WO02071491 A1 WO 02071491A1
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layer
channel
relaxed
providing
sige
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PCT/US2002/003688
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Eugene A. Fitzgerald
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Amberwave Systems Corporation
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Priority claimed from US09/906,200 external-priority patent/US6703688B1/en
Priority claimed from US09/906,201 external-priority patent/US6723661B2/en
Application filed by Amberwave Systems Corporation filed Critical Amberwave Systems Corporation
Publication of WO2002071491A1 publication Critical patent/WO2002071491A1/fr

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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0516—Manufacture or treatment of FETs having PN junction gates of FETs having PN heterojunction gates
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs

Definitions

  • the invention relates to the field of relaxed SiGe platforms for high speed CMOS electronics and high speed analog circuits.
  • Si CMOS as a platform for digital integrated circuits has progressed predictably through the industry roadmap. The progress is created through device miniaturization, leading to higher performance, greater reliability, and lower cost. However, new bottlenecks in data flow are appearing as the interconnection hierarchy is expanded. Although digital integrated circuits have progressed at unprecedented rates, analog circuitry has hardly progressed at all. Furthermore, it appears that in the near future, serious economic and technological issues will confront the progress of digital integrated circuits.
  • One promising candidate material that improves digital integrated circuit technology and introduces new analog integrated circuit possibilities is relaxed SiGe material on Si substrates.
  • Relaxed SiGe alloys on Si can have thin layers of Si deposited on them, creating tension in the thin Si layers.
  • Tensile Si layers have many advantageous properties for the basic device in integrated circuits, the metal-oxide field effect transistor (MOSFET).
  • MOSFET metal-oxide field effect transistor
  • the channel in an electron channel device (n-charmel), the channel can be removed from the surface or 'buried'.
  • This ability to spatially separate the charge carriers from scattering centers such as ionized impurities and the 'rough' oxide interface enables the production of low noise, high performance analog devices and circuits.
  • Exemplary embodiments of the invention describe structures and methods to fabricate advanced strained-layer Si devices, and structures and methods to create circuits based on a multiplicity of devices, all fabricated from the same starting material platform. Starting from the same material platform is key to minimizing cost as well as to allowing as many circuit topologies to be built on this platform as possible.
  • the invention provides a material platform of planarized relaxed
  • planarization and regrowth strategy allows device layers to have minimal surface roughness as compared to strategies in which device layers are grown without planarization.
  • This planarized and regrown platform is a host for strained Si devices that can possess optimal characteristics for both digital and analog circuits. Structures and processes are described that allow for the fabrication of high performance digital logic or analog circuits, but the same structure can be used to host a combination of digital and analog circuits, forming a single system-on-chip.
  • FIG. 1 is a schematic block diagram of a structure including a relaxed SiGe layer epitaxially grown on a Si substrate;
  • FIG. 2 is a schematic block diagram of an exemplary structure showing that the origin of the Crosshatch pattern is the stress fields from injected misfit dislocations;
  • FIG. 3 is a table showing surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates;
  • FIGs. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention
  • FIGs. 5A-5D are schematic diagrams of the corresponding process flow and layer structure for a surface channel FET platform in accordance with the invention.
  • FIGs. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention
  • FIGs. 7A-7D are schematic diagrams of a process flow for a surface channel MOSFET in accordance with the invention
  • FIGs. 8A and 8B are schematic block diagrams of surface channel devices with protective layers;
  • FIGs. 9A and 9B are schematic block diagrams of surface channel devices with Si layers on Ge-rich layers for use in suicide formation
  • FIGs. 10 is schematic diagram of a buried channel MOSFET after device isolation in accordance with the invention.
  • FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention.
  • FIGs. 12A-12D are schematic diagrams of aprocess flow in the case of forming the surface channel MOSFET in the top strained Si layer in accordance with the invention.
  • FIGs. 13A-13D are schematic diagrams of aprocess flow in the case of forming the surface channel MOSFET in the buried strained Si layer in accordance with the invention.
  • FIGs. 14A and 14B are schematic diagrams of surface and buried channel devices with Si ⁇ - y Ge y channels on a relaxed Si ⁇ _ z Ge z layer.
  • FIG. 1 is a schematic block diagram of a structure 100 including a relaxed SiGe layer epitaxially grown on a Si substrate 102.
  • a compositionally graded buffer layer 104 is used to accommodate the lattice mismatch between the uniform SiGe layer 106 and the Si substrate. By spreading the lattice mismatch over a distance, the graded buffer minimizes the number of dislocations reaching the surface and thus provides a method for growing high-quality relaxed SiGe films on Si.
  • Crosshatch pattern is typically a few hundred angstroms thickness over distances of microns.
  • the Crosshatch pattern is a mild, undulating surface morphology with respect to the size of the electron or hole. For that reason, it is possible to create individual devices that achieve enhancements over their control Si device counterparts. However, commercialization of these devices requires injection of the material into the
  • Si CMOS process environment to achieve low cost, high performance targets.
  • This processing environment requires that the material and device characteristics have minimal impact on the manufacturing process.
  • the Crosshatch pattern on the surface of the wafer is one limiting characteristic of relaxed SiGe on Si that affects the yield and the ease of manufacture. Greater planarity is desired for high yield and ease in lithography.
  • the origin of the Crosshatch pattern is the stress fields from the injected misfit dislocations. This effect is depicted by the exemplary structure 200 shown in FIG. 2.
  • the dislocations must be introduced in order to accommodate the lattice- mismatch between the SiGe alloy and the Si substrate.
  • the stress fields originate at the dislocations, and are terminated at the surface of the film. However, the termination at the surface creates crystal lattices that vary from place to place on the surface of the wafer. Since growth rate can be correlated to lattice constant size, different thicknesses of deposition occur at different points on the wafer. One may think that thick layer growth beyond the misfit dislocations will smooth the layer of these thickness differences. Unfortunately, the undulations on the surface have a relatively long wavelength; therefore, surface diffusion is typically not great enough to remove the morphology.
  • FIG. 3 is a table that displays surface roughness data for relaxed SiGe buffers produced by dislocation injection via graded SiGe layers on Si substrates. Note that the as-grown Crosshatch pattern for relaxed Si 0.8 Ge 0 . 2 buffers creates a typical roughness of approximately 7.9nm. This average roughness increases as the Ge content in the relaxed buffer is increased. Thus, for any SiGe layer that is relaxed through dislocation introduction during growth, the surface roughness is unacceptable for state-of-the-art fabrication facilities. After the process in which the relaxed SiGe is planarized, the average roughness is less than 2nm (typically 0.57nm), and after device layer deposition, the average roughness is 0.77nm with a 1.5 ⁇ m regrowth thickness.
  • 2nm typically 0.57nm
  • the average roughness is 0.77nm with a 1.5 ⁇ m regrowth thickness.
  • the regrowth device layers can be either greater than or less than the critical thickness of the regrowth layer.
  • thin layers can be deposited without fear of dislocation introduction at the interface.
  • any lattice-mismatch between the film and substrate will introduce misfit dislocations into the regrown heterostructure. These new dislocations can cause additional surface roughness.
  • the lattice-mismatch between the regrowth device layers and relaxed SiGe buffer is too great, the effort of planarizing the relaxed SiGe may be lost since massive dislocation introduction will roughen the surface.
  • the regrowth thickness There are two distinct possibilities with respect to the regrowth thickness and the quality of surface. If the regrowth layers are very thin, then exact lattice matching of the regrowth layer composition and the relaxed buffer composition is not necessary. In this case, the surface roughness will be very low, approximately equal to the post-planarization flatness. However, in many applications for devices, the regrowth layer thickness will be 1 -2 ⁇ m or more. For a 1 % difference in Ge concentration between the relaxed SiGe and the regrowth layer, the critical thickness is approximately 0.5 ⁇ m. Thus, if optimal flatness is desired, it is best to keep the regrowth layer below approximately 0.5 ⁇ m unless excellent control of the uniformity of Ge concentration across the wafer is achieved.
  • FIG.3 shows that less precise matching, i.e., within 2% Ge, results in misfit dislocation introduction and introduction of a new Crosshatch pattern.
  • the lattice mismatch is so small, the average roughness is still very low, approximately 0.77nm. Thus, either lattice-matching or slight mismatch will result in excellent device layer surfaces for processing.
  • the relaxed SiGe alloy with surface roughness may not necessarily be a uniform composition relaxed SiGe layer on a graded composition layer.
  • this material layer structure has been shown to be an early example of high quality relaxed SiGe, there are some disadvantages to this structure.
  • SiGe alloys possess a much worse coefficient of thermal conductivity than pure Si.
  • it may be relatively difficult to guide the heat away from the device areas due to the thick graded composition layer and uniform composition layer.
  • FIGs. 4A-4D show an exemplary process flow and resulting platform structure in accordance with the invention.
  • the structure is produced by first forming a relaxed uniform SiGe alloy 400 via a compositionally graded layer 402 on a Si substrate 404.
  • the SiGe layer 400 is'then transferred to a second Si substrate 406 using conventional bonding.
  • the uniform SiGe alloy 400 on the graded layer 402 can be planarized to remove the Crosshatch pattern, and that relaxed SiGe alloy can be bonded to the Si wafer.
  • the graded layer 402 and the original substrate 404 can be removed by a variety of conventional processes.
  • one process is to grind the original Si substrate away and selectively etch to the SiGe, either by a controlled dry or wet etch, or by embedding an etch stop layer.
  • the end result is a relaxed SiGe alloy 400 on Si without the thick graded layer.
  • This structure is more suited for high power applications since the heat can be conducted away from the SiGe layer more efficiently.
  • the bond and substrate removal technique can also be used to produce SiGe on insulator substrates, or SGOI.
  • An SGOI wafer is produced using the same technique shown in FIGs.4A-4D; however, the second substrate is coated with a Si0 2 layer before bonding. In an alternative embodiment, both wafers can be coated with Si0 2 to enable oxide-to-oxide bonding.
  • the resulting structure after substrate removal is a high quality, relaxed SiGe layer on an insulating film. Devices built on this platform can utilize the performance enhancements of both strained Si and the
  • the SiGe layer is transferred to another host substrate, one may still need to planarize before regrowing the device layer structure.
  • the SiGe surface can be too rough for state of the art processing due to the substrate removal technique.
  • the relaxed SiGe is planarized, and the device layers are regrown on top of the high-quality relaxed SiGe surface.
  • FIGs. 5 and 6 show the process sequence and regrowth layers required to create embodiments of surface channel and buried channel FETs, respectively.
  • FIGs. 5A-5D are schematic diagrams of a process flow and resulting layer structure in accordance with the invention.
  • FIG. 5A shows the surface roughness 500, which is typical of a relaxed SiGe alloy 502 on a substrate 504, as an exaggerated wavy surface.
  • the substrate is labeled in a generic way, since the substrate could itself be Si, a relaxed compositionally graded SiGe layer on Si, or another material in which the relaxed SiGe has been transferred through a wafer bonding and removal technique.
  • the relaxed SiGe alloy 502 is planarized (FIG. 5B) to remove the substantial roughness, and then device regrowth layers 506 are epitaxially deposited (FIG. 5C).
  • FIGs. 6A-6D are schematic diagrams of the corresponding process flow and layer structure for a buried channel FET platform in accordance with the invention.
  • the regrowth layers 606 include a lattice matched SiGe layer 602, a strained Si channel layer 608 with a thickness of less than 0.05 ⁇ m, a SiGe separation or spacer layer
  • a Si gate oxidation layer 614 used to protect the heterostructure during the initial device processing steps.
  • FIGs. 7A-7D This surface channel MOSFET contains a relaxed SiGe layer 700 and a strained Si layer 702.
  • the device isolation oxide 704, depicted in FIG. 7A, is typically formed first.
  • the SiN layer 706, which is on top of a thin pad oxide layer 708, serves as a hard mask for either local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Both techniques use a thick oxide (relative to device dimensions) to provide a high threshold voltage between devices; however, STI is better suited for sub-quarter-micron technologies.
  • Figure 7B is a schematic of the device area after the gate oxide 716 growth and the shallow-source drain implant.
  • the implant regions 710 are self-aligned by using a poly-Si gate 712 patterned with photoresist 714 as a masking layer. Subsequently, deep source-drain implants 718 are positioned using conventional spacer 720 formation and the device is electrically contacted through the formation of suicide 722 at the gate and silicide/germanides 724 at the source and drain (Figure 7C).
  • Figure 7D is a schematic of the device after the first level of metal interconnects 726 have been deposited and etched.
  • the removal of surface material during processing becomes more critical than with standard Si.
  • the structure that is regrown consists primarily of nearly lattice-matched SiGe, and a thin surface layer of strained Si.
  • Many of the processes that are at the beginning of a Si fabrication sequence strip Si from the surface. If the processing is not carefully controlled, the entire strained Si layer can be removed before the gate oxidation. The resulting device will be a relaxed SiGe channel FET and thus the benefits of a strained Si channel will not be realized.
  • a logical solution to combat Si removal during initial processing is to make the strained Si layer thick enough to compensate for this removal.
  • thick Si layers are not possible for two reasons.
  • the enhanced electrical properties originate from the fact that the Si is strained and thick layers experience strain relief through the introduction of misfit dislocations.
  • the misfit dislocations themselves are undesirable in significant quantity, since they can scatter carriers and increase leakage currents injunctions.
  • FIGS. 8 A and 8B Some examples of protective layers for surface channel devices are shown in FIGS. 8 A and 8B.
  • FIG. 8A shows a strained Si heterostructure of a relaxed SiGe layer 800 and a strained Si channel layer 802 protected by a surface layer 804 of SiGe. The surface
  • SiGe layer 804 should have a Ge concentration similar to that of the relaxed SiGe layer 800 below, so that the thickness is not limited by critical thickness constraints.
  • the SiGe sacrificial layer is removed instead of the strained Si channel layer.
  • the thickness of the sacrificial layer can either be tuned to equal the removal thickness, or can be made greater than the removal thickness. In the latter case, the excess SiGe can be selectively removed before the gate oxidation step to reveal a clean, strained Si layer at the as grown thickness. If the particular fabrication facility prefers a Si terminated surface, a sacrificial Si layer may be deposited on top of the SiGe sacrificial cap layer.
  • FIG. 8B shows a structure where a layer 806 of Si0 2 and a surface layer 808 of either a poly-crystalline or an amorphous material are used as protective layers.
  • an oxide layer is either grown or deposited after the epitaxial growth of the strained Si layer.
  • a polycrystalline or amorphous layer of Si, SiGe, or Ge is deposited.
  • These semiconductor layers protect the strained-Si layer in the same manner as a SiGe cap during the processing steps before gate oxidation.
  • the poly/amorphous and oxide layers are selectively removed.
  • the sacrificial layers are shown as protection for a surface channel device, the same techniques can be employed in a buried channel heterostructure.
  • FIG. 7C Another way in which conventional Si processing is modified is during the source-drain silicide-germanide formation (FIG. 7C).
  • a metal typically Ti, Co, or Ni
  • Si silicon
  • the metal reacts with both Si and Ge simultaneously. Since the silicides have much lower free energy than the germanides, there is a tendency to form a suicide while the Ge is expelled. The expelled germanium creates agglomeration and increases the resistance of the contacts. This increase in series resistance offsets the benefits of the extra drive current from the heterostructure, and negates the advantages of the structure.
  • Ti and Ni can form phases in which the Ge is not rejected severely, thus allowing the formation of a good contact. Co is much more problematic.
  • a protective layer(s) at the device epitaxy stage can be applied instead of optimizing the SiGe-metal reaction.
  • the strained Si that will become the surface channel can be coated with a high-Ge-content
  • the first approach shown on a surface channel heterostructure 900 in FIG. 9A, uses a Ge-rich layer 906 thin enough that it is substantially strained.
  • the layer 906 is provided on a strained Si channel layer 904 and relaxed SiGe layer 902.
  • the compressive Ge-rich layer 906 acts as a barrier to dislocations entering the strained Si channel 904. This barrier is beneficial since dislocations do not adversely affect the silicide process; thus, their presence in the subsequent Si layer 908 is of no consequence. However, if the dislocations were to penetrate to the channel, there would be adverse effects on the device.
  • a second approach, shown in FIG. 9B, is to allow a Ge-rich layer 910 to intentionally exceed the critical thickness, thereby causing substantial relaxation in the Ge-rich layer.
  • an arbitrarily thick Si layer 912 can be applied on top of the relaxed Ge-rich layer. This layer will contain more defects than the strained channel, but the defects play no role in device operation since this Si is relevant only in the silicide reaction. In both cases, the process is free from the metal-SiGe reaction concerns, since the metal will react with Si-only.
  • Si/SiGe FET heterostructures to achieve enhanced performance is the compatibility with conventional Si techniques. Many of the processes are identical to Si CMOS processing, and once the front-end of the process, i.e., the processing of the Si/SiGe heterostructure, is complete, the entire back-end process is uninfluenced by the fact that Si/SiGe lies below. Even though the starting heterostructure for the buried channel device is different from that of the surface channel device, its process flow is very similar to the surface
  • FIG. 10 is a schematic block diagram of a buried channel MOSFET structure 1000 after the device isolation oxide 1016 has been formed using a SiN mask 1014.
  • the strained channel 1002 on a first SiGe layer 1010 is separated from the surface by the growth of another SiGe layer 1004, followed by another Si layer 1006.
  • This Si layer is needed for the gate oxide 1008 since gate-oxide formation on SiGe produces a very high interface state density, thus creating non-ideal
  • Si layer Si is kept as thin as possible, typically less than 5 ⁇ A and ideally in the range of 5-15A.
  • a supply layer implant Another added feature that is necessary for a buried channel device is the supply layer implant.
  • the field experienced in the vertical direction when the device is turned on is strong enough to pull carriers from the buried channel 1002 and force them to populate a Si channel 1006 near the Si/Si0 2 interface 1012, thus destroying any advantage of the buried channel.
  • a supply layer of dopant must be introduced either in the layer 1004 between the buried channel and the top Si layer 1006, or below the buried channel in the underlying SiGe 1010. In this way, the device is forced on with little or no applied voltage, and turned off by applying a voltage (depletion mode device).
  • FIG. 11 is a schematic flow of the process, for any heterostructure FET device deposited on relaxed SiGe, in accordance with the invention.
  • the main process steps are shown in the boxes, and optional steps or comments are shown in the circles.
  • the first three steps (1100,1102,1104) describe the fabrication of the strained silicon heterostructure.
  • the sequence includes production of relaxed SiGe on Si, planarization of the SiGe, and regrowth of the device layers.
  • MOS fabrication begins with device isolation (1112) using either STI (1110) or LOCOS (1108).
  • buried channel devices undergo a supply and threshold implant (1114), and any protective layers applied to either a buried or surface channel heterostructure must be selectively removed (1116).
  • the processing sequence after the gate oxidation (1118) is similar to conventional Si CMOS processing. These steps include gate deposition, doping, and definition (1120), self-aligned shallow source-drain implant (1122), spacer formation (1124), self-aligned deep source-drain implant (1126), salicide formation (1128), and pad isolation via metal deposition and etch (1130). The steps requiring significant alteration have been discussed.
  • FIG. 11 One particular advantage of the process of FIG. 11 is that it enables the use of surface channel and buried channel devices on the same platform. Consider FIGs.
  • FIGs. 12A-12D and FIGs. 13A-13D show a universal substrate layer configuration and a process that leads to the co-habitation of surface and buried channel MOSFETs on the same chip.
  • the universal substrate is one in which both surface channel and buried channel devices can be fabricated.
  • FIGs. 12 and 13 There are two possibilities in fabricating the surface channel device in this sequence, shown in FIGs. 12 and 13.
  • the process flows for combining surface and buried channel are similar to the previous process described in FIG. 7. Therefore, only the critical steps involved in exposing the proper gate areas are shown in FIGs. 12 and 13.
  • FIGs. 12A and 13A depict the same basic heterostructure 1200,1300 for integrating surface channel and buried channel devices.
  • Two strained Si layers are necessary because the buried channel MOSFET requires a surface Si layer to form the gate oxide and a buried Si layer to form the device channel.
  • the figures also show a device isolation region 1210 that separates the buried channel device area 1212,1312 from the surface channel device area 1214,1314. Unlike the buried channel device, a surface channel MOSFET only requires one strained Si layer.
  • FIG. 12B is a schematic diagram of a surface channel gate oxidation 1216 in the top Si layer 1202.
  • a thicker top Si layer is desired, since after oxidation, a residual strained Si layer must be present to form the channel.
  • FIG. 12B also shows a possible position for the buried channel supply implant 1218, which is usually implanted before the buried channel gate oxide is grown.
  • top Si layer is optimized for the surface channel device, it may be necessary to strip some of the top strained Si in the regions 1220 where buried channel devices are being created, as shown in FIG. 12C. This removal is necessary in order to minimize the surface Si thickness after gate oxide 1222 formation (FIG. 12D), and thus avoid the formation of a parallel device channel.
  • the top strained Si layer can be thin, i.e., designed optimally for the buried channel MOSFET.
  • FIG. 13B the top strained Si and SiGe layers are removed in the region 1312 where the surface charmel MOSFETs are formed.
  • a range of selective removal techniques' can be used, such as wet or dry chemical etching. Selective oxidation can also be used since SiGe oxidizes at much higher rates than Si, especially under wet oxidation conditions.
  • FIG. 13C shows the gate oxidation 1314 of the surface channel device as well as the supply layer implant 1316 for the buried channel device.
  • 13D shows the position of the buried channel gate oxide 1318. No thinning of the top Si layer is required prior to the oxidation since the epitaxial thickness is optimized for the buried channel device. Subsequent to these initial steps, the processing for each device proceeds as previously described. Another key step in the process is the use of a localized implant to create the supply layer needed in the buried channel device. In a MOSFET structure, when the channel is turned on, large vertical fields are present that bring carriers to the surface. The band offset between the Si and SiGe that confines the electrons in the buried strained Si layer is not large enough to prevent carriers from being pulled out of the buried channel. Thus, at first, the buried channel MOSFET would appear useless.
  • the MOSFET would become a depletion-mode device, i.e. normally on and requiring bias to turn off the channel.
  • a supply layer implant can be created in the regions where the buried channel will be fabricated, thus easing process integration. If for some reason the supply layer implant is not possible, note that the process shown in FIG. 11 in which the surface channel is created on the buried Si layer is an acceptable process, since the dopant can be introduced into the top SiGe layer during epitaxial growth. The supply layer is then removed from the surface channel MOSFET areas when the top SiGe and strained Si layers are selectively etched away. In the processes described in FIGs.
  • MOSFET the self-aligned nature can be a great advantage in device performance.
  • MOSFET structure Another benefit of the MOSFET structure is that the gate leakage is very low.
  • FIGs. 14A and 14B are schematic diagrams of surface 1400 and buried
  • the devices are shown after salicidation and thus contain a poly-Si gate 1410, gate oxide 1408, silicide regions 1412, spacers 1414, and doped regions 1416.
  • a thin layer 1406 of Si must be deposited onto the Si ⁇ .
  • the device layer sequence is unchanged and consists of a buried strained channel 1402, a SiGe spacer layer 1418, and a surface Si layer 1420 for oxidation.
  • the lattice constant of the channel layer must be less than that of the relaxed SiGe layer, i.e., y must be less than z. Since n-channel devices are sensitive to alloy scattering, the highest mobilities result when the Ge concentration in the channel is low. In order to have strain on this channel layer at a reasonable critical thickness, the underlying SiGe should have a Ge concentration in the range of 10-50%.
  • enhancement mode surface channel devices n and p channel, through implants as in typical Si CMOS technology
  • depletion-mode buried channel MOSFETs and MODFETs it is possible to create highly integrated digital analog systems.
  • the enhancement mode devices can be fabricated into high performance CMOS, and the regions of an analog circuit requiring the high performance low-noise depletion mode device can be fabricated in the buried channel regions.
  • optimal communication stages, digital processing stages, etc. on a single platform. These different regions are connected electrically in the backend of the
  • Si CMOS chip just as transistors are connected by the back-end technology today.
  • the only changes to the CMOS process are some parameters in the processes in the fabrication facility, and the new material, but otherwise, the entire manufacturing process is transparent to the change.
  • the economics favor such a platform for integrated Si

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Abstract

L'invention concerne des structures et des procédés permettant la fabrication de systèmes numériques, analogiques, et mixtes analogiques/numériques grande vitgesse à plate-forme au SiGe planarisée et relâchée. Ce type de plate-forme permet d'établir une grande quantité de couches au Si contraintes offrant des propriétés électroniques améliorées. Le fait qu'il soit possible de laisser le canal de transistor MOS en surface ou d'enfouir ce canal permet d'établir des circuits numériques et/ou analogiques grande vitesse. La planarisation qui intervient avant le dépôt des couches épitaxiales du dispositif assure la mise en place d'une surface plate pour les besoins des techniques existantes de lithographie.
PCT/US2002/003688 2001-03-02 2002-02-07 Plate-forme au silicium-germanium relachee pour electronique cmos grande vitesse et circuits analogiques grande vitesse WO2002071491A1 (fr)

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US09/906,200 US6703688B1 (en) 2001-03-02 2001-07-16 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US09/906,201 US6723661B2 (en) 2001-03-02 2001-07-16 Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
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US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
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US7217603B2 (en) 2002-06-25 2007-05-15 Amberwave Systems Corporation Methods of forming reacted conductive gate electrodes
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US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors

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US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6921914B2 (en) 2000-08-16 2005-07-26 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
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US7301180B2 (en) 2001-06-18 2007-11-27 Massachusetts Institute Of Technology Structure and method for a high-speed semiconductor device having a Ge channel layer
US6916727B2 (en) 2001-06-21 2005-07-12 Massachusetts Institute Of Technology Enhancement of P-type metal-oxide-semiconductor field effect transistors
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US7259388B2 (en) 2002-06-07 2007-08-21 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7297612B2 (en) 2002-06-07 2007-11-20 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes
US7109516B2 (en) 2002-06-07 2006-09-19 Amberwave Systems Corporation Strained-semiconductor-on-insulator finFET device structures
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7588994B2 (en) 2002-06-07 2009-09-15 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7420201B2 (en) 2002-06-07 2008-09-02 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures with elevated source/drain regions
US7414259B2 (en) 2002-06-07 2008-08-19 Amberwave Systems Corporation Strained germanium-on-insulator device structures
US7122449B2 (en) 2002-06-10 2006-10-17 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US7439164B2 (en) 2002-06-10 2008-10-21 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US7217603B2 (en) 2002-06-25 2007-05-15 Amberwave Systems Corporation Methods of forming reacted conductive gate electrodes
US8129821B2 (en) 2002-06-25 2012-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Reacted conductive gate electrodes
US7534701B2 (en) 2002-07-09 2009-05-19 S.O.I. Tec Silicon On Insulator Technologies Process for transferring a layer of strained semiconductor material
US7510949B2 (en) 2002-07-09 2009-03-31 S.O.I.Tec Silicon On Insulator Technologies Methods for producing a multilayer semiconductor structure
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US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
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