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JPS6428945A - Circuit package assembly - Google Patents

Circuit package assembly

Info

Publication number
JPS6428945A
JPS6428945A JP63095826A JP9582688A JPS6428945A JP S6428945 A JPS6428945 A JP S6428945A JP 63095826 A JP63095826 A JP 63095826A JP 9582688 A JP9582688 A JP 9582688A JP S6428945 A JPS6428945 A JP S6428945A
Authority
JP
Japan
Prior art keywords
integrated circuit
lead frame
circuit device
pad
finger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63095826A
Other languages
English (en)
Other versions
JPH0831560B2 (ja
Inventor
Waaresu Fuiritsupusu Dagurasu
Jieemuzu Retsudomondo Robaato
Kaaroru Waado Buiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6428945A publication Critical patent/JPS6428945A/ja
Publication of JPH0831560B2 publication Critical patent/JPH0831560B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Credit Cards Or The Like (AREA)
JP63095826A 1987-06-15 1988-04-20 回路パツケージ・アセンブリ Expired - Lifetime JPH0831560B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61361 1987-06-15
US07/061,361 US4796078A (en) 1987-06-15 1987-06-15 Peripheral/area wire bonding technique

Publications (2)

Publication Number Publication Date
JPS6428945A true JPS6428945A (en) 1989-01-31
JPH0831560B2 JPH0831560B2 (ja) 1996-03-27

Family

ID=22035304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63095826A Expired - Lifetime JPH0831560B2 (ja) 1987-06-15 1988-04-20 回路パツケージ・アセンブリ

Country Status (3)

Country Link
US (1) US4796078A (ja)
EP (1) EP0295459A3 (ja)
JP (1) JPH0831560B2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124503A (en) * 1990-12-13 1992-06-23 Allied-Signal Inc. Dichlorotrifluoroethane stabilized to minimize hydrolysis thereof
US5380449A (en) * 1991-04-05 1995-01-10 Alliedsignal Inc. Stabilized dichlorotrifluoroethane refrigeration compositions
JP2013513969A (ja) * 2009-12-15 2013-04-22 シリコン ストーリッジ テクノロージー インコーポレイテッド パネルベースのリードフレームパッケージング方法及び装置

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US5184208A (en) * 1987-06-30 1993-02-02 Hitachi, Ltd. Semiconductor device
US5365113A (en) * 1987-06-30 1994-11-15 Hitachi, Ltd. Semiconductor device
JP2708191B2 (ja) * 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
JP2522524B2 (ja) * 1988-08-06 1996-08-07 株式会社東芝 半導体装置の製造方法
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
US5311056A (en) * 1988-10-21 1994-05-10 Shinko Electric Industries Co., Ltd. Semiconductor device having a bi-level leadframe
US5099306A (en) * 1988-11-21 1992-03-24 Honeywell Inc. Stacked tab leadframe assembly
US5089878A (en) * 1989-06-09 1992-02-18 Lee Jaesup N Low impedance packaging
US4987473A (en) * 1989-08-03 1991-01-22 Vlsi Technology, Inc. Leadframe system with multi-tier leads
US5291060A (en) * 1989-10-16 1994-03-01 Shinko Electric Industries Co., Ltd. Lead frame and semiconductor device using same
US5237202A (en) * 1989-10-16 1993-08-17 Shinko Electric Industries Co., Ltd Lead frame and semiconductor device using same
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
US5256903A (en) * 1990-02-28 1993-10-26 Hitachi Ltd. Plastic encapsulated semiconductor device
JPH0760837B2 (ja) * 1990-03-13 1995-06-28 株式会社東芝 樹脂封止型半導体装置
US5147815A (en) * 1990-05-14 1992-09-15 Motorola, Inc. Method for fabricating a multichip semiconductor device having two interdigitated leadframes
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
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US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
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JP2501246B2 (ja) * 1991-01-21 1996-05-29 株式会社東芝 半導体装置
KR940006164B1 (ko) * 1991-05-11 1994-07-08 금성일렉트론 주식회사 반도체 패키지 및 그 제조방법
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JP2932785B2 (ja) * 1991-09-20 1999-08-09 富士通株式会社 半導体装置
JP2609382B2 (ja) * 1991-10-01 1997-05-14 三菱電機株式会社 半導体装置
JP2634516B2 (ja) * 1991-10-15 1997-07-30 三菱電機株式会社 反転型icの製造方法、反転型ic、icモジュール
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US5455740A (en) * 1994-03-07 1995-10-03 Staktek Corporation Bus communication system for stacked high density integrated circuit packages
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JPS5229060U (ja) * 1975-08-20 1977-03-01
JPS61241959A (ja) * 1985-04-18 1986-10-28 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 半導体モジユ−ル
JPS6240752A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd 半導体装置

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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS5229060U (ja) * 1975-08-20 1977-03-01
JPS61241959A (ja) * 1985-04-18 1986-10-28 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 半導体モジユ−ル
JPS6240752A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5124503A (en) * 1990-12-13 1992-06-23 Allied-Signal Inc. Dichlorotrifluoroethane stabilized to minimize hydrolysis thereof
US5380449A (en) * 1991-04-05 1995-01-10 Alliedsignal Inc. Stabilized dichlorotrifluoroethane refrigeration compositions
JP2013513969A (ja) * 2009-12-15 2013-04-22 シリコン ストーリッジ テクノロージー インコーポレイテッド パネルベースのリードフレームパッケージング方法及び装置

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Publication number Publication date
EP0295459A3 (en) 1989-10-18
EP0295459A2 (en) 1988-12-21
US4796078A (en) 1989-01-03
JPH0831560B2 (ja) 1996-03-27

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