KR930007920Y1 - 양면 박막회로판을 갖는 이중 패키지 구조 - Google Patents
양면 박막회로판을 갖는 이중 패키지 구조 Download PDFInfo
- Publication number
- KR930007920Y1 KR930007920Y1 KR2019900017385U KR900017385U KR930007920Y1 KR 930007920 Y1 KR930007920 Y1 KR 930007920Y1 KR 2019900017385 U KR2019900017385 U KR 2019900017385U KR 900017385 U KR900017385 U KR 900017385U KR 930007920 Y1 KR930007920 Y1 KR 930007920Y1
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- double
- circuit board
- film circuit
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000012212 insulator Substances 0.000 claims description 3
- 230000010354 integration Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (1)
- 양면 박막회로판을 이용하여 두개의 칩을 하나의 패키지에 내장시킴에 있어서, 반도체 칩(11, 12)과 양면 박막회로판 내의 회로를 연결하기 위한 패드(17, 18), 리드(15)와 반도체 칩(11, 12) 사이를 연결하는 박막회로판 리드(19), 박막회로의 다층화를 위한 절연체(20, 20A, 20B)로 구성된 것을 특징으로 하는 양면 박막회로판을 갖는 이중 패키지구조.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019900017385U KR930007920Y1 (ko) | 1990-11-13 | 1990-11-13 | 양면 박막회로판을 갖는 이중 패키지 구조 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019900017385U KR930007920Y1 (ko) | 1990-11-13 | 1990-11-13 | 양면 박막회로판을 갖는 이중 패키지 구조 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920010423U KR920010423U (ko) | 1992-06-17 |
KR930007920Y1 true KR930007920Y1 (ko) | 1993-11-24 |
Family
ID=19305338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019900017385U Expired - Fee Related KR930007920Y1 (ko) | 1990-11-13 | 1990-11-13 | 양면 박막회로판을 갖는 이중 패키지 구조 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR930007920Y1 (ko) |
-
1990
- 1990-11-13 KR KR2019900017385U patent/KR930007920Y1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR920010423U (ko) | 1992-06-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
UA0108 | Application for utility model registration |
Comment text: Application for Utility Model Registration Patent event code: UA01011R08D Patent event date: 19901113 |
|
UA0201 | Request for examination |
Patent event date: 19901113 Patent event code: UA02012R01D Comment text: Request for Examination of Application |
|
UG1501 | Laying open of application | ||
UG1604 | Publication of application |
Patent event code: UG16041S01I Comment text: Decision on Publication of Application Patent event date: 19931030 |
|
E701 | Decision to grant or registration of patent right | ||
UE0701 | Decision of registration |
Patent event date: 19940218 Comment text: Decision to Grant Registration Patent event code: UE07011S01D |
|
REGI | Registration of establishment | ||
UR0701 | Registration of establishment |
Patent event date: 19940314 Patent event code: UR07011E01D Comment text: Registration of Establishment |
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UR1002 | Payment of registration fee |
Start annual number: 1 End annual number: 3 Payment date: 19940314 |
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UR1001 | Payment of annual fee |
Payment date: 19961101 Start annual number: 4 End annual number: 4 |
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UR1001 | Payment of annual fee |
Payment date: 19971031 Start annual number: 5 End annual number: 5 |
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UR1001 | Payment of annual fee |
Payment date: 19981030 Start annual number: 6 End annual number: 6 |
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UR1001 | Payment of annual fee |
Payment date: 19991101 Start annual number: 7 End annual number: 7 |
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UR1001 | Payment of annual fee |
Payment date: 20001019 Start annual number: 8 End annual number: 8 |
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UR1001 | Payment of annual fee |
Payment date: 20011017 Start annual number: 9 End annual number: 9 |
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FPAY | Annual fee payment |
Payment date: 20021018 Year of fee payment: 10 |
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UR1001 | Payment of annual fee |
Payment date: 20021018 Start annual number: 10 End annual number: 10 |
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LAPS | Lapse due to unpaid annual fee | ||
UC1903 | Unpaid annual fee |