[go: up one dir, main page]

JPS622626A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS622626A
JPS622626A JP60141712A JP14171285A JPS622626A JP S622626 A JPS622626 A JP S622626A JP 60141712 A JP60141712 A JP 60141712A JP 14171285 A JP14171285 A JP 14171285A JP S622626 A JPS622626 A JP S622626A
Authority
JP
Japan
Prior art keywords
mount base
leads
lead
semiconductor element
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60141712A
Other languages
Japanese (ja)
Inventor
Kaoru Sonobe
薫 園部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60141712A priority Critical patent/JPS622626A/en
Publication of JPS622626A publication Critical patent/JPS622626A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent deformation of the top of the lead, vertical deformation of the mount base, solder extension to the mount base leads, etc. and make it possible to perform stably the wire-bonding, by covering and fixing the mount base and the top part of the lead with an insulating plate. CONSTITUTION:An insulating plate 5 is fixed on the edge surface of the mount base 2 which mounts the semiconductor element 1 and the surfaces of the top parts 7 of a plurality of leads 4. A thin plate of ceramic, polyimide, etc., for example, can be used as the insulating plate, which covers and fixes the top parts 7 of the leads 4 and the mount base 2 of the semiconductor element. In this manner, the positional deviation of the top parts 7 of the leads 4 and the contact of the metal thin wires 3 with the mount base 2 can be prevented, and the floating deformation of the mount base 2 also can be reduced. Thus, the extension of Au-Si eutectic alloy to the mount base leads 8 connecting to the mount base 2 can be prevented, where the extension occurs at the time of fixing semiconductor elements.

Description

【発明の詳細な説明】 （産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

一般に半導体装置は、半導体素子をリードフレームの半
導体素子搭載台にソルダー等により固着させたのち、半
導体素子とリードフレームのリードとを金属細線で接続
して製造される。Generally, a semiconductor device is manufactured by fixing a semiconductor element to a semiconductor element mounting base of a lead frame using solder or the like, and then connecting the semiconductor element and the leads of the lead frame with thin metal wires.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置は、第３図（ａ）。 The conventional semiconductor device described above is shown in FIG. 3(a).

（ｂ）に示すように、リード４の先端部７が製造工程中
に位置ずれを生じ、半導体素子１とリード４を金属細線
３にて導通がとれるようにするワイヤボンディングする
工程において、リードの先端部７に金属細線３が結線さ
れなかったり、または金属細線３にたれを生じ、半導体
素子の搭載台２とショートするという欠点があった。As shown in (b), the tip end 7 of the lead 4 is misaligned during the manufacturing process, and in the wire bonding process to establish electrical continuity between the semiconductor element 1 and the lead 4 using the thin metal wire 3, the lead There is a drawback that the thin metal wire 3 is not connected to the tip 7 or the thin metal wire 3 sags, resulting in a short circuit with the mounting base 2 for the semiconductor element.

また、半導体素子１を搭載台２に固着するダイアタッチ
工程において、半導体素子１の位置が搭載台２の中心位
置からずれて搭載された場合に金属、ｌｌｌｍ３が隣接
リードとショートしたり、あるいはたれを生じ搭載台２
とショートしてしまう等の欠点があった。Furthermore, in the die attach process for fixing the semiconductor element 1 to the mounting base 2, if the position of the semiconductor element 1 is shifted from the center position of the mounting base 2, the metal llm3 may short-circuit with adjacent leads or sag. The mounting base 2
There were drawbacks such as short circuits.

本発明の目的は、上記欠点を除去し、ワイヤボンディン
グが正確に安定して行なわれ、金属細線のショートがな
い信頼性の高い半導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable semiconductor device in which wire bonding is performed accurately and stably and there is no short-circuiting of thin metal wires.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置は、半導体素子が搭載される搭載台
と金属細線により半導体素子に接続される複数のリード
とを有する半導体装置であって、前記搭載台表面と前記
リードの先端部表面とを覆って固着された絶縁板を有す
るものである。A semiconductor device of the present invention is a semiconductor device having a mounting base on which a semiconductor element is mounted and a plurality of leads connected to the semiconductor element by thin metal wires, the surface of the mounting base and the surface of the tip of the lead. It has an insulating plate fixed over it.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第１図（ａ）、（ｂ）は、本発明の一実施例の平面図及
びＡ−Ａ’断面図である。FIGS. 1(a) and 1(b) are a plan view and an AA' cross-sectional view of an embodiment of the present invention.

第１図（ａ）、（ｂ）において半導体素子１を搭載する
搭載台２の端部表面と複数のリード４の先端部７表面に
は絶縁板５が固着されている。絶縁板としては例えばセ
ラミックやポリイミド等の薄板を用ることかできる。In FIGS. 1A and 1B, an insulating plate 5 is fixed to the end surface of the mounting base 2 on which the semiconductor element 1 is mounted and to the surface of the tip ends 7 of the plurality of leads 4. In FIGS. As the insulating plate, for example, a thin plate made of ceramic or polyimide may be used.

このようにリード４の先端部７と半導体素子の搭載台２
を被覆かつ固定することにより、リード先端部７の位置
ずれや金属細線３の搭載台２への接触を防止でき、かつ
、搭載台２の浮き変形も低減することができた。また、
半導体素子固着時に生じる搭載台２に連結している搭載
台リード８へ。In this way, the tip 7 of the lead 4 and the mounting base 2 for the semiconductor element are connected.
By covering and fixing, it was possible to prevent the lead tip 7 from shifting and the thin metal wire 3 from coming into contact with the mounting base 2, and also to reduce floating deformation of the mounting base 2. Also,
To the mounting base lead 8 connected to the mounting base 2 that occurs when the semiconductor element is fixed.

のＡｕ−５ｉ共晶合金等の伸びを防止することも可能と
なった。It has also become possible to prevent the elongation of Au-5i eutectic alloys and the like.

第２図（ａ）、（ｂ）は、本発明の池の実施例の平面図
及びＹ　−Ｙ　’断面であり、セラミックからなる絶縁
板５が搭載台２の表面全体を覆って固着された場合を示
している。本実施例はＡｇベースト材等のソルダーを用
いてダイ・アタッチする際に有効である。FIGS. 2(a) and 2(b) are a plan view and a Y-Y' cross section of an embodiment of the pond of the present invention, in which an insulating plate 5 made of ceramic is fixed to cover the entire surface of the mounting base 2. It shows the case. This embodiment is effective when die attaching is performed using a solder such as an Ag-based material.

（発明の効果〕 以」二説明したように、本発明は、半導体素子の搭載台
とリード先端部を絶縁板にて被覆かつ固着することによ
り、リード先端の変形、搭載台の上下方向の変形、ソル
ダーの搭載台リードへの伸び等を防止することができ、
ワイヤボンディングを安定して行なうことが可能となっ
た。同時に、ワイヤボンディング後における金属細線の
たれによる半導体素子の搭載台とのショート及びリード
先端の隣接リード等とのショート不良を無くすことがで
き信頼性を高める効果がある。(Effects of the Invention) As explained in Section 2 below, the present invention covers and fixes the semiconductor element mounting base and the lead tip with an insulating plate, thereby preventing deformation of the lead tip and vertical deformation of the mounting base. , it is possible to prevent the solder from stretching onto the lead of the mounting table,
It has become possible to perform wire bonding stably. At the same time, it is possible to eliminate short-circuits with the mounting base of the semiconductor element and short-circuits between the lead tips and adjacent leads due to sagging of the thin metal wires after wire bonding, thereby improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ＞、（ｂ）は本発明の一実施例を示す平面図
、及び断面図、第２図（ａ）、（ｂ）は本発明の他の実
施例を示す平面図及び断面図、第３図（ａ）、（１））
は従来の半導体装置の構造を説明するための平面図及び
断面図である。 １・・・半導体素子、２・・・搭載台、３・・・金属細
線、４・・・リード、５・・・絶縁板、７・・・リード
先端部、８・・・搭載台リード。 代理人　弁理士　　内　原　　昔 ＄　１　　図 茅　３１！ＩFIGS. 1(a) and (b) are a plan view and a sectional view showing one embodiment of the present invention, and FIGS. 2(a) and (b) are a plan view and a sectional view showing another embodiment of the present invention. Figure 3 (a), (1))
1A and 1B are a plan view and a cross-sectional view for explaining the structure of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Mounting stand, 3... Metal thin wire, 4... Lead, 5... Insulating plate, 7... Lead tip, 8... Mounting stand lead. Agent Patent Attorney Uchihara Former $ 1 Figure 31! I

Claims (1)

【特許請求の範囲】[Claims] 半導体素子が搭載される搭載台と、金属細線により前記
半導体素子に接続される複数のリードとを有する半導体
装置において、前記搭載台表面と前記リードの先端部表
面とを覆って固着された絶縁板を有することを特徴とす
る半導体装置。In a semiconductor device having a mounting base on which a semiconductor element is mounted and a plurality of leads connected to the semiconductor element by thin metal wires, an insulating plate is fixed to cover the surface of the mounting base and the surface of the tip of the lead. A semiconductor device characterized by having:
JP60141712A 1985-06-28 1985-06-28 Semiconductor device Pending JPS622626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60141712A JPS622626A (en) 1985-06-28 1985-06-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60141712A JPS622626A (en) 1985-06-28 1985-06-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS622626A true JPS622626A (en) 1987-01-08

Family

ID=15298443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60141712A Pending JPS622626A (en) 1985-06-28 1985-06-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS622626A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165846U (en) * 1987-04-17 1988-10-28
JPH01503184A (en) * 1987-05-13 1989-10-26 エルエスアイ　ロジック　コーポレーション integrated circuit device package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165846U (en) * 1987-04-17 1988-10-28
JPH01503184A (en) * 1987-05-13 1989-10-26 エルエスアイ　ロジック　コーポレーション integrated circuit device package

Similar Documents

Publication Publication Date Title
US5408127A (en) Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components
JPS63124434A (en) Manufacture of semiconductor device
US5606204A (en) Resin-sealed semiconductor device
JPS622626A (en) Semiconductor device
JPH0817870A (en) Semiconductor device
JPH08148623A (en) Semiconductor device
JPS61279141A (en) Direct connection apparatus and method for lead frame with flexible tapered lead and mechanical die support
JPH03261153A (en) Package for semiconductor device
JPS63104458A (en) Semiconductor device
JPS62235763A (en) Lead frame for semiconductor device
JPS6228780Y2 (en)
JP2652222B2 (en) Substrate for mounting electronic components
JP2871575B2 (en) Lead frame, method of manufacturing the same, resin-sealed semiconductor device and method of manufacturing the same
JP2000196004A (en) Semiconductor device lead frame and semiconductor device using the same
JPH02308563A (en) Lead frame
JP2822446B2 (en) Hybrid integrated circuit device
JPS59189659A (en) Semiconductor device
JPH07201928A (en) Film carrier and semiconductor device
JPS62134957A (en) Semiconductor device
JPS6043660B2 (en) semiconductor equipment
JPH0513011Y2 (en)
KR200169976Y1 (en) Semiconductor package
JPS60251636A (en) Semiconductor device
JPS61280639A (en) Semiconductor device
JPS63122131A (en) Carrier tape for semiconductor device