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JPS622626A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS622626A
JPS622626A JP60141712A JP14171285A JPS622626A JP S622626 A JPS622626 A JP S622626A JP 60141712 A JP60141712 A JP 60141712A JP 14171285 A JP14171285 A JP 14171285A JP S622626 A JPS622626 A JP S622626A
Authority
JP
Japan
Prior art keywords
mount base
leads
lead
semiconductor element
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60141712A
Other languages
English (en)
Inventor
Kaoru Sonobe
薫 園部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60141712A priority Critical patent/JPS622626A/ja
Publication of JPS622626A publication Critical patent/JPS622626A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野〕 本発明は半導体装置に関する。
〔従来の技術〕
一般に半導体装置は、半導体素子をリードフレームの半
導体素子搭載台にソルダー等により固着させたのち、半
導体素子とリードフレームのリードとを金属細線で接続
して製造される。
〔発明が解決しようとする問題点〕
上述した従来の半導体装置は、第３図（ａ）。
（ｂ）に示すように、リード４の先端部７が製造工程中
に位置ずれを生じ、半導体素子１とリード４を金属細線
３にて導通がとれるようにするワイヤボンディングする
工程において、リードの先端部７に金属細線３が結線さ
れなかったり、または金属細線３にたれを生じ、半導体
素子の搭載台２とショートするという欠点があった。
また、半導体素子１を搭載台２に固着するダイアタッチ
工程において、半導体素子１の位置が搭載台２の中心位
置からずれて搭載された場合に金属、ｌｌｌｍ３が隣接
リードとショートしたり、あるいはたれを生じ搭載台２
とショートしてしまう等の欠点があった。
本発明の目的は、上記欠点を除去し、ワイヤボンディン
グが正確に安定して行なわれ、金属細線のショートがな
い信頼性の高い半導体装置を提供することにある。
〔問題点を解決するための手段〕
本発明の半導体装置は、半導体素子が搭載される搭載台
と金属細線により半導体素子に接続される複数のリード
とを有する半導体装置であって、前記搭載台表面と前記
リードの先端部表面とを覆って固着された絶縁板を有す
るものである。
〔実施例〕
以下、本発明の実施例について図面を参照して説明する
。
第１図（ａ）、（ｂ）は、本発明の一実施例の平面図及
びＡ−Ａ’断面図である。
第１図（ａ）、（ｂ）において半導体素子１を搭載する
搭載台２の端部表面と複数のリード４の先端部７表面に
は絶縁板５が固着されている。絶縁板としては例えばセ
ラミックやポリイミド等の薄板を用ることかできる。
このようにリード４の先端部７と半導体素子の搭載台２
を被覆かつ固定することにより、リード先端部７の位置
ずれや金属細線３の搭載台２への接触を防止でき、かつ
、搭載台２の浮き変形も低減することができた。また、
半導体素子固着時に生じる搭載台２に連結している搭載
台リード８へ。
のＡｕ−５ｉ共晶合金等の伸びを防止することも可能と
なった。
第２図（ａ）、（ｂ）は、本発明の池の実施例の平面図
及びＹ　−Ｙ　’断面であり、セラミックからなる絶縁
板５が搭載台２の表面全体を覆って固着された場合を示
している。本実施例はＡｇベースト材等のソルダーを用
いてダイ・アタッチする際に有効である。
（発明の効果〕 以」二説明したように、本発明は、半導体素子の搭載台
とリード先端部を絶縁板にて被覆かつ固着することによ
り、リード先端の変形、搭載台の上下方向の変形、ソル
ダーの搭載台リードへの伸び等を防止することができ、
ワイヤボンディングを安定して行なうことが可能となっ
た。同時に、ワイヤボンディング後における金属細線の
たれによる半導体素子の搭載台とのショート及びリード
先端の隣接リード等とのショート不良を無くすことがで
き信頼性を高める効果がある。
【図面の簡単な説明】
第１図（ａ＞、（ｂ）は本発明の一実施例を示す平面図
、及び断面図、第２図（ａ）、（ｂ）は本発明の他の実
施例を示す平面図及び断面図、第３図（ａ）、（１））
は従来の半導体装置の構造を説明するための平面図及び
断面図である。 １・・・半導体素子、２・・・搭載台、３・・・金属細
線、４・・・リード、５・・・絶縁板、７・・・リード
先端部、８・・・搭載台リード。 代理人　弁理士　　内　原　　昔 ＄　１　　図 茅　３１！Ｉ

Claims (1)

    【特許請求の範囲】
  1. 半導体素子が搭載される搭載台と、金属細線により前記
    半導体素子に接続される複数のリードとを有する半導体
    装置において、前記搭載台表面と前記リードの先端部表
    面とを覆って固着された絶縁板を有することを特徴とす
    る半導体装置。
JP60141712A 1985-06-28 1985-06-28 半導体装置 Pending JPS622626A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60141712A JPS622626A (ja) 1985-06-28 1985-06-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60141712A JPS622626A (ja) 1985-06-28 1985-06-28 半導体装置

Publications (1)

Publication Number Publication Date
JPS622626A true JPS622626A (ja) 1987-01-08

Family

ID=15298443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60141712A Pending JPS622626A (ja) 1985-06-28 1985-06-28 半導体装置

Country Status (1)

Country Link
JP (1) JPS622626A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165846U (ja) * 1987-04-17 1988-10-28
JPH01503184A (ja) * 1987-05-13 1989-10-26 エルエスアイ　ロジック　コーポレーション 集積回路装置パッケージ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165846U (ja) * 1987-04-17 1988-10-28
JPH01503184A (ja) * 1987-05-13 1989-10-26 エルエスアイ　ロジック　コーポレーション 集積回路装置パッケージ

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