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JPS63104458A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63104458A
JPS63104458A JP25233986A JP25233986A JPS63104458A JP S63104458 A JPS63104458 A JP S63104458A JP 25233986 A JP25233986 A JP 25233986A JP 25233986 A JP25233986 A JP 25233986A JP S63104458 A JPS63104458 A JP S63104458A
Authority
JP
Japan
Prior art keywords
tub
heat sinking
semiconductor device
external lead
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25233986A
Other languages
Japanese (ja)
Inventor
Yoshihiro Horie
堀江 義弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25233986A priority Critical patent/JPS63104458A/en
Publication of JPS63104458A publication Critical patent/JPS63104458A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the positioning deviation of an external lead and the occurrence of a defective bend, to improve the efficiency of a mounting operation and a bonding operation and to reduce a defect due to a short circuit by a method wherein, after the tip part of the external lead has been kept installed at the heat sinking tub and electrodes of a semiconductor device are connected by a metal thin wire, the underside of the heat sinking tub is exposed for resin-sealing. CONSTITUTION:A semiconductor device 1 is mounted on the surface of a heat sinking tub; an insulating material is formed on the surface of the heat sinking tub 2 except the area where the semiconductor device is mounted; the tip part of an external lead 5 is kept on the surface of the heat sinking tub 2 by means of the insulating material 3. After the external lead 5 and an electrode of the semiconductor device 1 have been connected by means of a metal thin wire 4, the underside of the heat sinking tub 2 is exposed, and sassembly is resin-sealed in such a way that the radiation of the heat generated by the power semiconductor device 1 is not disturbed. Because the size of the heat sinking tub can be made bigger than that of a conventional system by the length at the tip part of the external lead, this method has a good effect on the heat sinking.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電力用半導体素子を良好にマウント及びボンデ
ィングが行え、かつ熱放散を出来るだけ大きくできる多
数外部リードを有する電力用半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power semiconductor device having a large number of external leads, which allows power semiconductor elements to be mounted and bonded well, and which can maximize heat dissipation.

〔従来の技術〕[Conventional technology]

第2図の平面図に示す従来の電力用半導体装置において
、外部リードのうちのタブ用リード5aと放熱用タブ2
との接続方法として、タブ用リードフレーム5aの先端
部と放熱用タブ2とのカシメ構造、または高融点半田に
よる溶融法が使用されている。
In the conventional power semiconductor device shown in the plan view of FIG. 2, a tab lead 5a of the external leads and a heat radiation tab 2
As a connection method, a caulking structure between the tip of the tab lead frame 5a and the heat dissipation tab 2, or a melting method using high melting point solder is used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

最近の電力用半導体素子は高機能化と高集積化の要請に
より、外部リード本数が増大する傾向にある。このため
、外部リードのリード幅と厚みが小さく、かつリード回
隔が狭くなり、外部リードの取扱いが悪いとリード先端
が曲シやすく、第2図に示す半導体素子1の電極から、
金属細線4を外部リード5に接続する場合、外部リード
5の所定の位置からずれるため、金属細線が垂れて、他
の外部リード又は半導体素子とシ璽−トしたり、外部か
らの力により、金属細線が切れるという欠点がある。ま
たタブ用リード5aが放熱用タブ2とカシメまたは高融
点半田により接続されているため、カシメの角度不具合
またはマウント時の半田溶融により、外部リード5と放
熱用タブ2との相対位置がずれたシ、平行度に狂いが生
じるという欠点がある。
Due to demands for higher functionality and higher integration in recent power semiconductor devices, the number of external leads tends to increase. For this reason, the lead width and thickness of the external lead are small, and the lead interval is narrow, and if the external lead is handled poorly, the lead tip is likely to bend.
When connecting the thin metal wire 4 to the external lead 5, the thin metal wire 4 may deviate from the predetermined position of the external lead 5, causing the thin metal wire to sag and cause contact with other external leads or semiconductor elements, or due to external force. The disadvantage is that the thin metal wire can be cut. In addition, since the tab lead 5a is connected to the heat dissipation tab 2 by caulking or high melting point solder, the relative position of the external lead 5 and the heat dissipation tab 2 may shift due to an incorrect caulking angle or solder melting during mounting. However, there is a drawback that the parallelism is distorted.

〔問題点を解決するための手段〕[Means for solving problems]

前述の問題点に対し1本発明では、放熱用タブの周辺部
表面に形成された絶縁部材により、外部リードの先端部
を前記放熱用タブに絶縁した状態で保持し、この外部リ
ードと半導体素子の電極との間を金属細線で接続後、放
熱用タブの下面を露出させて樹脂封止をしている。
In order to solve the above-mentioned problems, in the present invention, the tip of the external lead is held insulated from the heat dissipation tab by an insulating member formed on the peripheral surface of the heat dissipation tab, and the external lead and the semiconductor element are connected to each other. After connecting with the electrode using a thin metal wire, the bottom surface of the heat dissipation tab is exposed and sealed with resin.

〔実施例〕〔Example〕

つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.

第1図(a)は本発明の一実施例の封止樹脂を省略した
平面図、同図(b)は断面図である。これらの図におい
て、放熱用タブ2の上面に半導体素子1がマウントされ
、半導体素子搭載部以外の放熱用タブ2上面に絶縁部材
3が形成され、外部リード5の先端部が絶縁部材3によ
り、放熱用タブ2上面に保持されている。そして、外部
リード5と半導体素子1の電極の間は金属細線4でもっ
て接続後、図示していない樹脂により、放熱用タブ2の
下面を露出させて電力用半導体素子1の発熱の放散を阻
害しないように樹脂封止されている。
FIG. 1(a) is a plan view of an embodiment of the present invention with the sealing resin omitted, and FIG. 1(b) is a sectional view. In these figures, the semiconductor element 1 is mounted on the upper surface of the heat dissipation tab 2, the insulating member 3 is formed on the upper surface of the heat dissipating tab 2 other than the semiconductor element mounting part, and the tip of the external lead 5 is connected to the insulating member 3. It is held on the upper surface of the heat dissipation tab 2. After connecting the external lead 5 and the electrode of the semiconductor element 1 with the thin metal wire 4, the lower surface of the heat dissipation tab 2 is exposed using a resin (not shown) to inhibit the dissipation of heat generated by the power semiconductor element 1. It is sealed with resin to prevent it from happening.

〔発明の効果〕〔Effect of the invention〕

上述の通セ、本発明は、外部リード先端部が放熱用タブ
上面に絶縁部材により固定されているため、外部リード
の位置ずれ及び曲シの不具合発生が防止され、マウント
及びボンディングの作業性の改善とショート不良低減を
計ることができる。
In contrast to the above, in the present invention, the tips of the external leads are fixed to the upper surface of the heat dissipation tab by an insulating member, which prevents the external leads from shifting and bending, and improves the workability of mounting and bonding. It is possible to measure improvements and reduce short-circuit defects.

また、従来よル、放熱用タブのサイズを外部リード先端
部の長さ分だけ大きく取れるので、熱放散にも良い効果
を与えることができる。
Further, since the size of the heat dissipation tab can be increased by the length of the tip of the external lead, it is possible to provide a good effect on heat dissipation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の一実施例の封止樹脂を省略した
平面図。同図(blは断面図、第2図は従来の電力用半
導体装置の封止樹脂を省略した平面図である0 1・・・・・・半導体素子、2・・・・・・放熱用タブ
、3・・・・・・絶縁部材、4・・・・・・金属細線、
5・・・・・・外部リード、5a・・・・・・タブ用リ
ード。 □ 閉口「 2 図
FIG. 1(a) is a plan view of an embodiment of the present invention with the sealing resin omitted. The same figure (bl is a cross-sectional view, and Fig. 2 is a plan view of a conventional power semiconductor device with the sealing resin omitted. 0 1...Semiconductor element, 2... Heat dissipation tab , 3... Insulating member, 4... Fine metal wire,
5...External lead, 5a...Tab lead. □ Closing “ 2 Figure

Claims (1)

【特許請求の範囲】[Claims]  半導体素子が搭載された放熱用タブと、この放熱用タ
ブの半導体素子搭載部以外の表面に形成された絶縁部材
と、この絶縁部材により前記放熱用タブと絶縁状態で先
端部が保持された外部リードと、前記半導体素子の電極
と外部リードの間を接続する金属細線と、前記半導体素
子を乞覆する封止体とを有する半導体装置。
a heat dissipation tab on which a semiconductor element is mounted; an insulating member formed on the surface of the heat dissipation tab other than the semiconductor element mounting portion; and an external portion whose tip is held insulated from the heat dissipation tab by the insulating member. A semiconductor device comprising a lead, a thin metal wire connecting between an electrode of the semiconductor element and an external lead, and a sealing body covering the semiconductor element.
JP25233986A 1986-10-22 1986-10-22 Semiconductor device Pending JPS63104458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25233986A JPS63104458A (en) 1986-10-22 1986-10-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25233986A JPS63104458A (en) 1986-10-22 1986-10-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63104458A true JPS63104458A (en) 1988-05-09

Family

ID=17235897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25233986A Pending JPS63104458A (en) 1986-10-22 1986-10-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63104458A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928364A (en) * 1982-08-09 1984-02-15 Sumitomo Electric Ind Ltd Lead frame
JPS5973077A (en) * 1982-10-21 1984-04-25 Nissan Motor Co Ltd Automatic coater

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5928364A (en) * 1982-08-09 1984-02-15 Sumitomo Electric Ind Ltd Lead frame
JPS5973077A (en) * 1982-10-21 1984-04-25 Nissan Motor Co Ltd Automatic coater

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227662A (en) * 1990-05-24 1993-07-13 Nippon Steel Corporation Composite lead frame and semiconductor device using the same

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