JPS61194751A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61194751A JPS61194751A JP60034347A JP3434785A JPS61194751A JP S61194751 A JPS61194751 A JP S61194751A JP 60034347 A JP60034347 A JP 60034347A JP 3434785 A JP3434785 A JP 3434785A JP S61194751 A JPS61194751 A JP S61194751A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- lead
- cap
- case member
- case
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はセラミック・ペースを用いたガラス封止パッケ
ージング構造忙関し、なかでもＥＦＲＯＭ（Ｅｒａｓａ
ｂｌｅ ａｎｄ Ｐｒｏｇｒａｍｍａｂｌｅ Ｒｅａ
ｄ ＯｎｌｙＭｅｍｏｒｙ ）用のパッケージング構造
を対象とする。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a glass-sealed packaging structure using a ceramic paste, and in particular to a glass-sealed packaging structure using a ceramic paste.
ble and Programmable Rea
d OnlyMemory) packaging structure.
紫外線照射でメモリ内容を消去して情報の書き換えを行
うＥＰＲＯＭのパッケージングには、ＤＩＬＧ（Ｄｕａ
ｌ ｉｎ １ｉｎｅ ｇｌａｓｓ）タイプのパッケー
ジで、上部キャップの中に紫外線を透過するガラス窓を
取りつけたものが使用され、たとえば（２）日立製作所
’８０ ＳＥＭＩ Ｃ０ＮＤＵＣＴＯＲＤＡＴＡＢＯＯ
Ｋ ＩＣメモリＰ、１２０−１２１ にその形状が記
載されている。DILG (Dua
(1 in 1ine glass) type package with a glass window that transmits ultraviolet rays in the upper cap is used, such as (2) Hitachi '80 SEMI CONDUCTORDATABOO.
Its shape is described in K IC memory P, 120-121.
第３図はＥＰＲＯＭ内蔵ＤＩＬＧパッケージの一例を斜
視図で示すものである。FIG. 3 is a perspective view of an example of a DILG package with a built-in EPROM.
１はセラミック・ペース、２はセラミックキャップ、３
は複数リード（アウターリード）である。1 is ceramic pace, 2 is ceramic cap, 3
is a multiple lead (outer lead).
セラミックキヤツプ２の上面にあるガラス窓４を通して
内蔵されたＥＰＲＯＭ素子５とワイヤを介して接続され
た複数リード（インナリード）３ａとがみられる。Through the glass window 4 on the top surface of the ceramic cap 2, a built-in EPROM element 5 and a plurality of leads (inner leads) 3a connected via wires can be seen.
第４図は上記パッケージの内部構造を示す断面図である
。ＥＰＲＯＭ素子の形成されたペレット５はセラミック
ペースの凹部６内にガラス７を介して固着され、複数の
リード３の内端側（インナリード）はセラミックペース
１とセラミックキャップ２との間に挾まれ、ガラス８を
介して封着されている。複数のリードの内端は細ワイヤ
１０を介してペレットの電極（パッド）に接続されてい
る。FIG. 4 is a sectional view showing the internal structure of the package. The pellet 5 on which the EPROM element is formed is fixed in the recess 6 of the ceramic paste via the glass 7, and the inner ends of the plurality of leads 3 are sandwiched between the ceramic paste 1 and the ceramic cap 2. , are sealed via glass 8. The inner ends of the plurality of leads are connected to electrodes (pads) of the pellet via thin wires 10.
上記セラミック・キャップ２は下面に凹部９を有する枠
状セラミック体と、粋の内側に嵌めこまれた透明ガラス
体４とからなっている。このセラミックキャップを製造
するには、セラミック材を型により成形し、１４００Ｃ
で焼結して、枠状セラミック体とし、その窓部に透明又
は紫外線透過できる半透明のガラス（たとえばコーニン
グ社製ガラス）を８００〜９００Ｃで接合するもので、
ガラスが特殊品であることとセラミックの窓に取付ける
ための加工手間とで、キャップの単価が高価なものとな
っていることが、本発明者の検討により明らかとなった
。The ceramic cap 2 consists of a frame-shaped ceramic body having a recess 9 on its lower surface, and a transparent glass body 4 fitted inside the cap. To manufacture this ceramic cap, the ceramic material is molded using a mold and heated to 1400C.
It is sintered to form a frame-shaped ceramic body, and transparent or semi-transparent glass that can transmit ultraviolet rays (for example, Corning glass) is bonded to the window at 800 to 900C.
The inventor's studies have revealed that the unit price of the cap is high due to the fact that the glass is a special product and the processing time required to attach it to a ceramic window.
本発明は上記した問題を克服するためになされたもので
ある。The present invention has been made to overcome the above-mentioned problems.
本発明の一つの目的は、原価の安いＥＰＲＯＭ用セラミ
ックパッケージング構造を得ることにある。One object of the present invention is to obtain a ceramic packaging structure for EPROM that is inexpensive.
本発明の他の一つの目的はキャップの構造を単純化し、
組立が容易なセラミツクツくツケージ構造を提供するこ
とにある。Another object of the invention is to simplify the structure of the cap,
To provide a ceramic shoe cage structure that is easy to assemble.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、上面に凹部を有するセラミックケース部材と
複数のリードが一体のリードフレームとして形成された
リード部材と、ＥＰＲＯＭ素子が形成された半導体ペレ
ットと、紫外線を透過できるガラスよりなるキャップ部
材とからなり、上記リード部材の内端部は上記ケース部
材の凹部にそって段状に曲げられて、上記ペレットとと
もにケース部材の凹部底面にガラス材を介して固着され
、上記キャップ部材は平らな板状に形成され、上記ケー
ス部材の上面にガラス材を介して封着されていることに
より、キャップの構造を単純化し、組立を容易にすると
ともに、パッケージングの原価を低減し、前記目的を達
成するものである。That is, it consists of a ceramic case member having a recessed portion on the upper surface, a lead member formed as an integral lead frame with a plurality of leads, a semiconductor pellet on which an EPROM element is formed, and a cap member made of glass that can transmit ultraviolet rays. The inner end of the lead member is bent into a step shape along the recess of the case member, and is fixed together with the pellet to the bottom of the recess of the case member via a glass material, and the cap member is formed into a flat plate shape. and is sealed to the upper surface of the case member via a glass material, thereby simplifying the structure of the cap, making assembly easier, and reducing packaging costs to achieve the above objectives. be.
第１図は本発明の一実施例を示すものであって、ＥＰＲ
ＯＭを内蔵した半導体装置の完成断面図である。FIG. 1 shows an embodiment of the present invention, in which the EPR
FIG. 2 is a completed cross-sectional view of a semiconductor device incorporating an OM.
１はセラミック・ケース部材で上面に凹部６が形成され
る。３はリード部材で複数のリードがたとえば左右対称
に配列されている。これらリードのケース内の部分をイ
ンナ・リード３ａ、ケース外の部分をアウタ・リード３
ｂと呼ぶ。上記リード部材は第５図（平面図）、第６図
（正面図）に示されるように複数のリードを左右対称に
配列し、周辺部をフレーム１１で繋いで一体のリードフ
レームに形成したものであり、インナリード３３部分は
セラミックケース部材の凹部にそって段状に曲げられる
とともに、アウターリード３ｂは先端が下方になるよう
にほぼ直角に曲げられた形態を有する。1 is a ceramic case member having a recess 6 formed on its upper surface. 3 is a lead member in which a plurality of leads are arranged symmetrically, for example. The parts of these leads inside the case are called the inner leads 3a, and the parts outside the case are called the outer leads 3.
Call it b. The above lead member is formed by arranging a plurality of leads symmetrically and connecting the peripheral parts with a frame 11 to form an integrated lead frame as shown in Fig. 5 (plan view) and Fig. 6 (front view). The inner lead 33 portion is bent into a step shape along the recessed portion of the ceramic case member, and the outer lead 3b is bent at a substantially right angle with the tip facing downward.
なお、このようなリード部材は、段のない平面状に形成
されたリードフレームを組立直前にアウタリードとイン
ナリードとを同時にプレス工程で折り曲げることにより
容易に形成できる、上記のリード部材は、第１図に示さ
れるようにその内端側３ａをケース部材の凹部底面にガ
ラス（低融点ガラス）７を介してたとえば４５０Ｃ程度
の温度で溶着し、リードの中央部分でケース部材の上面
にガラス８を介して溶着する。Note that such a lead member can be easily formed by simultaneously bending the outer lead and the inner lead in a press process immediately before assembling a lead frame formed into a planar shape without steps. As shown in the figure, the inner end 3a is welded to the bottom of the recess of the case member through a glass (low melting point glass) 7 at a temperature of, for example, about 450C, and a glass 8 is attached to the upper surface of the case member at the center of the lead. Welded through.
５はＥＰＲＯＭ素子の形成された半導体ペレットで、イ
ンナリード３ａと同じ低位置でケースの凹部底面にガラ
ス７を介して固着される。この状態でペレット５とイン
ナリード３ａとの間を金またはアルミニウムよりなる細
ワイヤ１０でワイヤボンディングされる。Reference numeral 5 denotes a semiconductor pellet on which an EPROM element is formed, and is fixed to the bottom of the recess of the case via glass 7 at the same low position as the inner lead 3a. In this state, wire bonding is performed between the pellet 5 and the inner lead 3a using a thin wire 10 made of gold or aluminum.
１１は透明ガラス又は紫外線を透過できる高純度アルミ
ナセラミックからなる平らな板状のキャップ部材である
。（第２図）このキャップ部材はリードを間に挾むよう
にしてセラミックケース上面にガラス８を介して封着さ
れる。Reference numeral 11 denotes a flat plate-shaped cap member made of transparent glass or high-purity alumina ceramic that can transmit ultraviolet rays. (FIG. 2) This cap member is sealed to the top surface of the ceramic case via glass 8 with the lead in between.
ガラス封着後にリードフレームのフレーム部分が切り取
られ、各リード間が切り離されてノくツケージング組立
が完了する。After glass sealing, the frame portion of the lead frame is cut out, and each lead is separated to complete the casing assembly.
このＥＰＲＯＭ半導体装置は、たとえば２５３７λの紫
外線を照射（Ｉ Ｓ Ｗ −ｓｅｃ ／ｃＩｒＬ２）す
ることによりメモリ内容を消去できる。消去されたビッ
トはプログラム電圧（＋２５Ｖ 、 ５０ｍｓ単一）く
ルス）により簡単に書き込みができる。The memory contents of this EPROM semiconductor device can be erased by irradiating it with ultraviolet light of 2537λ (I SW -sec/cIrL2), for example. Erased bits can be easily written using a program voltage (+25V, 50ms single pulse).
以上、実施例で述べた本発明によれば下記のように効果
を得ることができる。According to the present invention described in the examples above, the following effects can be obtained.
ｆｉｌ １７−ドの内端側を曲げて段状に形成するこ
とにより、セラミックケース部材の凹部内に内端部を位
置させることができ、ベレットと同じ低位置でワイヤボ
ンディングが可能となる。すなわち、Ａ召（アルミニウ
ム）ポールポンディングにすることで段部（ポスト）へ
のＡＡ線接続ができ、チップ間のループ作成が可能とな
り、組立速度も向上する。By bending the inner end of the fil 17-cord to form a stepped shape, the inner end can be positioned within the recess of the ceramic case member, and wire bonding can be performed at the same low position as the bullet. That is, by using aluminum pole bonding, it is possible to connect the AA wire to the step (post), making it possible to create a loop between chips, and improving the assembly speed.
（２）上記（１）により、ワイヤをケース部材の凹部内
におさめることができ、したがってキャップ部材には凹
部が不要で段なしのシート状（板状）のものを使用でき
、安価に製造できる。(2) Due to (1) above, the wire can be housed in the recess of the case member, so the cap member does not need a recess and can be made in the form of a sheet (plate) without steps, which can be manufactured at low cost. .
特に、ＥＰＲＯＭのように紫外線照射を必要とするパッ
ケージでは、従来のセラミックとガラスを組合せた複雑
な形状に対して原価を大幅に節減することができる。In particular, for packages such as EPROMs that require ultraviolet irradiation, the cost can be significantly reduced compared to the conventional complex shapes made by combining ceramic and glass.
（３）キャップ部材は平らな板を使用できるため、セラ
ミックパッケージの全体の厚みなうす（することが可能
となった。たとえば、従来のパッケージでは厚さ４．０
ｆｌのものがキヤツプ部材の凹部の深さ分０．５μｍだ
け低減できるから全体の厚みを３．５ｆｌ程度とするこ
とができる。その結果半導体装置の高密度化高集積化が
実現できる。(3) Since a flat plate can be used as the cap member, it has become possible to reduce the overall thickness of the ceramic package.For example, the thickness of the conventional package is 4.0 mm.
Since fl can be reduced by 0.5 μm corresponding to the depth of the concave portion of the cap member, the total thickness can be reduced to about 3.5 fl. As a result, higher density and higher integration of semiconductor devices can be achieved.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present invention has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. do not have.
たとえば、キャップ部材は透明ガラスなどの紫外線透過
材を使用する以外比、通常の紫外線の不透過性のセラミ
ック材や金属を使用し、ＥＰＲＯト４以外の半導体製品
を収納させる場合のパッケージングに使用した場合にも
、前記（１）〜（３）項で述べたのと同様の効果を得る
ことができる。For example, the cap member is made of a ceramic material or metal that is impermeable to normal ultraviolet rays, instead of using an ultraviolet transmitting material such as transparent glass, and is used for packaging when storing semiconductor products other than EPRO 4. Even in this case, the same effects as described in sections (1) to (3) above can be obtained.
本発明はセラミンクパッケージを用いた半導体装置であ
って薄型化を必要とする場合一般に適用することができ
る。The present invention can be generally applied to semiconductor devices using a ceramic package that need to be made thinner.
本発明は特にＤＩＬＧタイプＥＰＲＯＭに応用する場合
に最も有効である。The present invention is particularly effective when applied to DILG type EPROMs.
第１図は本発明の一実施例を示す半導体装置の断面図で
ある。
第２図は第１図で示した半導体装置におけるキャップ部
材の形状を示す斜視図である。
第３図はＤＩＬＧタイプＥＰＲＯＭの一例を示す斜面図
である。
第４図ｕＤＩＬＧタイプＥＰＲＯＭの従来例の断面図で
ある。
第５図は本発明の一実施例におけるリードフレームの形
状を示す平面図である。
第６図は本発明の一実施例の組立時におけるリードフレ
ームとケース部材の正面（断面）図である。
１・・・セラミック・ケース部材、２・・・セラミック
・キャップ部材、３・・・リード部材、４・・・窓ガラ
ス部、５・・・半導体ペレット、６・・・凹部、７，８
・・・ガラス、９・・・凹部、１０・・・ワイヤ、１１
・・・平板状キャップ。
第 １ 図
第 ３ 図
第 ４ 図FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention. 2 is a perspective view showing the shape of the cap member in the semiconductor device shown in FIG. 1. FIG. FIG. 3 is a perspective view showing an example of a DILG type EPROM. FIG. 4 is a sectional view of a conventional example of uDILG type EPROM. FIG. 5 is a plan view showing the shape of a lead frame in an embodiment of the present invention. FIG. 6 is a front (cross-sectional) view of the lead frame and case member during assembly according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic case member, 2... Ceramic cap member, 3... Lead member, 4... Window glass part, 5... Semiconductor pellet, 6... Recessed part, 7, 8
...Glass, 9...Concavity, 10...Wire, 11
...Flat cap. Figure 1 Figure 3 Figure 4
Claims (1)
のリードが一体のリードフレームとして形成されたリー
ド部材と、半導体素子が形成されたペレット及びキヤツ
プ部材とからなり、上記リード部材の内端側は上記ケー
ス部材の凹部にそって段状に曲げられて上記ペレットと
ともにケース部材の凹部底面にガラス材を介して固着さ
れ、上記キャップ部材は平らな板からなり、上記ケース
部材の上面にガラス材を介して封着されていることを特
徴とする半導体装置。 ２、上記半導体素子がＥＰＲＯＭであり、上記キャップ
部材が紫外線透過できるガラスである特許請求の範囲第
１項に記載の半導体装置。[Claims] 1. The ceramic case member is composed of a ceramic case member having a recessed portion on the upper surface, a lead member in which a plurality of leads are formed as an integrated lead frame, and a pellet and cap member on which a semiconductor element is formed; The inner end of the member is bent into a step shape along the recess of the case member and fixed together with the pellet to the bottom of the recess of the case member via a glass material, the cap member is made of a flat plate, and the cap member is made of a flat plate. A semiconductor device characterized in that the semiconductor device is sealed to the upper surface of the semiconductor device through a glass material. 2. The semiconductor device according to claim 1, wherein the semiconductor element is an EPROM, and the cap member is made of glass that can transmit ultraviolet rays.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60034347A JPS61194751A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60034347A JPS61194751A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61194751A true JPS61194751A (en) | 1986-08-29 |
Family
ID=12411604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60034347A Pending JPS61194751A (en) | 1985-02-25 | 1985-02-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61194751A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5122862A (en) * | 1989-03-15 | 1992-06-16 | Ngk Insulators, Ltd. | Ceramic lid for sealing semiconductor element and method of manufacturing the same |
| US5256901A (en) * | 1988-12-26 | 1993-10-26 | Ngk Insulators, Ltd. | Ceramic package for memory semiconductor |
| US6313525B1 (en) * | 1997-07-10 | 2001-11-06 | Sony Corporation | Hollow package and method for fabricating the same and solid-state image apparatus provided therewith |
| US6531334B2 (en) | 1997-07-10 | 2003-03-11 | Sony Corporation | Method for fabricating hollow package with a solid-state image device |
-
1985
- 1985-02-25 JP JP60034347A patent/JPS61194751A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5256901A (en) * | 1988-12-26 | 1993-10-26 | Ngk Insulators, Ltd. | Ceramic package for memory semiconductor |
| US5122862A (en) * | 1989-03-15 | 1992-06-16 | Ngk Insulators, Ltd. | Ceramic lid for sealing semiconductor element and method of manufacturing the same |
| US6313525B1 (en) * | 1997-07-10 | 2001-11-06 | Sony Corporation | Hollow package and method for fabricating the same and solid-state image apparatus provided therewith |
| US6531334B2 (en) | 1997-07-10 | 2003-03-11 | Sony Corporation | Method for fabricating hollow package with a solid-state image device |
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