JPS62145748A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS62145748A JPS62145748A JP60288127A JP28812785A JPS62145748A JP S62145748 A JPS62145748 A JP S62145748A JP 60288127 A JP60288127 A JP 60288127A JP 28812785 A JP28812785 A JP 28812785A JP S62145748 A JPS62145748 A JP S62145748A
- Authority
- JP
- Japan
- Prior art keywords
- lid
- semiconductor device
- base
- prepreg
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims 1
- 239000011521 glass Substances 0.000 description 16
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 238000002844 melting Methods 0.000 description 8
- 230000008018 melting Effects 0.000 description 8
- 238000007789 sealing Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000002991 molded plastic Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241000208140 Acer Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/50—Encapsulations or containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置、符に固体撮像素子等の光学的
な半導体素子を光特性を損なうことなく封止する封止構
造に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a sealing structure for sealing an optical semiconductor element such as a solid-state image sensor without impairing optical characteristics. .
第５図は従来のセラミックで封止された固体撮像素子の
断面図で、（１）はセラミック製のベース（２］に接着
材（３）によって固着された半導体チップ、（４）はリ
ードフレーム（５）とチップ（１）の端子を接続する金
線、（６］はセラミック製の蓋、（７）はリードフレー
ム（５）をベース（２）と蓋（６」に接着する低融点ガ
ラス、（８）は蓋（６）の開口部周囲にメタライズされ
た金属、（９］は金属キャップ、明は光透過用ガラス、
ａυは光透過用ガラスαｑと金属キャップ（９１とを接
着する低融点ガラスである。Figure 5 is a cross-sectional view of a conventional solid-state imaging device sealed with ceramic, in which (1) is a semiconductor chip fixed to a ceramic base (2) with an adhesive (3), and (4) is a lead frame. (5) and the gold wire that connects the terminals of the chip (1), (6) is the ceramic lid, and (7) is the low melting point glass that adheres the lead frame (5) to the base (2) and the lid (6). , (8) is a metallized metal around the opening of the lid (6), (9) is a metal cap, light is a light-transmitting glass,
aυ is a low melting point glass that adheres the light transmitting glass αq and the metal cap (91).
この従来のものを作るには、先ずベース（２）内に接着
材（３）によってチップ（１）を接着固定し、低融点ガ
ラス（７）によってリードフレーム（５１を約４００℃
前後でベース（２）に融解固着する。次にチップ（１）
の端子とリードフレーム（５）を金線１４】によってワ
イヤボンディングして後、！［６１を低融点ガラス（７
）でリードフレーム（５）をはさむように＃！ｄｙ固着
する。To make this conventional type, first, the chip (1) is adhesively fixed in the base (2) with an adhesive (3), and the lead frame (51 is heated to approximately 400°C using a low melting point glass (7).
It is melted and fixed to the base (2) at the front and back. Then the chip (1)
After wire bonding the terminal and lead frame (5) with gold wire 14],! [61 is a low melting point glass (7
) to sandwich the lead frame (5) with #! dy stick.
ここで蓋（６）の開口部には金属（８）を予めメタライ
ズしておく。Here, the opening of the lid (6) is previously metallized with metal (8).
次に金属キャップ（９）に低融点ガラス（１刀で光透過
用のガラス四を接着したものを蓋（６）の開口部にメタ
ライズした金楓（８）上に浴接によって耐層し外気と完
全に遮断する。Next, a metal cap (9) with a low melting point glass (glass 4 for light transmission glued with one knife) is coated on the metalized gold maple (8) at the opening of the lid (6) by bath welding to make it resistant to outside air. and completely cut it off.
この従来のものでは、封止用の構成材料としてセラミッ
クと金属を生体に用いているため低融点ガラス（７］を
融解固着する工程および金属キャップ（９）に低融点ガ
ラスσ〃によって光透過用のガラス四を接着する工程を
含む等製造工程が複雑で量産性に問題があった。In this conventional product, since ceramic and metal are used in the living body as the constituent materials for sealing, the process of melting and fixing the low melting point glass (7) and the low melting point glass σ〃 in the metal cap (9) are used for light transmission. The manufacturing process was complicated, including the process of gluing the four glasses together, and there were problems with mass production.
さらに、チップ（１）の耐熱性が劣ることから金属キャ
ップ（９）をメタライズ金属（８）上に溶接する際チッ
プへの熱の影響を少なくするため、金属キャップ（９）
の寸法を大きくしなければならず、封止形状が大きくな
る欠点があった。Furthermore, since the heat resistance of the chip (1) is poor, when welding the metal cap (9) onto the metallized metal (8), the metal cap (9) is
This has the disadvantage that the dimensions of the sealing device must be increased, resulting in a larger sealing shape.
この発明はこのような従来のもの＼問題点を解決するた
めになされたもので、量産性に優れ、さらに封止形状を
小さくした半導体装置を得ることを目的とする。The present invention has been made to solve the problems of the prior art, and aims to provide a semiconductor device that is excellent in mass production and has a smaller sealed shape.
この発明に係る半導体装置は、半導体素子が装着される
ベース部材と透明部を有する蓋部材をこれら各部材に予
め取付けられたプリプレグ部材を介して熱圧着したもの
である。In the semiconductor device according to the present invention, a base member on which a semiconductor element is mounted and a lid member having a transparent portion are thermocompression bonded to each of these members via prepreg members attached in advance.
この発明における半導体装置では、封止構造が小形で簡
単になると共に製作が容易となる。In the semiconductor device according to the present invention, the sealing structure is small and simple, and manufacturing is easy.
以下この発明の一実施例を第１図〜第４図にもとづいて
説明する〇
即ち第１図〜第４図において、艶はトランスファ成形さ
れたプラスチック製のベース、口は同じくトランスファ
成形されたプラスチック製の蓋、α４１Ｃ１５はいずれ
も粉末樹脂とガラスクロスとを真空プレスして形成した
後、第８図および第４図に示す如く切断されたプリプレ
グ部材、Ｏ４０はベース（６）と蓋賂との間に形成され
た空間である。（５）はチップ（１）を固定する長方形
のダイパッド団とダイパッドｉ５刀の周囲に細線上に配
置されたリード線１５ｚを有Ｔるリードフレームである
。An embodiment of the present invention will be described below based on FIGS. 1 to 4. In FIGS. 1 to 4, the gloss is a transfer-molded plastic base, and the mouth is also a transfer-molded plastic α41C15 is a prepreg member that is formed by vacuum pressing powdered resin and glass cloth, and then cut as shown in Figures 8 and 4. It is the space formed between. (5) is a lead frame having a rectangular die pad group for fixing the chip (1) and a lead wire 15z arranged in a thin line around the die pad i5.
なお、その池の構成は第５図に示す従来のものと同様で
あるので説明を省略する。Note that the configuration of the pond is similar to the conventional one shown in FIG. 5, so a description thereof will be omitted.
この装置を作るには、先ず第２図に示すようにトランス
ファ成形により光透過用ガラス０Ｑを有する蓋叫とベー
ス（２）を作る。次にガラスクロスと樹脂粉末とを１２
０１Ｅに加熱した真空プレスによりＢステージのプリプ
レグ部材を作る。ここでＢステージのプリプレグ部材は
常温では硬く温度を上げると軟化し硬化するものである
。次ＧここのＢステージのプリプレグ部材を打抜金属に
よって第８図に示すように角形のプリプレグ部材Ｃ１４
１と第４図に示すように角形に切断した内面をさらに角
形に切断してプリプレグ部材（至）とを形成する。これ
らのプリプレグ部材ａ４０Ｇを夫々第２図に示すように
ベース四の上部と蓋四の下部に熱融層する。To make this device, first, as shown in FIG. 2, a lid and base (2) having a light transmitting glass 0Q are made by transfer molding. Next, add glass cloth and resin powder for 12 minutes.
A B-stage prepreg member is made using a vacuum press heated to 01E. Here, the B-stage prepreg member is hard at room temperature and softens and hardens when the temperature is raised. Next G The prepreg member of the B stage here is stamped with metal to form a rectangular prepreg member C14 as shown in Fig. 8.
As shown in FIG. 1 and FIG. 4, the inner surface cut into a square shape is further cut into a square shape to form a prepreg member. These prepreg members a40G are placed in a thermal melt layer on the upper part of the base 4 and the lower part of the lid 4, respectively, as shown in FIG.
次にリードフレーム（５）のダイパッド伸υにチップ（
１）をダイボンディングし、チップ（１）とり−１Ｉ２
とを金線（４）によってワイヤボンディングする０次に
このように構成したリードフレーム（５）を第１図に示
すようにプリプレグ部材Ｃ１４１０ｆ９を熱融層したベ
ース四と蓋賂ではさむようにして１８０′ｃで熱圧着し
空間叫を形成し外気と完全に遮断する。Next, the chip (
1) is die-bonded, and the chip (1) is taken -1I2.
As shown in FIG. 1, the lead frame (5) constructed in this manner is sandwiched between the base 4 made of a heat-fused layer of prepreg member C1410f9 and the lid 180'. c) to form a space seal and completely isolate it from the outside air.
このように構成されたものでは、従来のセラミツク封止
のものに比較して外形が約８になる。またベースおよび
蓋にプラスチックを用いたので量産性に優れている。With this structure, the outer diameter is about 8 mm compared to the conventional ceramic seal. Also, since plastic is used for the base and lid, it is suitable for mass production.
なお、ここでは固体撮像素子について説明したが、必ず
しもこれに限られるものでなく、例えば紫外線消去形読
み出し専用メモリ（以下１１７ＦＲＯＭという）の封止
Ｇこも同様に適用できる。ＥＦＲＯＭの場合は紫外線透
過用ガラスに石英ガラス、硼珪酸ガラスを用いる外は固
体撮像素子と同様である。Although a solid-state image sensor has been described here, the present invention is not necessarily limited to this, and can be similarly applied to, for example, the sealing of an ultraviolet erasable read-only memory (hereinafter referred to as 117FROM). In the case of an EFROM, it is similar to a solid-state image pickup device except that quartz glass or borosilicate glass is used as the glass for transmitting ultraviolet rays.
上記のようにこの発明による半導体装置は、ベース部材
と蓋部材をプリプレグ部材を介して熱圧着するようにし
たもので、装置が小形になると同時に製作が容易となる
。As described above, in the semiconductor device according to the present invention, the base member and the lid member are bonded together by thermocompression via the prepreg member, which makes the device smaller and easier to manufacture.
第１図〜第４図はいずれもこの発明の一実施例を示すも
ので、第１図は側断面図、第２図は要部分解側面図、第
８図および第４図は要部斜視図、第５図は従来のこの種
半導体装置の側断面図である。
図中、（１）は半導体チップ、＋２） ｆｌｉｌはベー
ス、（６］賂は蓋、（５）はリードフレーム、αｑは光
透過用ガラス、Ｑ４）αＧはプリプレグ部材である。
尚、図中同一符号は同−士たは相当部分を示す。Figures 1 to 4 all show an embodiment of the present invention, with Figure 1 being a sectional side view, Figure 2 being an exploded side view of the main part, and Figures 8 and 4 being a perspective view of the main part. FIG. 5 is a side sectional view of a conventional semiconductor device of this type. In the figure, (1) is a semiconductor chip, +2) flil is a base, (6) is a lid, (5) is a lead frame, αq is a light transmitting glass, and Q4) αG is a prepreg member. Note that the same reference numerals in the drawings indicate the same or corresponding parts.
Claims (4)
する蓋部材とを各部材に予め取付けられたプリプレグ部
材を介して熱圧着してなる半導体装置。(1) A semiconductor device formed by thermocompression bonding a base member on which a semiconductor element is mounted and a lid member having a transparent portion through prepreg members attached to each member in advance.
グ部材間に半導体素子のリード部を挾んで熱圧着するよ
うにしてなる特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the lead portion of the semiconductor element is sandwiched between prepreg members attached to the base member and the lid member and bonded by thermocompression.
範囲第１項または第２項記載の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein the prepreg member is a thermosetting resin.
特許請求の範囲第１項乃至第３項のいずれか１項記載の
半導体装置。(4) The semiconductor device according to any one of claims 1 to 3, wherein the base member and the lid member are made of plastic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288127A JPS62145748A (en) | 1985-12-19 | 1985-12-19 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60288127A JPS62145748A (en) | 1985-12-19 | 1985-12-19 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62145748A true JPS62145748A (en) | 1987-06-29 |
Family
ID=17726156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60288127A Pending JPS62145748A (en) | 1985-12-19 | 1985-12-19 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62145748A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324888A (en) * | 1992-10-13 | 1994-06-28 | Olin Corporation | Metal electronic package with reduced seal width |
| US6100583A (en) * | 1998-02-27 | 2000-08-08 | Nec Corporation | Semiconductor device containing semiconductor element in package |
| US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54129880A (en) * | 1978-03-02 | 1979-10-08 | Nec Corp | Manufacture for semiconductor device |
-
1985
- 1985-12-19 JP JP60288127A patent/JPS62145748A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54129880A (en) * | 1978-03-02 | 1979-10-08 | Nec Corp | Manufacture for semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5324888A (en) * | 1992-10-13 | 1994-06-28 | Olin Corporation | Metal electronic package with reduced seal width |
| US5399805A (en) * | 1992-10-13 | 1995-03-21 | Olin Corporation | Metal electronic package with reduced seal width |
| US6100583A (en) * | 1998-02-27 | 2000-08-08 | Nec Corporation | Semiconductor device containing semiconductor element in package |
| KR100309305B1 (en) * | 1998-02-27 | 2001-09-26 | 가네꼬 히사시 | Semiconductor device containing semiconductor element in package |
| CN1091299C (en) * | 1998-02-27 | 2002-09-18 | 日本电气株式会社 | Semiconductor device containing semiconductor element in package |
| US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
| US6420204B2 (en) | 1999-06-03 | 2002-07-16 | Amkor Technology, Inc. | Method of making a plastic package for an optical integrated circuit device |
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