JPH0513642A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0513642A JPH0513642A JP3185304A JP18530491A JPH0513642A JP H0513642 A JPH0513642 A JP H0513642A JP 3185304 A JP3185304 A JP 3185304A JP 18530491 A JP18530491 A JP 18530491A JP H0513642 A JPH0513642 A JP H0513642A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- chip
- semiconductor device
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置に関し、特
に樹脂封止型の半導体装置に用いられるリードフレーム
の構造の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of the structure of a lead frame used in a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】図５は従来の樹脂封止型半導体装置のリ
ードフレーム面を示す平面図であり、図６は図５に示す
Ｃ−Ｃ′線での断面図である。図において、５は半導体
チップ、８は該チップ５上のボンディングパッド、６は
上記チップ５がのっているダイパッドであり、チップ５
はロウ材１０によりダイパッド６上に固定されている。
７はダイパッド６を支持する宙吊りリードである。１は
半導体装置を形成する樹脂、３ｂはインナーリードであ
り、上記樹脂１内部のリードフレームを示す。４はイン
ナーリード３ｂ上に設けられたロックバーである。２は
リードで、上記樹脂１の外部に出ているリードフレーム
を示す。９はインナーリード３ｂとボンディングパッド
８を接続するワイヤである。Ｌ′はリード間隔を示す。
半導体装置を組み立てる場合、ダイパッド６にロウ材１
０をのせ、ダイパッド６を高温にしてロウ材１０を溶融
させ、その状態でチップ５をロウ材１０の上にのせてチ
ップ５とダイパッド６とを密着させる。次に、チップ５
上のボンディングパッド８とインナーリード３ｂとをワ
イヤ９によりワイヤボンドする。次に樹脂１で樹脂封止
し、外部のリード２を整形する。2. Description of the Related Art FIG. 5 is a plan view showing a lead frame surface of a conventional resin-sealed semiconductor device, and FIG. 6 is a sectional view taken along line CC 'shown in FIG. In the figure, 5 is a semiconductor chip, 8 is a bonding pad on the chip 5, and 6 is a die pad on which the chip 5 is mounted.
Is fixed on the die pad 6 by the brazing material 10.
Reference numeral 7 is a suspended lead that supports the die pad 6. Reference numeral 1 denotes a resin forming a semiconductor device, 3b denotes an inner lead, which is a lead frame inside the resin 1. Reference numeral 4 is a lock bar provided on the inner lead 3b. Reference numeral 2 denotes a lead, which is a lead frame protruding outside the resin 1. A wire 9 connects the inner lead 3b and the bonding pad 8. L'indicates a lead interval.
When assembling a semiconductor device, the brazing material 1 is attached to the die pad 6.
0 is placed, the die pad 6 is heated to a high temperature to melt the brazing material 10, and in this state, the chip 5 is placed on the brazing material 10 to bring the chip 5 and the die pad 6 into close contact with each other. Next, tip 5
The upper bonding pad 8 and the inner lead 3b are wire-bonded with the wire 9. Next, resin 1 is resin-sealed and the external leads 2 are shaped.
【０００３】この樹脂封止された状態において、インナ
ーリード３ｂ上にはロックバー４があるので、樹脂１外
部からのリード引っ張り強度が保たれることとなり、リ
ード抜けを防止できる。In this resin-sealed state, since the lock bar 4 is provided on the inner lead 3b, the lead pulling strength from the outside of the resin 1 is maintained, and the lead drop can be prevented.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されており、リード抜け防止のためにロ
ックバーを設けなければならず、ロックバーの分だけリ
ード間隔（図５に示す間隔Ｌ′）を広げなければならな
いので、リードピッチを狭くできず、このためパッケー
ジの外形寸法を小さくできないという問題点があった。
この発明は上記のような問題点を解消するためになされ
たもので、リード間隔が狭くでき、パッケージの外形寸
法を小さくすることのできる半導体装置を得ることを目
的とする。The conventional semiconductor device is configured as described above, and the lock bar must be provided to prevent the lead from coming off, and the lead interval is the same as the lock bar (see FIG. 5). Since the space L ') must be widened, there is a problem that the lead pitch cannot be narrowed, and thus the external dimensions of the package cannot be reduced.
The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device in which a lead interval can be narrowed and a package outer dimension can be reduced.
【０００５】[0005]
【課題を解決するための手段】この発明に係る半導体装
置は、リードフレームの樹脂封止内のインナーリードに
屈曲部分を有するものである。A semiconductor device according to the present invention has a bent portion in an inner lead inside a resin encapsulation of a lead frame.
【０００６】[0006]
【作用】この発明においては、樹脂封止内のインナーリ
ードに屈曲部分を有するので、リード抜けが防止でき、
従ってロックバーを必要としないため、リード間隔が狭
くできる。In the present invention, since the inner lead in the resin encapsulation has the bent portion, the lead drop can be prevented,
Therefore, since the lock bar is not required, the lead interval can be narrowed.
【０００７】[0007]
【実施例】図１はこの発明の一実施例による樹脂封止型
半導体装置のリードフレーム面を示す平面図であり、図
２は図１に示すＡ−Ａ′線での断面図である。図におい
て、図５，図６と同一符号は同一又は相当部分を示し、
３ａはインナーリードであり、樹脂１内部のリードフレ
ームを示す。１１はインナーリード３ａに設けられた屈
曲部である。Ｌはリード間隔を示す。1 is a plan view showing a lead frame surface of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA 'shown in FIG. In the figure, the same reference numerals as those in FIGS. 5 and 6 denote the same or corresponding parts,
Reference numeral 3a denotes an inner lead, which is a lead frame inside the resin 1. Reference numeral 11 is a bent portion provided on the inner lead 3a. L indicates a lead interval.
【０００８】図１，図２に示す半導体装置を組み立てる
場合、従来と同様に、まずダイパッド６にロウ材１０を
のせ、ダイパッド６を高温にしてロウ材１０を溶融さ
せ、その状態でチップ５をロウ材１０の上にのせてチッ
プ５とダイパッド６とを密着させる。次に、チップ５上
のボンディングパッド８とインナーリード３ａとをワイ
ヤ９によりワイヤボンドする。次にインナーリード３ａ
の屈曲部１１を含め樹脂１により樹脂封止し、外部のリ
ード２を整形する。When assembling the semiconductor device shown in FIGS. 1 and 2, as in the conventional case, first, the brazing material 10 is placed on the die pad 6, the die pad 6 is heated to a high temperature, and the brazing material 10 is melted. The chip 5 and the die pad 6 are placed in close contact with each other by being placed on the brazing material 10. Next, the bonding pad 8 on the chip 5 and the inner lead 3a are wire-bonded with the wire 9. Next, the inner lead 3a
The outer lead 2 is shaped by resin-sealing with the resin 1 including the bent portion 11.
【０００９】このように本実施例では、インナーリード
３ａに屈曲部１１を有するので、樹脂封止された状態に
おいて、上記屈曲部１１により樹脂外部からのリード引
っ張り強度を保つことができ、リード抜けを防止するこ
とができる。従ってロックバーを必要としないので、リ
ード間隔Ｌを広くする必要がなく、リードピッチを狭く
できるので、パッケージの外形寸法を小さくできる。As described above, in this embodiment, since the inner lead 3a has the bent portion 11, the bent portion 11 can maintain the lead tensile strength from the outside of the resin in the resin-sealed state, and the lead can be pulled out. Can be prevented. Therefore, since the lock bar is not required, it is not necessary to widen the lead interval L and the lead pitch can be narrowed, so that the package outer dimension can be reduced.
【００１０】図３は本発明の他の実施例による半導体装
置のリードフレーム面の平面図であり、図４は図３に示
すＢ−Ｂ′線での断面図である。上記実施例では、ダイ
パッド沈めを行っていないものを示したが、本実施例は
ダイパッド沈めを行ったものに適用したものであり、こ
の場合チップ５上面のボンディングパッド８の部分とイ
ンナーリード３ａの屈曲部より内側の部分を同一の高さ
としている。FIG. 3 is a plan view of a lead frame surface of a semiconductor device according to another embodiment of the present invention, and FIG. 4 is a sectional view taken along line BB 'shown in FIG. In the above embodiment, the die pad is not submerged, but this embodiment is applied to the die pad submerged. In this case, the bonding pad 8 portion on the upper surface of the chip 5 and the inner lead 3a are not formed. The part inside the bent part has the same height.
【００１１】[0011]
【発明の効果】以上のようにこの発明に係る半導体装置
によれば、樹脂封止内のインナーリードが屈曲部分を有
するので、リード抜けを防止することができ、従ってロ
ックバーを必要とせず、リード間隔を狭くでき、パッケ
ージの外形寸法を小さくできるという効果がある。As described above, according to the semiconductor device of the present invention, since the inner lead in the resin encapsulation has the bent portion, it is possible to prevent the lead from coming off, and therefore, the lock bar is not required, There is an effect that the lead interval can be narrowed and the package outer dimension can be reduced.
【図１】この発明の一実施例による半導体装置のリード
フレーム面の平面図。FIG. 1 is a plan view of a lead frame surface of a semiconductor device according to an embodiment of the present invention.
【図２】図１に示すＡ−Ａ′線での断面図。FIG. 2 is a sectional view taken along the line AA ′ shown in FIG.
【図３】この発明の他の実施例による半導体装置のリー
ドフレーム面の平面図。FIG. 3 is a plan view of a lead frame surface of a semiconductor device according to another embodiment of the present invention.
【図４】図３に示すＢ−Ｂ′線での断面図。FIG. 4 is a cross-sectional view taken along line BB ′ shown in FIG.
【図５】従来の半導体装置のリードフレーム面の平面
図。FIG. 5 is a plan view of a lead frame surface of a conventional semiconductor device.
【図６】図５に示すＣ−Ｃ′線での断面図。6 is a cross-sectional view taken along the line CC ′ shown in FIG.
１ 樹脂 ２ リード ３ａ インナーリード ５ チップ ６ ダイパッド ７ 宙吊りリード ８ ボンディングパッド ９ ワイヤ １０ ロウ材 １１ 屈曲部 1 resin 2 leads 3a Inner lead 5 chips 6 die pad 7 suspended leads 8 Bonding pad 9 wires 10 brazing material 11 Bend
Claims (2)
プ上のボンディングパッドとリードフレームの屈曲部分
を有するインナーリードとをワイヤにより接続し、樹脂
封止してなることを特徴とする半導体装置。1. A semiconductor device comprising a chip fixed on a die pad, a bonding pad on the chip and an inner lead having a bent portion of a lead frame connected by a wire, and resin-sealed.
徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the bent portion of the inner lead has a step shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3185304A JPH0513642A (en) | 1991-06-28 | 1991-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3185304A JPH0513642A (en) | 1991-06-28 | 1991-06-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0513642A true JPH0513642A (en) | 1993-01-22 |
Family
ID=16168519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3185304A Pending JPH0513642A (en) | 1991-06-28 | 1991-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0513642A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015068565A1 (en) * | 2013-11-08 | 2015-05-14 | アイシン精機株式会社 | Semiconductor device |
-
1991
- 1991-06-28 JP JP3185304A patent/JPH0513642A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015068565A1 (en) * | 2013-11-08 | 2015-05-14 | アイシン精機株式会社 | Semiconductor device |
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