JPS59131158U - Chippukiyariya - Google Patents
ChippukiyariyaInfo
- Publication number
- JPS59131158U JPS59131158U JP1983024333U JP2433383U JPS59131158U JP S59131158 U JPS59131158 U JP S59131158U JP 1983024333 U JP1983024333 U JP 1983024333U JP 2433383 U JP2433383 U JP 2433383U JP S59131158 U JPS59131158 U JP S59131158U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic layer
- chip carrier
- layer
- chippukiyariya
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来公知のチップキャリヤーの断面図、第2図
は本考案の一実施例を示す断面図である。
21・・・第1のセラミック層、22・・・チップ接続
用配線層、23・・・第2のセラミック層、24・・・
封止用導体層、25・・・第3のセラミック層、26・
・・外部電極配線、27・・・集積回路チップ、28・
・・チップ接続部、29・・・キャップ、30・・・封
止部分。FIG. 1 is a sectional view of a conventionally known chip carrier, and FIG. 2 is a sectional view showing an embodiment of the present invention. 21... First ceramic layer, 22... Wiring layer for chip connection, 23... Second ceramic layer, 24...
Sealing conductor layer, 25...Third ceramic layer, 26.
・・External electrode wiring, 27・・Integrated circuit chip, 28・
...Chip connection part, 29...Cap, 30...Sealing part.
Claims (1)
ミック層の積層体と封止キャップよりなるチップキャリ
ヤーにおいて、第1のセラミック層上にフェースダウン
接続用集積回路が接続可能な配線層を形成し、第2のセ
ラミック層上に、第3のセラミック層に周囲をかこまれ
た封止面を形成したことを特徴とするチップキャリヤー
。In a chip carrier comprising a laminate of a first ceramic layer, a second ceramic layer, a third ceramic layer, and a sealing cap, a wiring layer to which an integrated circuit for face-down connection can be connected is provided on the first ceramic layer. A chip carrier comprising a sealing surface formed on the second ceramic layer and surrounded by a third ceramic layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983024333U JPS59131158U (en) | 1983-02-23 | 1983-02-23 | Chippukiyariya |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983024333U JPS59131158U (en) | 1983-02-23 | 1983-02-23 | Chippukiyariya |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59131158U true JPS59131158U (en) | 1984-09-03 |
Family
ID=30155377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983024333U Pending JPS59131158U (en) | 1983-02-23 | 1983-02-23 | Chippukiyariya |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59131158U (en) |
-
1983
- 1983-02-23 JP JP1983024333U patent/JPS59131158U/en active Pending
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