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JPS59176154U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS59176154U
JPS59176154U JP6990983U JP6990983U JPS59176154U JP S59176154 U JPS59176154 U JP S59176154U JP 6990983 U JP6990983 U JP 6990983U JP 6990983 U JP6990983 U JP 6990983U JP S59176154 U JPS59176154 U JP S59176154U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
metallized layer
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6990983U
Other languages
Japanese (ja)
Inventor
祐司 藤田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP6990983U priority Critical patent/JPS59176154U/en
Publication of JPS59176154U publication Critical patent/JPS59176154U/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のハイブリッドICの平面図、第2図は本
考案の一実施例の平面図、第3図a、  bは夫々本考
案のリード部の構造を示す側面図である。 1・・・・・・外部リード(金属体)、10・・・・・
・樹脂、11・・・・・・基板、12・・・・・・メタ
ライズ層、13・・・・・・テーパ。
FIG. 1 is a plan view of a conventional hybrid IC, FIG. 2 is a plan view of an embodiment of the present invention, and FIGS. 3a and 3b are side views showing the structure of the lead portion of the present invention. 1... External lead (metal body), 10...
- Resin, 11... Substrate, 12... Metallized layer, 13... Taper.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数個必要とされる外部引出しリード部をメタライズ層
で形成し、このメタライズ層は部分的に離間していない
装置の絶縁基板上に設けられている事を特徴とする混成
集積回路装置。
A hybrid integrated circuit device characterized in that a plurality of required external lead portions are formed of a metallized layer, and the metallized layer is provided on an insulating substrate of the device that is not partially spaced apart.
JP6990983U 1983-05-11 1983-05-11 Hybrid integrated circuit device Pending JPS59176154U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6990983U JPS59176154U (en) 1983-05-11 1983-05-11 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6990983U JPS59176154U (en) 1983-05-11 1983-05-11 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS59176154U true JPS59176154U (en) 1984-11-24

Family

ID=30200057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6990983U Pending JPS59176154U (en) 1983-05-11 1983-05-11 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59176154U (en)

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