[go: up one dir, main page]

JPS59131158U - チツプキヤリヤ− - Google Patents

チツプキヤリヤ−

Info

Publication number
JPS59131158U
JPS59131158U JP1983024333U JP2433383U JPS59131158U JP S59131158 U JPS59131158 U JP S59131158U JP 1983024333 U JP1983024333 U JP 1983024333U JP 2433383 U JP2433383 U JP 2433383U JP S59131158 U JPS59131158 U JP S59131158U
Authority
JP
Japan
Prior art keywords
ceramic layer
chip carrier
layer
chippukiyariya
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983024333U
Other languages
English (en)
Inventor
草野　正昭
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1983024333U priority Critical patent/JPS59131158U/ja
Publication of JPS59131158U publication Critical patent/JPS59131158U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は従来公知のチップキャリヤーの断面図、第２図
は本考案の一実施例を示す断面図である。 ２１・・・第１のセラミック層、２２・・・チップ接続
用配線層、２３・・・第２のセラミック層、２４・・・
封止用導体層、２５・・・第３のセラミック層、２６・
・・外部電極配線、２７・・・集積回路チップ、２８・
・・チップ接続部、２９・・・キャップ、３０・・・封
止部分。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１のセラミック層と第２のセラミック層と第３のセラ
    ミック層の積層体と封止キャップよりなるチップキャリ
    ヤーにおいて、第１のセラミック層上にフェースダウン
    接続用集積回路が接続可能な配線層を形成し、第２のセ
    ラミック層上に、第３のセラミック層に周囲をかこまれ
    た封止面を形成したことを特徴とするチップキャリヤー
    。
JP1983024333U 1983-02-23 1983-02-23 チツプキヤリヤ− Pending JPS59131158U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983024333U JPS59131158U (ja) 1983-02-23 1983-02-23 チツプキヤリヤ−

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983024333U JPS59131158U (ja) 1983-02-23 1983-02-23 チツプキヤリヤ−

Publications (1)

Publication Number Publication Date
JPS59131158U true JPS59131158U (ja) 1984-09-03

Family

ID=30155377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983024333U Pending JPS59131158U (ja) 1983-02-23 1983-02-23 チツプキヤリヤ−

Country Status (1)

Country Link
JP (1) JPS59131158U (ja)

Similar Documents

Publication Publication Date Title
JPS5858342U (ja) 混成集積回路
JPS59131158U (ja) チツプキヤリヤ−
JPS58120662U (ja) チツプキヤリヤ−
JPS58109254U (ja) フエ−スダウン接続形チツプ用チツプキヤリヤ−
JPS606242U (ja) 混成集積回路
JPS58168141U (ja) リ−ドレスパツケ−ジ
JPS58159756U (ja) 集積回路装置
JPS609226U (ja) 半導体の実装用パツケ−ジ
JPS60169860U (ja) 混成集積回路
JPS59107155U (ja) 半導体回路装置
JPS59104535U (ja) 半導体装置
JPS5895054U (ja) 半導体装置
JPS5866647U (ja) 混成集積回路の封止構造
JPS6011471U (ja) 混成集積回路装置
JPS5866648U (ja) 混成集積回路
JPS6081674U (ja) セラミツク混成集積回路装置
JPS5881949U (ja) 集積回路基板
JPS6142861U (ja) 半導体装置
JPS6037240U (ja) 混成集積回路
JPS6037273U (ja) 混成集積回路
JPS59143051U (ja) 集積回路装置
JPS59176154U (ja) 混成集積回路装置
JPS606231U (ja) 混成集積回路の構造
JPS6078139U (ja) 混成集積回路装置
JPS5858343U (ja) 混成集積回路